Abstract: A method of controlling a power field-effect transistor includes controlling a plurality of different phases of a gate-to-source voltage of the power field-effect transistor. Without comparing the gate-to-source voltage of the power field effect transistor to a plurality of reference voltages, the method includes discriminating between the different phases of the gate-to-source voltage based on the plurality of reference voltages. At least one of the plurality of reference voltages is based on a threshold voltage of at least one field-effect transistor.

Abstract: Active post-power loss discharging of capacitors is provided. In an integrated circuit having a startup behavior depending on a capacitor voltage, a discharge transistor is provided to discharge the capacitor. A power-down discharger actively drives the discharge transistor after a power supply voltage drops below a threshold. The power-down discharger may include, or be coupled to, an internal capacitance that is charged when the power supply voltage is above the threshold, thereby storing sufficient energy for later driving of the discharge transistor. A diode is employed to ensure that the loss of power does not drain away the needed energy until after the discharge has been completed. One illustrative discharging method includes: sensing a condition indicative of power supply voltage loss for an integrated circuit; and actively driving the discharge transistor into a conducting state. The sensing may include driving the discharge transistor inversely to a signal from a pin.

Abstract: A reverse-current-prevention circuit includes a reverse-current-prevention transistor of a P-channel MOS transistor inserted between an input terminal supplied with a power supply voltage and an output stage transistor of a P-channel MOS transistor providing an output voltage from an output terminal, and a reverse-current-prevention controller configured to turn the reverse-current-prevention transistor from on to off according to exceedance of the output voltage to the power supply voltage. The reverse-current-prevention controller includes a first transistor of a depletion type P-channel MOS transistor having a source and gate respectively connected to the output terminal and the input terminal, and a second transistor of a depletion type P-channel MOS transistor having a source and gate respectively connected to a drain of the first transistor and a gate of the reverse-current-prevention transistor, and a drain grounded.

Abstract: An apparatus is disclosed. In some examples, the apparatus comprises a display panel comprising a plurality of display pixels. In some examples, the apparatus comprises a plurality of temperature sensors disposed at different portions the display panel, wherein the plurality of temperature sensors comprise ratioed pairs of thin film transistors and the ratioed pairs of thin film transistors are formed on the display panel. In some examples, the apparatus comprises control circuitry for changing illumination properties of the plurality of display pixels based on changes is temperature detected by a proximate temperature sensor of the plurality of temperature sensors. In some examples, the ratioed pairs of thin film transistors are operated in a sub-threshold mode.

Abstract: A reference voltage generator includes a voltage generation circuit, an amplifier, a diode unit and a transistor. The voltage generation circuit includes an output terminal for outputting a reference voltage, a first terminal having an operational voltage, and a second terminal. The amplifier includes an input terminal coupled to the first terminal of the voltage generation circuit, an output terminal, a first terminal coupled to a first voltage terminal, and a second terminal. The diode unit includes a first terminal coupled to the second terminal of the amplifier, and a second terminal coupled to the second terminal of the voltage generation circuit and a second voltage terminal. The transistor includes a first terminal coupled to the first terminal of the amplifier, a second terminal coupled to the output terminal of the voltage generation circuit, and a control terminal coupled to the output terminal of the amplifier.

Abstract: An embodiment for bandgap reference voltage circuitry includes: a bandgap reference voltage generator including: a first bipolar junction transistor (BJT); a first amplifier having a non-inverting input coupled to a collector of the first BJT and a first output node configured to provide a bandgap reference voltage; a first resistor coupled between a base of the first BJT and the first output node; a second BJT; a second amplifier having a non-inverting input coupled to a collector of the second BJT and a second output node coupled to a junction node; a second resistor coupled between a base of the second BJT and the junction node; and a third resistor coupled between the base of the first BJT and the junction node.

Abstract: In a voltage generating circuit, a bandgap voltage generator has a first operational amplifier to receive a first voltage and a second voltage, and generate a bias voltage by comparing the first voltage and the second voltage, wherein the bandgap voltage generator generates a bandgap current according to the bias voltage and generates an output voltage according to the bandgap current. In a start-up circuit, a comparison circuit compares the first voltage or the second voltage with a reference voltage to generate a first comparison result, and generates a first current according to the first comparison result. A voltage regulator generates a second current according to the first current, and compares the second current with a reference current to generate a second comparison result, and adjusts a voltage value of the bias voltage according to the second comparison result.

Abstract: A family of bandgap embodiments are disclosed herein, capable of operating with very low currents and low power supply voltages, using neither any custom devices nor any special manufacturing technology, and fabricated on mainstream standard digital CMOS processes. As such, manufacturing cost can be kept low, manufacturing yields of digital CMOS system-on-a-chip (SOC) that require a reference can be kept optimal, and manufacturing risk can be minimized due to its flexibility with respect to fabrication process node-portability. Although the embodiments disclosed herein use novel techniques to achieve accurate operations with low power and low voltage, this family of bandgaps also uses parasitic bipolar junction transistors (BJT) available in low cost digital CMOS process to generate proportional and complementary to absolute temperature (PTAT and CTAT) voltages via the base-emitter voltage (VEB) of BJTs and scaling VEB differential pairs to generate the BJTs thermal voltage (VT).

Abstract: Bandgap reference circuitry comprises a first current mirror connected to a power supply line and configured to supply a first current to a first node and a second current to a second node virtually-shorted to the first node, a first pn junction element between the first node and a ground line; a first variable resistor element between the second node and the ground line, and a second pn junction element connected in series to the first variable resistor element. The first variable resistor element has a resistance dependent on a power supply voltage supplied to the power supply line.

Abstract: An oscillator control circuit includes a zero-temperature coefficient (ZTC) estimator estimating a ZTC voltage based on a supply voltage supplied to the oscillator and a frequency of an oscillation signal output by the oscillator. The ZTC voltage is the magnitude of the supply voltage VDD which corresponds to the ZTC condition for the oscillator. The ZTC estimator generates a bias control signal such that the magnitude of the supply voltage becomes the ZTC voltage.

Abstract: A voltage regulator that includes an input voltage; a first JFET transistor, the input voltage being applied to a drain of the first JFET transistor; a second JFET transistor, the input voltage being applied to a drain of the second JFET transistor; and a resistor string, the resistor string including a first resistor, a second resistor and a third resistor, the resistor string and the second JFET transistor forming a voltage reference circuit having a reference voltage.

Abstract: A regulator amplifier circuit of an embodiment includes a differential amplifier circuit, an nMOS transistor, and a pMOS transistor. The differential amplifier circuit includes a differential circuit and a transistor. The differential circuit includes a differential MOS transistor circuit, and the transistor includes a gate voltage controlled by the differential circuit. The nMOS transistor includes a drain connected to a drain on minus side of the differential MOS transistor, and a gate connected to a source of the transistor. The nMOS transistor operates in a weak inversion region. The pMOS transistor includes a source connected to a source of the nMOS transistor, and a drain connected to a voltage lower than a source voltage of the nMOS transistor. The pMOS transistor operates in the weak inversion region.

Abstract: A voltage or current generator has a configurable temperature coefficient and includes a first voltage generator that generates a first voltage having a first negative temperature coefficient. A second voltage generator generates a second voltage having a second negative temperature coefficient different to the first negative temperature coefficient. A circuit generates an output level based on the difference between the first voltage scaled by a first scale factor and the second voltage scaled by a second scale factor.

Abstract: There is disclosed configurable frequency-divider circuitry for generating a target signal of a frequency Fr/Di based on a reference signal of a frequency Fr, where Di is an integer divider ratio, the frequency-divider circuitry comprising: N divider stages organised into a ring, each stage configured to receive an input signal and generate an output signal, with the output signal of each successive stage in the ring being the input signal of the next stage in the ring, wherein: the ring of stages is controlled by the reference signal so that the output signals are governed by the reference signal; the target signal is one of the output signals or a signal derived therefrom; and at least one of the stages is a configurable stage, whose mode of operation is configurable based on a configuration signal to configure the value of Di.

Abstract: An integrated circuit (IC) comprises an output and a voltage regulator. The voltage regulator comprises an amplifier having a first input coupled to a reference voltage source and a second input coupled to the output, a first resistor coupled to the output and coupled to a ground terminal, a metal oxide semiconductor field effect transistor (MOSFET) having a gate coupled to an output of the amplifier and a drain coupled to the output, and a second resistor coupled to a source of the MOSFET and coupled to the ground terminal.

Abstract: The present disclosure relates to a PTAT voltage reference circuit and a temperature independent voltage reference circuit in which the effect of transistor base currents on the circuit output is compensated for. This is achieved by a pair of compensation resistors. The base current from one of the pair of transistors is used to increase the voltage drop across one of the compensation resistors. The base current from the other of the pair of transistors is used to decrease the voltage drop across another of the compensation resistors, by an equal amount. The compensation resistors are connected in series with the resistor which reflects the difference in base-emitter voltage (?VBE). The circuit output is measured across the series connected resistors. As such, the base currents are compensated for at the output.

Abstract: A reference voltage circuit is provided. The reference voltage circuit includes a first current bias circuit including a first node; a second current bias circuit including a plurality of NMOS transistors and a second node, and an amplifier configured to output a reference voltage having same value as the second voltage. The plurality of NMOS transistors include a first NMOS transistor and a second NMOS transistor, the first NMOS transistor is connected to the first node, and the plurality of NMOS transistors are connected to the second node and configured to perform a sub-threshold operation based on a first voltage of the first node so that a second voltage is generated at the second node.

Abstract: A bandgap reference circuit including a clamp circuit is provided. The bandgap reference circuit performs the calibration only for one time in a normal mode to store a control code of a reference generator of the clamp circuit. In a suspend mode, the control code is used for controlling the reference generator to cause the clamp circuit to provide a desired source voltage, and a bandgap reference voltage source is shut down to reduce the power consumption.

Abstract: Provided are a switching regulator and a voltage-current conversion circuit configured to shorten a start-up period. The voltage-current conversion circuit includes: a first MOS transistor of a first conductivity type including a gate and a drain connected in common, and a source connected to a first power supply terminal; a first resistor connected between the drain of the first MOS transistor and a second power supply terminal; and a correction current generation unit including a second resistor, and configured to generate, as a correction current, through use of the second resistor, a current corresponding to a current generated when a voltage corresponding to an absolute value of a gate-source voltage of the first MOS transistor is applied to the first resistor. The voltage-current conversion circuit is configured to add the correction current to a current flowing through the first resistor, to thereby generate the conversion current.

Abstract: An example voltage reference circuit includes: a reference circuit comprising a first circuit configured to generate a proportional-to-temperature current and corresponding first control voltage and a second circuit configured to generate a complementary-to-temperature current and corresponding second control voltage; a first current source coupled to a first load circuit, the first current source generating a sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the first load circuit generating a zero temperature coefficient (Tempco) voltage from the sum current; and a second current source coupled to a second load circuit, the second current source generating the sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the second load circuit generating a negative Tempco voltage from the sum current and the compl

Abstract: An integrated circuit voltage regulator includes a transconductor first stage; and a negative impedance cancellation stage, where the negative impedance cancellation stage comprises cross-coupled transistors at outputs of said transconductor first stage, and resistors in the transconductor first stage and the negative impedance cancellation stage introduce zeros in a transfer function, compensating for parasitic poles. The resistors may compensate for parasitic capacitance inherent in transistors. Load transistors may be coupled to outputs of the transconductance first stage. The voltage regulator may be implemented in a Complementary Metal-Oxide-Semiconductor (CMOS) structure, which may be a system-on-chip integrated circuit. The voltage regulator may provide immunity to power supply noise. The negative impedance cancellation stage may include differential input transistors coupled to the cross-coupled transistors.

Abstract: The disclosure provides a voltage generating device and a calibrating method thereof. The voltage generating device includes a bandgap circuit, a regulator circuit and a calibrating circuit. The bandgap circuit provides a bandgap voltage. The regulator circuit generates an output voltage correspondingly according to the bandgap voltage. In a first stage of a calibration period, the calibrating circuit detects the bandgap voltage, and correspondingly sets a resistance of at least one resistor of the bandgap circuit according to the bandgap voltage. In a second stage of the calibration period, the calibrating circuit detects the output voltage, and correspondingly sets a resistance of at least one resistor of the regulator circuit according to the output voltage.

Abstract: A start-up circuit for a bandgap reference voltage generator circuit, including a first native transistor with a drain connected to a supply voltage of the bandgap reference voltage generator circuit and a source connected to a gate of the first native transistor; a low voltage transistor with a source connected to ground, a drain connected to the source of the first native transistor, and a gate connected to a resistor; a second native transistor with a source connected to the resistor, a gate connected to the source of the first native transistor; a high voltage transistor with a drain connected to a drain of the second native transistor and a source connected to the supply voltage; and a transistor with a gate connected to the gate of the first high voltage transistor and a drain which provides a start-up current for the bandgap reference voltage generator circuit.

Abstract: An apparatus for obfuscating power consumption associated with one or more operations of a logic circuitry of a processor. The apparatus comprises counterbalance circuitry configured to provide a second power consumption to directly counterbalance the power consumption associated with the one or more operations of the logic circuitry. The second power consumption varies inversely with the power consumption associated with the one or more operations of the logic circuitry. The apparatus further comprises header circuitry configured to enable a common node to vary in voltage corresponding to the one or more operations of the logic circuitry. The counterbalance circuitry and the header circuitry are each coupled to the logic circuitry at the common node.

Abstract: A linear regulator includes: a current bias module, a voltage bias module having positive temperature characteristics, and a flip voltage follower. An input end of the current bias module receives an input voltage of the linear regulator, and an output end of the current bias module outputs a bias current. A first input end and a second input end of the voltage bias module receive the input voltage and the bias current, respectively, and an output end of the voltage bias module outputs a bias voltage. A first input end and a second input end of the flip voltage follower receive the input voltage and the bias voltage, respectively, and an output end of the flip voltage follower outputs an output voltage of the linear regulator.

Abstract: A voltage reference includes a flipped gate transistor and a first transistor, the first transistor having a first leakage current, wherein the first transistor is connected with the flipped gate transistor in a Vgs subtractive arrangement. The voltage reference further includes an output node configured to output a reference voltage, the output node connected to the first transistor. The voltage reference further includes a second transistor connected to the output node, the second transistor having a second leakage current. The voltage reference further includes a boxing region configured to provide a voltage level at a drain terminal of the first transistor to maintain the first leakage current substantially equal to the second leakage current.

Abstract: A proportional to absolute temperature (PTAT) generator, for example, generates a PTAT current (IPTAT) and a VBE (voltage base-to-emitter) in a first regulation loop. A voltage-to-current converter is operable to generate a complementary to absolute temperature current (ICTAT). The IPTAT and ICTAT are summed to obtain a zero temperature coefficient current (IZTC). One ICTAT and one resistor are used to generate the IZTC signal.

Abstract: A bandgap reference (BGR) circuit and method generates a constant voltage reference that is stable over temperature variations. The BGR circuit is composed of a proportional to absolute temperature (PTAT) stage, a complementary to absolute temperature (CTAT) stage, and an output stage interposed between the PTAT stage and the CTAT stage. The PTAT stage is configured to produce a PTAT current and the CTAT stage is configured to produce a CTAT current. The BGR circuit is configured to mirror the PTAT current and mirror the CTAT current to produce a mirrored PTAT current and a mirrored CTAT current in the output stage and the output stage is configured to combine the mirrored PTAT current and the mirrored CTAT current to generate the constant voltage reference.

Abstract: A bandgap reference circuit includes a voltage reference circuit configured to generate a reference voltage at a first output and a proportional to absolute temperature (PTAT) current source configured to generate a PTAT current reference at a second output. A divider circuit is coupled to the reference voltage and configured to generate a divided reference voltage at a third output of the bandgap reference circuit. The bandgap reference circuit further includes a tunable current source coupled to the divider circuit and configured to generate a tunable current reference at a fourth output of the bandgap reference circuit based, at least in part, on the divider circuit. A method of generating a tunable current with a bandgap circuit is also provided.

Abstract: A microfluidic pump with thermal control. The microfluidic pump employs a fluid motivation mechanism that moves microscopic fluid volumes through a conduit using thermal vapor bubbles generated using supercritical heating. Aspects of the microfluidic pump include the use of a pump temperature controller that monitors temperatures associated with the microfluidic pump and slows or pauses operation of the microfluidic pump to reduce the rate at which heat is generated allowing additional time for heat to be passively dissipated. Controlling the upper microfluidic pump temperature prevents or reduces overheating of the fluid being pumped that renders the fluid less suitable or unsuitable for its intended purpose or harm to the microfluidic pump. Other aspects of the pump temperature controller include an optional substrate heater that helps raise the fluid temperature to a selected operational range for better performance of the fluid and/or the microfluidic pump.

Abstract: A bandgap reference circuit incorporates first, second, and third current sources, first and second amplifiers, first and second bipolar transistors, a feedback device, a first resistor, and a second resistor. The first resistor is coupled between one input of the second amplifier and the base of the first bipolar transistor. The second resistor is coupled between the base of the first bipolar transistor and the base of the second bipolar transistor. The first and second amplifies and the first to third current sources constitute negative feedback loops which force the voltages at the inputs of the amplifiers to be substantially equal.

Abstract: A semiconductor device includes a first circuit configured to generate a current corresponding to the input signal, a second circuit configured to generate a voltage corresponding to the current generated by the first circuit, a constant current source, a transistor that includes a drain terminal receiving a current from the constant current source and a gate terminal to which the voltage corresponding to the current generated by the first circuit is applied, and an amplification circuit configured to amplify a difference voltage between a drain voltage of the transistor and a reference voltage and output the amplified difference voltage as an output signal corresponding to the input signal.

Abstract: An electronic device may include first through fourth current generators. The first current generator may be configured to output first and second mirroring currents. The second current generator may be configured to output third and fourth mirroring currents. The third current generator may be configured to generate a fifth mirroring current having a current slope proportional to a current slope of the first mirroring current and output a first current having a level of a value obtained by subtracting a level of the fifth mirroring current from a level of the second mirroring current. The fourth current generator may be configured to generate a sixth mirroring current having a current slope proportional to a current slope of the fourth mirroring current and output a second current having a level of a value obtained by subtracting a level of the sixth mirroring current from a level of the third mirroring current.

Abstract: A buck voltage converter is provided which is configured so that a dominant pole of an open loop transfer function of the buck voltage converter is a pole introduced by a network comprising an inductor and a capacitor coupled to an output of the buck voltage converter.

Abstract: A voltage generator which generates an internal voltage based on a varying voltage derived from the internal voltage includes a feedback control circuit configured to variably transmit the varying voltage responsive to a control signal to generate a feedback voltage. A voltage generation circuit is configured to generate the internal voltage based on the feedback voltage.

Abstract: The invention disclosed a signal processing system and method thereof, applicable to an environment providing accurate output frequency. By using the signal processing system, the stable output voltage (AMP OUT) of the error amplifier is inputted to the input of the voltage controlled oscillator (VCO), the output frequency (Fvco) of the VCO is provided to the input of fractional-N frequency divider for digital division. The output of the fractional-N frequency divider (Fo) is provided to the input of the frequency to voltage converter for frequency/voltage conversion. Then, the low pass filter is used to filter out the ripple of the output voltage (V1) of the frequency to voltage converter and the trebling jitter of the output of the fractional-N frequency divider. The signal processing system of the present invention utilizes the voltage locked loop property and digital frequency division to achieve accurate frequency output.

Abstract: An input buffer circuit providing an interface between integrated circuits having differing power supply voltage sources. A voltage reference generator that produces dual reference voltages employing a flipped gate anti-doped transistor. A receiver is connected to receive the first reference voltage and the second reference voltage and the input voltage signal from an integrated circuit operating with a low power supply and transmitting with the first voltage range. The receiver has a first comparator, a second comparator, and a latching circuit. The first comparator compares receive the input voltage and the first reference voltage and the second comparator compares the input voltage and the second reference voltage for determining the output state of the receiver. The output of the receiver provides the data output signal from the input buffer.

Abstract: An element substrate comprises: a data latch unit for latching, based on a first signal, first print data and second print data which have been received by a reception unit; a first driving unit for driving printing elements based on a timing of a second signal and a logical operation result of printing element selection data and the first print data latched by the data latch unit; a delay unit for delaying the second signal by a predetermined time; an operation result latch unit for latching, based on the delayed second signal, a result of a logical operation of the printing element selection data and the second print data latched by the data latch unit; and a second driving unit for driving the printing elements in accordance with the latched operation result and the delayed second signal.

Abstract: A reference voltage generator includes a mirroring circuit generating a first sub-voltage and a second sub-voltage that are constant, a first voltage generator including a first switch generating a first voltage based on the first sub-voltage, and a second voltage generator including a second switch generating a second voltage that is lower than the first voltage based on the second sub-voltage, wherein the second switch has a threshold voltage that is lower than the first switch to keep a voltage difference between the first voltage and the second voltage as a first reference voltage.

Abstract: Circuits and methods to compensate leakage current of a LDO regulator are disclosed. The compensation is achieved by a temperature dependent sink current generation, matched with its temperature dependency characteristic to the LDO regulator output transistor leakage, which has a nearly zero current consumption increase of about 50 nA at room temperature and starts sink current at temperatures about above 85 to 125 degrees Celsius, which is corresponding to a range of temperature wherein leakage currents come into account.

Abstract: The disclosure is directed to a simple, inexpensive circuit to extract the complementary metal-oxide-semiconductor (CMOS) threshold voltage (Vt) from an integrated circuit. The threshold voltage may be used elsewhere in the circuit for a variety of purposes. One example use of threshold voltage is to sense the temperature of the circuit. The CMOS Vt extraction circuit of this disclosure includes a current mirror and an arrangement of well-matched transistors and resistors that takes advantage of the square law equation. The structure of the circuit may make it well suited to applications that benefit from low-power radiation hardened circuits.

Abstract: Apparatuses, systems, and methods are disclosed for offset trimming for differential amplifiers. An apparatus includes a differential amplifier. A differential amplifier includes a non-inverting input, an inverting input, and an output coupled to the inverting input via a voltage divider. A first variable current source is coupled to a non-inverting input, so that increasing a current from the first variable current source increases a voltage at the non-inverting input. A second variable current source is coupled to an inverting input, and to an output via a voltage divider, so that increasing a current from the second variable current source decreases a voltage at the output.

Abstract: Systems disclosed herein provide for a low-noise current mirror operable under low power supply requirements. Embodiments of the systems provide for a low input current path and a high input current path, wherein the current in the low current input path sees a higher voltage and the current in the high input current path sees a lower voltage. Embodiments of the system also provide for a cascode transistor in the high input current path.

Abstract: A BGR circuit for sub-1V ICs utilizes a voltage chopping circuit and/or a current chopping circuit and a low-frequency filter to stabilize the output reference voltage that is generated by an op-amp, a current mirror circuit, a CTAT stage, a PTAT stage, and an output stage. The voltage chopping circuit reduces input offset and 1/f noise by periodically alternating (time-averaging) the negative temperature dependent and positive temperature dependent voltages supplied by the CTAT and PTAT stages to the op-amp's input terminals. The current chopping circuit minimizes current variations caused by process-related differences in the current mirror devices by periodically alternating (time-averaging) three balanced currents generated by the current mirror circuit such that each current is transmitted equally to each of the CTAT, PTAT and output stages. The filter serves to maintain loop stability and remove the low frequency noise generated by the applied voltage and/or current chopping operations.

Abstract: Two transistors are connected between a power source and separate current references. The base of the first transistor is connected to a bias voltage, and the base of the second transistor is connected to the output of a differential amplifier. The amplifier inputs are connected to the nodes where the transistors are connected to the current references. The transistors and the current references may be of different sizes, such that the output voltage of the amplifier is a function of temperature and of the product of the ratios of the transistors and the current references. A number of switches may be employed such that, in alternative modes of operation, the amplifier is used to buffer the bias voltage, the offset of the amplifier, the output of the first transistor, and/or a stored sample of the temperature output voltage, which are combined to arrive at an adjusted temperature reading.

Abstract: Methods, apparatus, systems and articles of manufacture for negative output voltage active clamping using a floating bandgap reference and temperature compensation are disclosed. An example load switch includes a floating bandgap reference circuit to generate a bandgap reference voltage. A resistor divider is to generate a resistor divider voltage. A temperature compensator to apply a temperature compensation current to the resistor divider to create a temperature compensated resistor divider voltage. A power transistor is to be enabled when the temperature compensated resistor divider voltage is less than the bandgap reference voltage. The example load switch can work under negative output voltage clamping and get better accuracy drain to source clamped voltage of power transistor for inductive load condition.

Abstract: A device includes a circuit cell, a voltage regulator, and an auxiliary signal generator. The voltage regulator is configured to output a write voltage. The auxiliary signal generator is configured to generate an auxiliary signal according to a reference voltage and a reference current, and to transmit the auxiliary signal and the write voltage to the circuit cell according to select signals.

Abstract: A semiconductor device having excellent data retention characteristics. A transistor with a low off-state current is utilized to save and retain data stored in a memory circuit, and a potential to be applied to a back gate of the transistor is applied from a battery provided for each memory circuit. The potential applied to the back gate of the transistor and a potential for charging the battery are generated in a voltage generation circuit. The battery is charged utilizing power gating of the memory circuit and data retention characteristics is improved.

Abstract: An apparatus includes: a first SCR device having a first source terminal coupled to a signal terminal, a first body terminal coupled to the first source terminal, a first gate terminal coupled to the signal terminal, and a first drain terminal; a second SCR device having a second drain terminal coupled to the first drain terminal, a second gate terminal coupled to a reference voltage terminal; and a second source terminal coupled to the reference voltage terminal. The apparatus also includes: a third SCR device having a third source terminal coupled to the signal terminal, a third gate terminal coupled to the first gate terminal, and a third drain terminal; a first capacitor coupled between the third drain terminal and the second gate terminal; and a second capacitor coupled between the second gate terminal and the reference voltage terminal.

Abstract: A Schmitt trigger circuit having an input coupled to a current summing junction. A trickle current source generates a trickle current applied to the current summing junction. A bandgap current source generates a bandgap current applied to the current summing junction (wherein the bandgap current is fixed when a supply voltage exceeds a threshold). A variable current source generates a variable current applied to the current summing junction (wherein the variable current varies dependent on the supply voltage). At the current summing junction, the variable current is offset against the trickle and bandgap currents with respect to generating a voltage that is sensed at the Schmitt trigger circuit input.