For Current Stabilization Patents (Class 323/312)
  • Patent number: 10734957
    Abstract: A circuit comprises a Sallen-Key filter, which includes a source follower that implements a unity-gain amplifier; and a programmable-gain amplifier coupled to the Sallen-Key filter. The circuit enables programmable gain via adjustment to a current mirror copying ratio in the programmable-gain amplifier, which decouples the bandwidth of the circuit from its gain settings. The programmable-gain amplifier can comprise a differential voltage-to-current converter, a current mirror pair, and programmable output gain stages. The Sallen-Key filter and at least one branch in the programmable-gain amplifier can comprise transistors arranged in identical circuit configurations.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: August 4, 2020
    Assignee: Tensorcom, Inc.
    Inventors: Zaw Soe, Kevin Jing, Steve Gao
  • Patent number: 10659241
    Abstract: In a Power over Ethernet (PoE) system, a Powered Device (PD) having circuitry to measure the load current from a Power Sourcing Equipment (PSE) in the PD. Circuitry compares the measured load current with a first threshold. Circuitry automatically generates load pulses for signaling the PSE. The pulse widths of the load pulses are measured and the widths are automatically adjusted, that power to the PD should be maintained.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: May 19, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Jean Picard
  • Patent number: 10630291
    Abstract: An integrated circuit delay cell includes an input circuit to establish a current level in the circuit, a switch configured to control an on/off time of a delay circuit, a delay circuit including at least one current starved stage configured to mirror the current level, the delay circuit configured to control a speed of a rise and/or fall time of an output signal, and a glitch discharging circuit connected to the delay circuit configured to tolerate and discharge unwanted charge of the delay circuit.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: April 21, 2020
    Assignee: NXP B.V.
    Inventor: Xu Zhang
  • Patent number: 10620657
    Abstract: A current source circuit includes a first current mirror, a first bipolar junction transistor (BJT), a second BJT, a third BJT and a first resistor. The first current minor has a first input terminal receiving a first current and a first output terminal providing a second current. The first BJT has a first collector coupled to the first output terminal, a first base, and a first emitter coupled to a reference voltage. The second BJT has a second collector coupled to the first input terminal, a second base coupled to the first base, and a second emitter. The first resistor is coupled between the second emitter and the reference voltage. The third BJT has a third collector providing a third current, a third base coupled to the first output terminal, and a third emitter coupled to the first base.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: April 14, 2020
    Assignee: Nuvoton Technology Corporation
    Inventor: Ming-Hsin Huang
  • Patent number: 10581380
    Abstract: The self-polarised quartz oscillator circuit comprises an amplifier with an output which is connected to a first electrode of the quartz and an input which is connected to a second electrode of the quartz, an output capacitor which is connected to the first electrode of the quartz and an input capacitor which is connected to the second electrode of the quartz. The amplifier is polarised by a current through a MOS polarisation transistor, which is generated in an amplitude regulation assembly which comprises also an amplitude regulation stage. The second electrode of the quartz is connected to the gate of the polarisation transistor and to the amplitude regulation stage in order to modulate the polarisation current and to regulate the oscillation amplitude of the quartz.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: March 3, 2020
    Assignee: EM Microelectronic-Martin SA
    Inventors: Mathieu Coustans, Luca Rossi, Yves Godat
  • Patent number: 10549094
    Abstract: Presented herein are techniques for monitoring the physical state of a stimulating assembly to, for example, detect the occurrence of an adverse event. More specifically, an elongate stimulating assembly comprising a plurality of longitudinally spaced contacts is at least partially implanted into a recipient. Electrical measurements are performed at one or more of the plurality of contacts and the electrical measurements are evaluated relative to one another to determine the physical state of the stimulating assembly.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: February 4, 2020
    Assignee: Cochlear Limited
    Inventors: Benjamin Peter Johnston, Paul Michael Carter, Stuart John Kay, Andrea Lam, Shaun Ashwin Kumar, Joerg Pesch
  • Patent number: 10509059
    Abstract: The apparatus for detecting current includes: a charging stage having one end connected to a power source and another end connected to an inductor and configured to charge the inductor with a current; a discharging stage having one end connected to the inductor and another end connected to ground potential and configured to discharge the current charged in the inductor; and a detecting stage configured to detect a magnitude of a current flowing through the inductor based on a first output voltage output from a first output node of the charging stage when the inductor is charged by the charging stage or on a second output voltage output from a second output node of the discharging stage when the inductor is discharged by the discharging stage.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: December 17, 2019
    Assignee: LSIS CO., LTD.
    Inventor: Jong-Kug Seon
  • Patent number: 10497410
    Abstract: A high-density memory includes: a data write interface, a data read interface, an array of memory cells and level-shifting write drivers. The data write interface inputs data written to the memory. The data read interface outputs data read from the memory. The array of memory cells stores data input at the data write interface and outputs stored data to the data read interface. Each of the memory cells includes at least one low threshold voltage (LVT) read transistor and at least one respective regular threshold voltage (RVT) transistor, so as to obtain high-speed read operations. The level-shifting write drivers supply shifted write wordline voltages to the array, so as to obtain high-speed write operations.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: December 3, 2019
    Assignees: MELLANOX TECHNOLOGIES, LTD., BAR-ILAN UNIVERSITY
    Inventors: Elad Mentovich, Narkis Geuli, Robert Giterman, Alexander Fish, Adam Teman
  • Patent number: 10459466
    Abstract: An apparatus is described comprising a bandgap reference circuit comprising: an amplifier including first and second inputs and an output; and a bandgap transistor coupled to the output of the amplifier at a control electrode thereof, the bandgap transistor being further coupled commonly to the first and second inputs of the amplifier at a first electrode thereof to form a feedback path. The apparatus further comprises a resistor coupled to the first electrode of the bandgap transistor.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: October 29, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Wei Lu Chu, Dong Pan
  • Patent number: 10454360
    Abstract: An over-voltage protection circuit and method may include a pass gate and a voltage boosting circuit for providing protection to start-up voltage-sensitive circuits during start-up conditions of a system including the voltage-sensitive circuits. The pass gate may include a drain, source, and gate, with the drain configured to receive an input signal and the source configured to output the input signal, in response to a pass gate driving voltage signal applied to the gate of the pass gate. The voltage boosting circuit may include an output coupled to the gate of the pass gate, the voltage boosting circuit configured to generate a pass gate driving voltage on the output. The voltage boosting circuit further configured to passively control the pass gate driving voltage to a level less than a steady-state voltage level during start-up of the protection circuit.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: October 22, 2019
    Assignee: NXP USA, INC.
    Inventors: Ahmad Dashtestani, Siamak Delshadpour
  • Patent number: 10439494
    Abstract: In described examples of methods and control circuitry to control a power conversion system, a regulator circuit is coupled to provide switching control signals according to a regulation signal to operate a plurality of converter switches to generate a voltage signal at a switching node. A compensation sense circuit is coupled to provide a compensation pulse signal having a duty cycle that represents a percentage of time that a current flowing through the switching node is above a threshold value. A current compensation circuit adjusts the regulation signal according to the compensation pulse signal.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: October 8, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Reza Sharifi, Kevin Scoones, Orlando Lazaro, Alvaro Aguilar
  • Patent number: 10423175
    Abstract: A method for providing a voltage reference at a present operating temperature in a circuit is provided. The circuit comprises a first MOS transistor having a first threshold voltage; and a second MOS transistor having a second threshold voltage different from the first threshold voltage is provided. Temperature insensitivity is obtained by compensating the difference between the first threshold voltage and the second threshold voltage with a parameter representative of the present operating temperature.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: September 24, 2019
    Assignee: NANYANG TECHNOLOGICAL UNIVERSITY
    Inventors: Joseph Sylvester Chang, Wei Shu, Jize Jiang
  • Patent number: 10418076
    Abstract: An apparatus is provided which comprises: a first power gate transistor coupled to an ungated power supply node and a gated power supply node, the first power gate transistor having a gate terminal controllable by a first logic; and a second power gate coupled to the ungated power supply node and the gated power supply node, the second power gate transistor having a gate terminal controllable by a second logic, wherein the first power gate transistor is larger than the second power gate transistor, and wherein the second logic is operable to: weakly turn on the second power gate, fully turn on the second power gate, turn off the second power gate, and connecting the second power gate as diode.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: September 17, 2019
    Assignee: Intel Corporation
    Inventors: Pascal A. Meinerzhagen, Stephen T. Kim, Anupama A. Thaploo, Muhammad M. Khellah
  • Patent number: 10411586
    Abstract: The present disclosure relates to a circuit and a method for overcurrent control and a power supply system including the same. When the system operates normally, a reference voltage has a constant value. When a short circuit or an overcurrent occurs at an output of the system, the reference voltage will be pulled down,. When the system is recovered from the short circuit or the overcurrent state, the reference voltage increases slowly up to a steady value. A feedback signal of an output voltage follows the reference voltage and increases slowly. Thus, an overshoot of the output voltage can be effectively eliminated to avoid damages to the system.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: September 10, 2019
    Assignee: JOULWATT TECHNOLOGY (HANGZHOU) CO., LTD.
    Inventors: Siopang Chan, Pitleong Wong, Yuancheng Ren, Xunwei Zhou
  • Patent number: 10383185
    Abstract: A motor vehicle lighting device comprising at least one branch of semiconductor light sources including two or more light source units connected in series is disclosed herein. A MOSFET switch bridging the individual light source units is assigned to the light source units. The at least one branch is fed from the output voltage of a DC/DC converter with respect to ground. An activation circuit is assigned to the MOSFET switch for activating the MOSFET switch, which is a p-channel MOSFET. A rectifier circuit is assigned to the DC/DC converter. The input of the rectifier circuit is connected to a pole of a storage inductor of the converter, at which negative voltage pulses occur with respect to ground. The rectifier circuit is designed to rectify the negative pulses and to provide the resulting negative DC voltage of the activation circuit for switching the MOSFET switch.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: August 13, 2019
    Assignee: ZKW Group GmbH
    Inventor: Christian Guth
  • Patent number: 10345839
    Abstract: A voltage regulator has feedback circuitry to generate a feedback voltage relative to an output voltage, and an amplifier to amplify a differential voltage between the feedback voltage and a reference voltage to generate the output voltage. The amplifier has a first transistor to feed a current in accordance with the feedback voltage, and a second transistor to feed a current in accordance with the reference voltage. The first transistor has a first gate to be applied with the feedback voltage, and the second transistor has a second gate to be applied with the reference voltage, and the voltage regulator further comprising a conductor disposed to face at least either one of the first and second gates, the conductor being set at a predetermined electric potential.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: July 9, 2019
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Akio Ogura
  • Patent number: 10338616
    Abstract: A reference circuit constituted of: a voltage/current bias circuitry; a first transistor coupled between a common voltage and an first bias circuitry output; a second transistor coupled between the common voltage and a second bias circuitry output; a third transistor coupled between the common voltage and an output providing a temperature and supply invariant current; a resistor coupled between the second transistor and the second output of the bias circuitry; and an output providing a temperature and supply invariant voltage coupled between the resistor and the second transistor, the voltage output terminal further coupled to a gate of the third transistor, wherein the bias circuitry is arranged, in cooperation with the first transistor, to generate a first current at the first output thereof, and, in cooperation with the second transistor, to generate a second current at the second output thereof, the current magnitudes exhibiting a ratio of a predetermined value.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: July 2, 2019
    Assignee: Microsemi Semiconductor (U.S.) Inc.
    Inventor: Daren Allee
  • Patent number: 10340793
    Abstract: A charge pump system includes: a differential amplifier, for receiving a feedback voltage and a reference voltage and generating an output signal; an oscillating circuit for generating clock pulses; a charge pump for receiving the clock pulses and generating an output voltage; a current sink coupled to the output of the charge pump; a first pair of cascode transistors for generating a digital signal; and an inverter for inverting the digital signal to generate a first digital signal according to the output signal, wherein the first digital signal is input to the current sink. When the feedback voltage is higher than the reference voltage, the first digital signal will be generated and the current sink will be turned on, and when the feedback voltage is lower than the reference voltage, the first digital signal will not be generated and the current sink will be turned off.
    Type: Grant
    Filed: November 22, 2018
    Date of Patent: July 2, 2019
    Assignee: Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.
    Inventors: Yuan Tang, Jen-Tai Hsu
  • Patent number: 10320409
    Abstract: A sampling clock generating circuit and an analog to digital converter includes a variable resistance circuit, and a NOT-gate type circuit, where an input end of the NOT-gate type circuit receives a pulse signal whose period is T; a power supply terminal of the NOT-gate type circuit is connected to a power supply; a ground terminal of the NOT-gate type circuit is connected to one end of the variable resistance circuit; and the other end of the variable resistance circuit is grounded; the NOT-gate type circuit is configured to: when the pulse signal is a high level, output a low level; and when the pulse signal is a low level, output a high level.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: June 11, 2019
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Jinda Yang, Liren Zhou
  • Patent number: 10312804
    Abstract: A full-wave rectifier-circuit (110) supplies a pulsating-DC-voltage (Vdc) obtained by rectifying an AC voltage (Vac). A switching element (T131) consisting of a power supply apparatus (130) is turned on during a fixed on-period Mon and turned off during a fixed off-period Moff (=M-Mon) in each fixed control period M. When the switching element (T131) is turned on, a current (I2) caused by electric charge accumulated in a capacitor (C132) flows through a path formed by an inductor (L131) and the switching element (T131). When the switching element (T131) is turned off, a flywheel current (I3) caused by electromagnetic energy accumulated in the inductor (L131) flows through a path formed by a diode (D131) and a parallel circuit consisting of a capacitor (C131) and a load (120), and a current (I1) is supplied from the full-wave rectifier circuit (110) to the capacitor (C132) via an inductor (L132).
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: June 4, 2019
    Inventor: Shunzou Ohshima
  • Patent number: 10298419
    Abstract: A low voltage differential signaling driver includes at least one output circuit, a first control circuit, and a second control circuit. The output circuit includes a first input terminal to receive a first input signal, a second input terminal to receive a second input signal, a first output terminal to output a first output signal, a second output terminal to output a second output signal, and first to sixth transistors. The first control circuit controls a voltage of a control terminal of the first transistor to make a voltage of the first output signal equal to a first reference voltage when the first input signal has a first value. The second control circuit controls a voltage of a control terminal of the second transistor to make the voltage of the first output signal equal to a second reference voltage when the first input signal has a second value.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: May 21, 2019
    Assignee: Ricoh Company, Ltd.
    Inventors: Yuji Watabe, Hiroaki Kyogoku, Nobunari Tsukamoto
  • Patent number: 10284074
    Abstract: A load switch includes a switch element and first and second control circuits. The switch element has an input terminal for receiving an input voltage, an output terminal for providing an output voltage, and a control terminal for receiving a switch signal, which turns the switch element on and off. The first control circuit is connected to the control terminal of the switch element and turns off the switch element in response to a first control signal. The second control circuit also is connected to the control terminal of the switch element and keeps the switch element turned off, after the first control circuit has turned off the switch element.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: May 7, 2019
    Assignee: NXP B.V.
    Inventors: Mingliang Wan, Tinghua Yun, Jian Qing, Peter Christiaans
  • Patent number: 10263794
    Abstract: The invention pertains to systems where DC power is supplied by a PSE to a PD, such as over differential data wire pairs. IEEE standards require a minimum current to be drawn from the PD in order for the PSE to continue supplying the DC voltage. If the PD is in a low power mode, the PSE will normally discontinue supplying the DC voltage, which then requires a new detection and classification routine for powering up again. To avoid this, a “maintain power signature” controller provides a periodic current pulse by a current source connected between the PD input and the PD's full bridge rectifier. Any droop in the DC voltage that reverse biases the full bridge rectifier while the PD is in its low power mode will not affect the current pulse, so the PSE continues to supply the DC voltage.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: April 16, 2019
    Assignee: Linear Technology Corporation
    Inventors: Michael Paul, David M. Stover, Heath D. Stewart, Jeffrey L. Heath
  • Patent number: 10256811
    Abstract: Provided is a cascode circuit including first and second transistors connected between a drain terminal and a source terminal in cascode form, a level sifter configured to change a voltage level of a switching control signal applied to a gate terminal and provide the changed switching control signal to a gate of the first transistor, a buffer configured to delay the switching control signal and provide the delayed switching control signal to a gate of the second transistor, and a first resistor connected between the level shifter and the gate of the first transistor.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: April 9, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Woojin Chang, Jong-Won Lim, Dong Min Kang, Dong-Young Kim, Seong-il Kim, Hae Cheon Kim, Jae Won Do, Byoung-Gue Min, Min Jeong Shin, Hokyun Ahn, Hyung Sup Yoon, Sang-Heung Lee, Jongmin Lee, Sungjae Chang, Yoo Jin Jang, Hyunwook Jung, Kyu Jun Cho, Hong Gu Ji
  • Patent number: 10250130
    Abstract: A switched capacitor converter and a method for configuring the switched capacitor converter are disclosed. The switched capacitor converter includes a capacitance resource with a cathode and an anode and a switching matrix with a first terminal, a second terminal, a third terminal, and at least one switch configured to switch among two or more connections selected from the group consisting of a connection of the first terminal to the anode and the second terminal to the cathode and a connection of the second terminal to the anode and the third terminal to the cathode.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: April 2, 2019
    Assignee: President and Fellows of Harvard College
    Inventors: Gu-Yeon Wei, Tao Tong, David Brooks, Saekyu Lee
  • Patent number: 10248149
    Abstract: A bias circuit includes a first transistor, a second transistor, a first resistor and a second resistor. The first end of the first transistor is coupled to a first voltage source. One end of the first resistor is coupled to the second end of the first transistor, and the other end of the first resistor is coupled to the control terminal of the first transistor. The first end of the second transistor is coupled to a second voltage source, and the second end of the second transistor is coupled to the control terminal of the first transistor. One end of the second resistor is coupled to the other end of the first resistor, and the other end of the second resistor is coupled to the control terminal of the second transistor.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: April 2, 2019
    Assignee: RichWave Technology Corp.
    Inventors: Chih-Sheng Chen, Tien-Yun Peng, Jhao-Yi Lin
  • Patent number: 10236040
    Abstract: Apparatus and methods are disclosed, including an apparatus having a first transistor configured to be coupled to a first bit line, and a control circuit configured to supply a gate of the first transistor with a first voltage to turn on the first transistor, and to supply the gate of the first transistor with a second voltage higher than the first voltage to strengthen a current drive capability of the first transistor.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: March 19, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Shinichi Miyatake
  • Patent number: 10222818
    Abstract: A circuit including a first PMOS (p-channel metal oxide semiconductor) transistor, a first NMOS (n-channel metal oxide semiconductor) transistor, a second PMOS transistor, and a second NMOS transistor. A source, a gate, and a drain of the first PMOS transistor connect to a first node, a second node, and a third node, respectively. A source, a gate, and a drain of the first NMOS transistor connect to a fourth node, the third node, and the second node, respectively. A source, a gate, and a drain of the second PMOS transistor connect to the third node, the fourth node, and the second node, respectively. Finally, a source, a gate, and a drain of the second NMOS transistor connect to the second node, the first node, and the third node, respectively.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: March 5, 2019
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chia-Liang (Leon) Lin
  • Patent number: 10209725
    Abstract: A current limiting circuit includes a current sensing module that is configured to sense an output current of a power transistor and to generate a corresponding sensing current which is proportional to the output current. A first current limiting module coupled to the current sensing module is configured to generate a first limiting current based on the sensing current when a variation of the output current of the power transistor exceeds a first current level. A second current limiting module coupled to the current sensing module is configured to generate a second limiting current based on the sensing current when a variation of the output current of the power transistor exceeds a second current level. A converting module coupled to the first and second current limiting modules and the power transistor controls a gate voltage of the power transistor based at least on the first and second limiting currents.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: February 19, 2019
    Assignee: STMicroelectronics (Shenzhen) R&D Co. Ltd.
    Inventor: Ni Zeng
  • Patent number: 10180465
    Abstract: Disclosed is an inspection apparatus for inspecting a chip for noise, including an inspection circuit that is connected to a first power line of the chip and that receives a signal to be inspected, wherein the first voltage is applied to the first power line and the signal to be inspected includes noise having a second voltage, and a voltage doubler that is connected to the first power line and boosts a voltage of driving power having the first voltage, wherein the inspection circuit may be driven by the driving power, the voltage of the driving power is boosted by the voltage doubler, and the inspection circuit inspects the chip for the noise of the signal to be inspected.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: January 15, 2019
    Assignee: Samsung Electronics Co., Ltd
    Inventor: Hyunho Baek
  • Patent number: 10161976
    Abstract: A method of measuring an output resistance of a DUT includes determining an initial output resistance of an n-type transistor, thereby determining an initial gate voltage for the n-type transistor, and determining an initial output resistance of a p-type transistor, thereby determining an initial gate voltage for the n-type transistor. A resistance for a cascode arrangement of the n-type transistor and the p-type transistor is determined, and the output resistance of the DUT using the cascode arrangement is measured by biasing the n-type transistor with the initial gate voltage for the n-type transistor and biasing the p-type transistor with the initial gate voltage for the p-type transistor.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Shen Chou, Po-Zeng Kang, Yung-Chow Peng
  • Patent number: 10153774
    Abstract: A phase locked loop (PLL) circuit and a method for providing a transconductance in the PLL involve forming an input voltage to an operational amplifier by a loop filter. A voltage output of the operational amplifier controls a plurality of current mirrors. A current is formed through a first one of the current mirrors as a function of the input voltage, a resistance of a resistor, and a reference voltage. The reference voltage is directly provided by, or derived from, a reference signal. A second voltage formed in the first current mirror is fed back to the operational amplifier to maintain the current through the first current mirror, which current is then mirrored into at least a second one of the current mirrors to form an output current proportional to a difference between the input voltage and the reference voltage.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: December 11, 2018
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Scott David Huss, Mark Alan Summers
  • Patent number: 10153909
    Abstract: In some embodiments, a powered device includes a powered device circuit, which may include a maintain power signature (MPS) circuit configured to compare a sense current to a reference current. In a first mode, the MPS circuit may be configured to automatically generate an MPS signal when the sense current is less than the reference current.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: December 11, 2018
    Assignee: Silicon Laboratories Inc.
    Inventors: Vince András Horváth, Tamás Marozsák, Péter Onódy, John Gammel
  • Patent number: 10122335
    Abstract: The present invention is directed to electrical circuits and techniques thereof. More specifically, an embodiment of the present invention provides a line driver with transistors directly coupled to the ground, and a bias voltage is coupled common mode resistors of the line driver. There are other embodiments as well.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: November 6, 2018
    Assignee: INPHI CORPORATION
    Inventors: Rajasekhar Nagulapalli, Simon Forey, Parmanand Mishra
  • Patent number: 10122347
    Abstract: An apparatus is provided which includes: a first power supply node; a second power supply node; a memory bit-cell coupled to the second power supply node; a circuitry coupled to the first and second power supply nodes, the circuitry to operate in a diode-connected mode; and a transistor coupled in parallel to the circuitry, wherein the transistor is controllable by a digital signal such that when the transistor is to turn on, it is to apply voltage and/or current stress to the memory bit-cell.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: November 6, 2018
    Assignee: Intel Corporation
    Inventors: Minki Cho, Jaydeep Kulkarni, Carlos Tokunaga, Muhammad Khellah, James Tschanz
  • Patent number: 10063218
    Abstract: Voltage level shifting in a switching output stage is presented. The circuit may include a switching output stage configured to receive an analog input signal and provide a responsive digital output signal, the switching output stage having a first switching device coupled to a first supply voltage and a second switching device coupled to a second supply voltage, the first switching device and the second switching device being coupled to a common output node. The apparatus may also include a voltage level shifter circuit coupled to a switching control node of the second switching device, the voltage level shifter configured to shift a voltage level at the switching control node of the second switching device relative to the analog input signal, wherein the digital output signal at the common output node transitions as the input signal reaches a predetermined threshold value.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: August 28, 2018
    Assignee: Cirrus Logic, Inc.
    Inventor: Dan Shen
  • Patent number: 10062344
    Abstract: The invention provides a voltage stabilizing device. In the voltage stabilizing device, a signal detecting and amplifying circuit detects an operating voltage of the functional circuit, amplifies the detected operating voltage and outputs the amplified voltage signal to a logic processing circuit; the logic processing circuit adjusts a first control signal according to the amplified voltage signal and outputs the adjusted first control signal to a feedback voltage signal generating circuit; the feedback voltage signal generating circuit adjusts a feedback voltage signal according to the adjusted first control signal and outputs the adjusted feedback voltage signal to the logic processing circuit. Moreover, the logic processing circuit further adjusts a second control signal according to the adjusted feedback voltage signal and outputs the adjusted second control signal to the functional circuit, and thereby controls an output voltage of the functional circuit to be kept stable.
    Type: Grant
    Filed: June 18, 2016
    Date of Patent: August 28, 2018
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventors: Xianming Zhang, Dan Cao
  • Patent number: 10042378
    Abstract: An on chip temperature independent current generator for generating a temperature independent current, said temperature independent current generator including: an on chip current generator having an output to provide an electrical current being proportional to an absolute temperature of a chip in which the temperature independent current generator is embedded; and an on chip transistor having a base connected to a temperature independent reference voltage generator, a collector connected to a current mirror, and an emitter connected to the output of the on chip current generator and connected via an on chip resistor to a reference potential, wherein the current mirror is adapted to mirror a collector current flowing to the collector of said on chip transistor to generate the temperature independent current.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: August 7, 2018
    Assignee: ROHM CO., LTD.
    Inventor: Irina Mladenova
  • Patent number: 10018660
    Abstract: A testing structure includes a first transistor having a first dopant type connected to a current source. The testing structure further includes a second transistor having a second dopant type, opposite to the first dopant type. The second transistor is connected to a device under test (DUT). The second transistor is connected in series with the first transistor in a cascode arrangement. The cascode arrangement is capable of measuring an output resistance of the DUT of greater than 1 mega-ohm (M?).
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: July 10, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Shen Chou, Po-Zeng Kang, Yung-Chow Peng
  • Patent number: 10020727
    Abstract: Method and device for controlling an inductive load by pulse width modulation, on the basis of a periodic set point control signal having a given set point duty cycle. The set point control signal is, in each period of the set point control signal, in a first logic state determined from the high and low logic states for at least a first duration, and is in the other logic state during the rest of the period. Control signals are generated for activating the inductive load, on the basis of the set point control signal. With the aid of a first counter, the first duration (t0) is determined on the basis of the set point control signal. Via a second counter, a second duration (t0?td2) is determined, for which a logic signal corresponding to an effective control signal observed in the load is in the first determined logic state.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: July 10, 2018
    Assignees: CONTINENTAL AUTOMOTIVE FRANCE, CONTINENTAL AUTOMOTIVE GMBH
    Inventor: Angelo Pasqualetto
  • Patent number: 10015026
    Abstract: A transmitter according to the disclosure includes: three first driver sections; three first pre-driver sections that are provided corresponding to the respective three first driver sections, and each drive corresponding one of the first driver sections on a basis of corresponding one of three first control signals that are different from one another and each including predetermined number of signals; a second pre-driver section that operates on a basis of a second control signal that includes predetermined number of signals; and a controller that controls transition of the predetermined number of signals included in the second control signal to allow number of signals to be subjected to the transition out of the plurality of signals included in the three first control signals and the plurality of signals included in the second control signal to be same between timings of the transition.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: July 3, 2018
    Assignee: Sony Corporation
    Inventor: Hisashi Owa
  • Patent number: 9998099
    Abstract: A feed-forward bias circuit biases body bias terminals of transistors of another circuit to compensate for PVT variations in the other circuit. In some aspects, the feed-forward bias circuit compensates for transistor process corners in a circuit by enabling the generation of different bias signals under different corner conditions. In some implementations, the feed-forward bias circuit is used to bias a delay circuit so that the delay circuit exhibits relatively constant delay characteristics over different PVT conditions.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: June 12, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Wenjun Su, Chulkyu Lee, Le Zhang, Guangming Yin
  • Patent number: 9983605
    Abstract: A voltage regulator may include an error amplifier configured to amplify a difference between a reference voltage and a feedback voltage and generate a first amplified voltage based thereon; a power transistor between a second voltage supply node and an output node of the voltage regulator, the power transistor including a gate configured to receive a gate voltage; a buffer between a first voltage supply node and a ground, the buffer configured to generate the gate voltage based on the first amplified voltage; a voltage divider between the output node and the ground, the voltage divider configured to generate the feedback voltage based on the output voltage; and a control circuit configured to connect the output node to the ground through the gate of the power transistor based on the output voltage and the gate voltage.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: May 29, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hoang Quoc Duong, Sung Woo Moon, Hyun Seok Shin, Dong Jin Keum
  • Patent number: 9971377
    Abstract: Apparatus and methods for voltage regulation are provided. In some implementations, a voltage regulator circuit includes a field-effect transistor including a source that receives a battery voltage from an input node and a drain coupled to an output node, an amplifier including an output coupled to a gate of the field-effect transistor, and a voltage generator that receives the battery voltage from the input node and provides a reference voltage and one or more bias voltages to the amplifier. The voltage generator controls the amplifier to operate the voltage regulator circuit in a regulation mode or in a bypass mode based on a voltage level of the battery voltage. The amplifier and the field-effect transistor regulate the battery voltage in the regulation mode to provide a regulated voltage at the output node, and the amplifier turns on the field-effect transistor in the bypass mode to provide a bypass voltage substantially equal to the battery voltage at the output node.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: May 15, 2018
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Florinel G. Balteanu, Jakub F. Pingot, Peter Harris Robert Popplewell
  • Patent number: 9921596
    Abstract: A power supply noise reduction circuit and a power supply noise reduction method are provided. An integrated circuit includes an input node configured to receive a signal via a transmission line. The integrated circuit also includes termination circuitry configured to electrically couple the input node to a power rail of the integrated circuit. The integrated circuit further includes a circuit component coupled to the power rail. The circuit component is configured to bleed off a portion of current on the power rail based on a determination that a voltage on the power rail meets or exceeds a high voltage threshold. The circuit component is also configured to bleed off a smaller portion of the current on the power rail based on a determination that the voltage on the power rail is less than the high voltage threshold.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: March 20, 2018
    Assignee: MARVELL ISRAEL (M.I.S.L) LTD
    Inventor: Liav Ben Artsi
  • Patent number: 9923471
    Abstract: There is disclosed a controller for a DC-DC converter comprising a series arrangement of a high-side switch and low-side switch with a half-bridge node therebetween, the controller comprising a high-side part for driving the high-side switch and configured to be powered, when the low-side switch is open, by a rechargeable power supply connected between the half-bridge node and a power supply node, the high-side part comprising a level shifter, driver, latch part comprising a latch having set and reset inputs and configured to latch the driver to either an on-state or an off-state, and a further circuit, wherein the latch part is configured and adapted to prevent the further circuit from drawing current from the power supply unless at least one of the set input is high and the driver is in the on-state. A DC-DC converter having such a controller is also disclosed, as are methods of operating a converter.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: March 20, 2018
    Assignee: NXP B.V.
    Inventors: Peter Theodorus Johannes Degen, Henricus Theodorus Petrus Johannes van Elk
  • Patent number: 9903766
    Abstract: An example method includes outputting, by a device, a first current through a temperature sensor that is that is external to the device; determining, by the device and based on a voltage drop across the temperature sensor while the first current is flowing through the temperature sensor, a current level; outputting, by the device, a second current at the determined current level through the temperature sensor; determining, by an analog-to-digital converter (ADC) of the device, a value that corresponds to a voltage drop across the temperature sensor while the second current is flowing through the temperature sensor; outputting, by the device, a third current through a reference resistor that is external to the device; and determining, based on the value and a voltage drop across the reference resistor while the third current is flowing through the reference resistor, a temperature of the temperature sensor.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: February 27, 2018
    Assignee: Infineon Technologies AG
    Inventors: Yoon Hwee Leow, Kwan Siong Choong, Cheow Guan Lim, Chin Yeong Koh
  • Patent number: 9906124
    Abstract: A reference voltage generation circuit includes a voltage dividing circuit, a transistor, and a capacitor. The voltage dividing circuit divides a power-supply voltage into a specified level to generate a predetermined voltage. The transistor has a gate applied with the predetermined voltage and a drain outputting, as a reference voltage, a voltage obtained by adding the predetermined voltage and a threshold voltage of the transistor. The capacitor bypasses the gate and source of the transistor. Moreover, one end of the capacitor is connected to the gate of the transistor, and the other end of the capacitor is connected to the source of the transistor and ground. Furthermore, an electric charge output source which outputs an electric charge is connected to the drain of the transistor.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: February 27, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yanzheng Zhang
  • Patent number: 9876329
    Abstract: An optical interconnect device is provided that includes a first vertical cavity of surface emitting laser (VCSEL), connected in parallel with a second VCSEL, an optical coupler that is configured to direct the light output from the first VCSEL and the second VCSEL to a single optical fiber, where a common connection of each VCSEL is controlled using a MOSFET/inverter, where in normal operation only one of the first VCSEL or the second VCSEL is enabled, where a common connection of each VCSEL is not directly connected to a ground, and a microcontroller that is configured to switch output from the first VCSEL to the second VCSEL in the event of failure by the first VCSEL, where a failure of the first VCSEL does not result a communication in link failure.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: January 23, 2018
    Assignee: Technische Universiteit Eindhoven
    Inventors: Oded Raz, Teng Li
  • Patent number: 9871509
    Abstract: A power-on reset circuit includes a first resistor having one end connected to a power source node; a first capacitor connected to another end of the first resistor; a second resistor having one end connected to the power source node; a second capacitor connected to another end of the second resistor; a first inverter having a power source terminal connected to the other end of the first resistor and an input terminal connected to the other end of the second resistor; and a second inverter having a power source terminal connected to the other end of the first resistor, an input terminal connected to an output terminal of the first inverter, and an output terminal electrically connected to a reset signal output terminal.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: January 16, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Ryangsu Kim