Abstract: A device includes a circuit cell, a voltage regulator, and an auxiliary signal generator. The voltage regulator is configured to output a write voltage. The auxiliary signal generator is configured to generate an auxiliary signal according to a reference voltage and a reference current, and to transmit the auxiliary signal and the write voltage to the circuit cell according to select signals.

Abstract: A semiconductor device having excellent data retention characteristics. A transistor with a low off-state current is utilized to save and retain data stored in a memory circuit, and a potential to be applied to a back gate of the transistor is applied from a battery provided for each memory circuit. The potential applied to the back gate of the transistor and a potential for charging the battery are generated in a voltage generation circuit. The battery is charged utilizing power gating of the memory circuit and data retention characteristics is improved.

Abstract: An apparatus includes: a first SCR device having a first source terminal coupled to a signal terminal, a first body terminal coupled to the first source terminal, a first gate terminal coupled to the signal terminal, and a first drain terminal; a second SCR device having a second drain terminal coupled to the first drain terminal, a second gate terminal coupled to a reference voltage terminal; and a second source terminal coupled to the reference voltage terminal. The apparatus also includes: a third SCR device having a third source terminal coupled to the signal terminal, a third gate terminal coupled to the first gate terminal, and a third drain terminal; a first capacitor coupled between the third drain terminal and the second gate terminal; and a second capacitor coupled between the second gate terminal and the reference voltage terminal.

Abstract: A Schmitt trigger circuit having an input coupled to a current summing junction. A trickle current source generates a trickle current applied to the current summing junction. A bandgap current source generates a bandgap current applied to the current summing junction (wherein the bandgap current is fixed when a supply voltage exceeds a threshold). A variable current source generates a variable current applied to the current summing junction (wherein the variable current varies dependent on the supply voltage). At the current summing junction, the variable current is offset against the trickle and bandgap currents with respect to generating a voltage that is sensed at the Schmitt trigger circuit input.

Abstract: A band-gap reference circuit including: mirror current branch circuits, band-gap paths, and an operational amplifier. Each mirror current branch circuit includes a mirror PMOS transistor and an auxiliary PMOS transistor. A drain of each mirror PMOS transistor is connected with a source of a corresponding auxiliary PMOS transistor, and a drain of said each auxiliary PMOS transistor is connected to a top end of a corresponding band-gap path, each gate of each mirror PMOS transistor is connected with an output port of the operational amplifier. A gate of each auxiliary PMOS transistor is connected to a first bias voltage. A substrate electrode of each mirror and auxiliary transistor is all connected to a source voltage. The output port of the operational amplifier outputs a high level less than the source voltage, the first bias voltage is less than an output voltage signal of the operational amplifier.

Abstract: A circuit includes first, second, and third power supply terminals. The circuit includes an input node coupled to receive a negative voltage and an output node coupled to provide a positive voltage proportional to the negative voltage. The circuit includes a voltage-to-current converter coupled to the first power supply terminal and the input node and configured to generate an intermediate current proportional to the negative voltage at the input node. The circuit also includes a current mirror coupled to the second power supply terminal and third power supply terminal and configured to mirror the intermediate current through a first resistor to provide the positive proportional voltage.

Abstract: A low-voltage bandgap reference circuit includes a current source supplying a reference voltage rail. The circuit further includes a Vbe loop branch coupled to the reference voltage rail to obtain a Vbe voltage with a negative temperature coefficient. The circuit further includes a ?Vbe loop branch to obtain a ?Vbe voltage, the ?Vbe loop branch employing a fractional Vbe voltage, to provide a reduced, positive temperature coefficient. The circuit further includes a feedback amplifier that sets identical voltages from the loop branches on inputs of the amplifier A to regulate an output voltage of the circuit on the reference voltage rail at a temperature-compensated value below 1.2V.

Abstract: An FDSOI reference voltage generation circuit, including a CTAT current generation circuit; a PTAT-type voltage generation circuit including a first branch including first and second series-connected transistors, the front surface gates of the first and second transistors being connected to the conduction node of the second transistor opposite to the first transistor; a third diode-assembled transistor having a conduction node connected to an output node of the PTAT voltage generation circuit and having its other conduction node forming a reference voltage supply node; and a current mirror; wherein the first and second transistors are of LVT type and the third transistor is of RVT type.

Abstract: A power supply with digitally compensated circuit having a plurality of integrated circuits. The plurality of integrated circuits has a digitally variable slope controller to adjust charge time of an inductor and voltage distortion and an adjustable voltage generator, which generates a modified voltage set point. The digitally compensated circuit has a comparator, which compares the modified voltage set point to a first feedback and turns off a comparator output signal when first feedback approaches or exceeds the modified voltage set point. An adjustable pulse width modulator generator produces an output voltage. A current monitor receives output voltage and provides a second feedback, which is transferred to the plurality of integrated circuits. An inductor receives output voltage and generates variable output power for a load, utilizing the digitally variable slope controller to reduce oscillation, system disturbances, and subharmonic oscillations over a dynamic voltage input range.

Abstract: An output stage buffer circuit including a first P-channel Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), first to third N-channel MOSFETs, a constant-voltage circuit and a bias circuit. A source of the first P-channel MOSFET is connected to a power supply terminal. A source and a drain of the first N-channel MOSFET are respectively connected to a ground terminal and an output terminal. The first N-channel and P-channel MOSFETs constitute a push-pull circuit. The second N-channel MOSFET is disposed between a drain of the first P-channel MOSFET and a connection point between the drain of the first N-channel MOSFET and the output terminal. A source and a drain of the third N-channel MOSFET respectively receive from the constant-voltage circuit a constant voltage lower than a voltage received at the power supply terminal, and from the bias circuit a constant current. The second and third N-channel MOSFETs constitute a current mirror circuit.

Abstract: A method and apparatus for generating an improved reference voltage for use, for example, in a system requiring accurate low power operation. In particular, our reference voltage generator is adapted to output VREF as a function of the voltage difference between V1 and V2. The reference voltage generator is further adapted to include our reference voltage tuner to compensate for predetermined sensitivities of the reference voltage VREF, and to adjust the absolute value of VREF. During manufacturing and system test, a driver may be used to drive a buffered or unbuffered version of VREF to off-chip test functionality. Also, a configuration memory may be used to store the trim settings during normal operation, and make such settings available to outside resources.

Abstract: A synchronous rectification DC/DC converter includes a first transistor and a second transistor including respective main electrodes connected to a common connection point, the first transistor and the second transistor being NMOS transistors, a control circuit configured to control switching of the first transistor and the second transistor in a complementary manner, a bootstrap circuit that includes a first capacitor charged with a current supplied from a high voltage potential terminal and is configured to raise a voltage potential of a control electrode of the first transistor to turn on the first transistor, and a charging stop circuit configured to stop the first capacitor from being charged from the high voltage potential terminal in a time period in which the first transistor and the second transistor are turned off simultaneously.

Abstract: A constant voltage generating circuit includes an ED-type reference voltage supply that generates a predetermined constant voltage by using a first transistor of depletion-type and a second transistor of enhancement-type that are connected in series between a power supply terminal and a ground terminal, and a third transistor a source of which is connected to an output terminal for the constant voltage, a drain of which is connected to the power supply terminal or the ground terminal, and a gate of which is connected to a connection node between the first transistor and the second transistor.

Abstract: A bandgap reference circuit including a clamp circuit is provided. The bandgap reference circuit performs the calibration only for one time in a normal mode to store a control code of a reference generator of the clamp circuit. In a suspend mode, the control code is used for controlling the reference generator to cause the clamp circuit to provide a desired source voltage, and a bandgap reference voltage source is shut down to reduce the power consumption.

Abstract: A voltage regulator is connected with an input/output circuit. The voltage regulator includes a controlling circuit, a sink voltage generator and a source voltage generator. The controlling circuit generates a first reference voltage, a second reference voltage, a first power start control signal and a second power start control signal. The sink voltage generator receives the first reference voltage and the first power start control signal. The source voltage generator receives the second reference voltage and the second power start control signal. When the voltage regulator is in a normal working state, the controlling circuit inactivates the first power start control signal and the second power start control signal, the sink voltage generator generates a sink voltage according to the first reference voltage, and the source voltage generator generates a source voltage according to the second reference voltage.

Abstract: One charge pump includes at least one delay element, a number of inverters, and a flip flop coupled in series, with an output of one inverter coupled in a feedback loop to one of the delay elements. The charge pump monitors a first supply voltage level, and turns off an oscillator of the charge pump when the first supply voltage drops below a certain level. This is accomplished in one embodiment by monitoring a first supply voltage level supplied to a charge pump, and turning off an oscillator of the charge pump when the first supply voltage drops below a certain level.

Abstract: An apparatus includes a plurality of mirrored transistor pairs configured to provide a first output current, and a second output current that is substantially equal to the first output current. The apparatus also includes a load isolation transistor configured to pass the first output current along to a resistive load and a first and a second biasing transistor configured to bias the load isolation transistor with a load biasing voltage. A gate and drain of the second biasing transistor may be connected to a gate of the load isolation transistor and a drain of the first biasing transistor. Furthermore, a source of the second biasing transistor may be connected to a gate of the first biasing transistor. The width-to-length ratio of the load isolation transistor, the first biasing transistor, and the second biasing transistor are selected to eliminate PTAT dependencies in the first output current.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a data storage circuit and a control circuit. The data storage circuit holds first data to be written into the memory cell and holds 1 bit data calculated from the first data. The control circuit writes the data of n bits into the memory cell in a first write operation and then executes a second write operation. The control circuit carries out the following control in the second write operation. It reads data stored in the memory cell in the first write operation. It restores the first data based on the data read from the memory cell and the 1 bit data held in the data storage circuit. It writes the restored first data into the memory cell.

Abstract: Circuitry for biasing a MEMS transducer and associated signal processing circuitry. A reference voltage generator is configured to generate a reference voltage at a reference voltage node. Control circuitry generates a drive signal to control a first current source which is operable to supply a current to the reference voltage generator in response to the drive signal. A switched DC-DC converter, such as a charge pump has a voltage input connected to the reference voltage node and a voltage output for providing a bias voltage for the MEMS transducer. The DC-DC converter cyclically switches in a sequence of states including at least a first state where a first converter capacitance is disconnected from the voltage input followed by a second state where the first converter capacitance is connected to the voltage input. A second current source is operable to supply a bias current in response to a voltage at a bias control node.

Abstract: Provided is a compensation circuit capable of improving compensation precision for manufacturing variations. The compensation circuit includes a manufacturing variation detection circuit which detects manufacturing variation of a transistor based on a first voltage output from an output terminal of the transistor having an input terminal applied with a substantially constant first current to temperature or based on a second current output from an output terminal of the transistor having an input terminal applied with a substantially constant second voltage to temperature, and a voltage generation circuit which generates a supply voltage supplied to an electric circuit based on the manufacturing variation. The first current corresponds to the substantially constant second voltage to temperature, and the first voltage corresponds to the substantially constant second current to temperature.

Abstract: A reference voltage generation circuit includes a bandgap reference circuit, a first resistive element and a second resistive element connected in series between the output node and a ground terminal, a third resistive element, a fourth resistive element, and a first switch connected in series between the output node and the ground terminal, and a second switch having one end connected to a connecting point of the first resistive element and the second resistive element, at which a reference voltage is generated, and the other end connected to a connecting point of the third resistive element and the fourth resistive element. A ratio between resistance values of the first resistive element and the second resistive element is equal to a ratio between resistance values of the third resistive element and the fourth resistive element. The first and second switches are turned on at power-on and turned off after the reference voltage is started.

Abstract: An improved reference current generator for use in an integrated circuit. A voltage difference generator generates two voltages that are separated by a relatively small electrical potential. The two closely separated voltages are applied across a resistive element with relatively large impedance value resulting in a small and stable reference current. The stable reference current is mirrored and, if desired, amplified for use on the integrated circuit. A driver selectively drives state information off chip for assisting in post-silicon correction of unwanted sensitivities. A configuration memory stores values used to adjust effective device widths and lengths for correcting unwanted sensitivities.

Abstract: An integrated electronic device includes a core having a first terminal and a second terminal. The core includes a first branch with a first diode-connected bipolar transistor coupled in series to a first resistor between the first terminal and a reference terminal intended to be supplied with a reference voltage, and a second branch with a second diode-connected bipolar transistor coupled between the second terminal and the reference terminal. The second diode-connected bipolar transistor has a current density higher than the first diode-connected bipolar transistor. The core also includes a first resistive network coupled between a base of the first diode-connected bipolar transistor and the reference terminal. An equalizer is configured to equalize potentials of the first terminal and of the second terminal and a voltage generator is coupled to the first and second terminals of the core and configured to generate the bandgap voltage.

Abstract: A circuit and method for power converter for improved current monitoring, comprising a buck converter comprising a high side switch, a current sensing circuits parallel to the buck converter configured to sense a current through a low side switch, and a positive slope inductor coil estimator sensing circuit parallel to a buck converter configured to estimate a current magnitude.

Abstract: Provided is a booster circuit enabling improvement of efficiency of a stress test for a circuit to which a boosted voltage is applied. A voltage divider circuit is configured to have a voltage-dividing ratio that is variable depending on a test signal, and a limiter circuit is configured to clamp a voltage to a voltage higher than a boosted voltage in normal operation. In a test mode, the voltage divider circuit is controlled so that the boosted voltage becomes higher than that in the normal operation, and the limiter circuit clamps the boosted voltage, with the result that a booster section continuously operates.

Abstract: Described is an apparatus which comprises: a bandgap core to provide a control signal; and an output stage coupled to the bandgap core, the output stage to receive the control signal and to provide a low impedance output at an output node.

Abstract: Provided is a reference voltage circuit capable of adjusting an arbitrary output voltage to have arbitrary temperature characteristics. The reference voltage circuit includes: a reference current generating circuit configured to convert a difference between forward voltages of a plurality of PN junction elements into current to generate a first current; a current generating circuit configured to use the first current generated by the reference current generating circuit to generate a second current; and a voltage generating circuit including a first resistive element and a second resistive element, the first resistive element being configured to generate a first voltage having positive temperature characteristics when the first current flows through the first resistive element, the second resistive element being configured to generate a second voltage having negative temperature characteristics when the first current and the second current flow through the second resistive element.

Abstract: A bandgap reference circuit includes a first temperature correction circuit that is connected between a power supply terminal and a node between a first resistor and a second resistor. The first temperature correction circuit includes a first transistor that is connected between the first power supply terminal and the node between the first resistor and the second resistor, a control terminal of the first transistor being connected at a junction where the end of a first bipolar transistor connects together with a third resistor, and a fourth resistor that is connected in series between the first transistor and the first power supply terminal.

Abstract: Described is a word-line driver which is operable to switch a voltage level of a word-line to one of: first power supply, second power supply, or third power supply wherein the voltage level of the second power supply is higher than the voltage level of the first power supply, and wherein transistors of the word-line driver have same gate oxide thicknesses.

Abstract: A reference voltage generator may include the following elements: a first power supply terminal configured to receive a first power supply voltage; a second power supply terminal configured to receive a second power supply voltage; a reference voltage output node configured to provide a reference voltage; a first switch electrically connected between the first power supply terminal and the reference voltage output node; a second switch electrically connected between the second power supply terminal and the reference voltage output node; a first positive feedback module electrically connected to both the reference voltage output node and the first switch and configured to provide a first feedback voltage to the first switch; and a second positive feedback module electrically connected to both the reference voltage output node and the second switch and configured to provide a second feedback voltage to the second switch.

Abstract: A delta-Vbe based bandgap reference voltage circuit generates a temperature stable reference voltage. First and second paths of the circuit each include a respective transistor coupled in series with a resistance. The collector current density of the transistor in first path is lower than the collector current density of transistor in the other path. A control path is used to generate a 2Vbe voltage that is coupled to the base nodes of the resistors in each path. A resistance that is coupled between a common node of a first end of the two paths and a circuit ground node. The circuit current is controlled by this resistance and a voltage drop of 2?Vbe is across the resistance. The output reference voltage of the circuit is 2(Vbe+?Vbe) when stack resistors in each path are used.

Abstract: In a reference voltage generation circuit, a reference voltage generation unit 1 is configured to receive, as feedback, a voltage of an output terminal 3; a startup circuit unit 2 has a depletion MOS transistor TR1, and enhancement MOS transistors TR2, TR3; the MOS transistor TR1 has one end connected to a power source 4 and is formed as a constant current connection; the MOS transistor TR2 has one end connected to the power source 4 via a resistor RST, has an opposite end connected to the output terminal 3, and further has a gate connected to an opposite end of the MOS transistor TR1; and the MOS transistor TR3 has one end connected to the opposite end of the MOS transistor TR1, has an opposite end grounded, and further has a gate connected to the output terminal 3. The reference voltage generation circuit can reduce the occurrence of a wasteful current consumption after circuit startup.

Abstract: A discharge circuit for a decoupling capacitor to stabilize a voltage supplied from a first power supply unit to a first load includes a first capacitor, a first switch, and a discharge control circuit. The first capacitor is charged by power supplied from a second power supply unit that supplies power to a second load that is different from the first load. The first switch is arranged between the decoupling capacitor and ground. The discharge control circuit discharges, in a case where power supplied from the second power supply unit to the second load is cut off, charges of the decoupling capacitor to the ground by driving the first switch using charges stored in the first capacitor.

Abstract: A current mirroring circuit including: a first portion having a first resistor and a first transistor, the first transistor having a control terminal coupled to a control terminal of a first diode-connected transistor; and a second portion having a second resistor and a second transistor, the second transistor having a control terminal coupled to a control terminal of a second diode-connected transistor, the first portion being in electrical communication with a first power level and the second portion being in electrical communication with a second power level, the first portion being coupled to the second portion.

Abstract: An apparatus comprising a first power combiner/divider network and a second power combiner/divider network. The first power combiner/divider network splits a first electromagnetic signal into split signals that are connectable to signal processor(s). The second power combiner/divider network combines processed signals into a second electromagnetic signal. The apparatus includes a three-dimensional coaxial microstructure.

Abstract: Systems and methods are disclosed, including a protection multiplexer circuit configured to receive a control signal and a reference voltage, to provide the reference voltage at an output when the control signal is in a first state, and to isolate the reference voltage from the output when the control signal is in a second state. The protection multiplexer circuit includes cascaded first and second transistors, wherein the first transistor is a native transistor. Control inputs of the first and second transistors are configured to receive the control signal, a first terminal of the first transistor is configured to receive the reference voltage, and the first terminal of the second transistor is coupled to the output. Methods of operation are disclosed, and other embodiments.

Abstract: Semiconductor devices are provided. The semiconductor device may include a current generation circuit and an internal circuit. The current generation circuit may include a first drive element and a second drive element which are connected in series. The current generation circuit may generate a reference voltage signal whose voltage level is set by a reference current which is identical or substantially identical to a current flowing through the first and second drive elements. The internal circuit may utilize an output current controlled according to the reference current as an operation current thereof.

Abstract: A reference circuit arrangement comprises a branched current path connecting a first and second terminal via an intermediate terminal. The intermediate terminal is connected to a reference terminal. A current path is coupled between the first and second terminal via the reference terminal. A feedback loop is connected to the first and second terminal and designed to control, at the first and second terminal, a virtual ground potential. A reference path is connected to the feedback loop having a reference input for receiving from the feedback loop a reference current and reference output to provide a reference voltage.

Abstract: A temperature sensor includes two branches, each branch having at least a first transistor and a second transistor connected as diodes and cascaded, so that an emitter of the first transistor is connected to a collector of the second transistor of the same branch. The temperature source also includes a current source configured to provide a current to the two branches, and an analog-to-digital convertor. The analog-to-digital convertor is connected to capture a voltage between emitters of the first transistors or of the second transistors, and is configured to convert said voltage to a digital temperature signal.

Abstract: An active voltage divider circuit is provided comprising: a first node; a second node; a third node; multiple FET load devices coupled in series between the first node and the second node; multiple first switches, each associated with a different FET load device and configured to selectably couple a respective associated bypass circuit between source and drain of its associated FET load device; and second switch circuitry configured to selectably couple a drain of a FET load device, from among the multiple FET load devices, to the third node.

Abstract: One example includes an reference voltage generator system. The system includes an amplifier configured to generate a reference voltage based on a respective input voltage provided at each of at least one input of the amplifier. The system also includes at least one input transistor that is coupled to the at least one input of the amplifier and is statically-biased to conduct a current to set an amplitude of the respective input voltage provided at each of the at least one input of the amplifier. Each of the at least one input transistor includes an input terminal that is coupled in series with an input resistor.

Abstract: A voltage regulator includes an error amplifier; an output transistor; and a first transistor including a gate for inputting a reference voltage and a source for inputting an output voltage. The first transistor is configured to cause a current to flow when the output voltage becomes an irregular voltage, and a current of the output transistor is controlled based on the current flowing through the first transistor. The voltage regulator capable of improving the overshoot or undershoot of the output voltage in a wide temperature range and to reduce a delay in detection of the overshoot or undershoot.

Abstract: A method and circuit for trimming a bandgap reference are described. The bandgap reference circuit comprises a first diode which is arranged in series with a first resistor between a reference point and a reference potential VSS. The circuit also comprises a second diode which is arranged in series with a second resistor and a third resistor between the reference point and the reference potential VSS. In addition, the bandgap reference circuit comprises a trimming network, wherein a bandgap reference voltage VBG CORE is provided at a midpoint between the trimming network and the current source. The circuit also comprises an operational amplifier. The method (700) comprises measuring a first diode voltage across a replica element of the first diode; determining a first resistance of a replica element of the first resistor; and setting a resistance of the trimming network using the first diode voltage and the first resistance.

Abstract: A reference voltage generator includes a depletion NMOS transistor of a first conductivity type for causing a constant current to flow, and an enhancement NMOS transistor of the first conductivity type diode-connected to the depletion NMOS transistor to generate a reference voltage. A resistor surrounds the periphery of the depletion NMOS transistor and the periphery of the enhancement NMOS transistor. A diode is connected in series to a constant current source and provides a voltage that controls current flowing through the resistor when the environment temperature is lower than a preset temperature. The reference voltage generator can operate under a given preset temperature environment because a voltage consumed in the resistor becomes approximately constant in accordance with the voltage provided from the diode.

Abstract: To provide a protection circuit that can reduce output voltage that is output from a switching power supply greatly when temperature rises. A protection circuit includes a comparator that supplies detection current based on voltage Vsens that a temperature sensor outputs in case that voltage Vsens that the temperature sensor outputs exceeds voltage Vref of predetermined potential, a control circuit that supplies control current that the control circuit increases detection current that the comparator supplies exponentially, and a constant voltage circuit reduces output voltage Vout that is output from a switching power supply based on control current that the control circuit supplies.

Abstract: A reference current generating circuit may comprise a first transistor with a gate, a source and a drain and a second transistor with a gate, a source and a drain. The source of the first transistor and the source of the second transistor are connected to one another and the width-to-length ratios of the first and the second transistors are equal. A differential amplifier has two voltage inputs, of which the first is at a reference potential while the second is connected to a first node coupled to the drain of the first transistor. A reference current generating circuit is designed such that the drain-source voltage of the second transistor is greater in amount than the drain-source voltage of the first transistor. An output circuit is set up to output a reference current based on the current through the second transistor.

Abstract: An electronic circuit and methods of operating the electronic circuit are provided. The electronic circuit includes a pull-up transistor for pulling up an input/output (I/O) node of the output circuit to a first voltage and a first isolation transistor for coupling the pull-up transistor to the I/O node. The electronic circuit also includes a pull-down transistor for pulling down the I/O node to a second voltage and a second isolation transistor for coupling the pull-down transistor to the I/O node. In the electronic circuit, the pull-up and the pull-down transistors are transistors supporting a first drain-to-source voltage and a first gate-to-source voltage, while the first and the second isolation transistors are transistors supporting the first drain-to-source voltage and a second gate-to-source voltage greater than the first gate-to-source voltage.

Abstract: For a block of memory cells interconnected by single-ended bit lines, a sense amplifier receives the input from a single-ended bit line to determine the logic state of a selected memory cell connected to the single-ended bit line. The sense amplifier also receives a reference voltage generated from a base-emitter voltage of a emitter follower bipolar transistor. The base-emitter voltage is controllably divided by a voltage divider network with selectable resistive elements to tune the reference voltage.

Abstract: A reference voltage generator has a bandgap reference circuit and a negative voltage generator. The bandgap reference circuit generates a reference voltage according to at least one base-emitter voltage of at least one bipolar junction transistor. The negative voltage generator generates a negative voltage, wherein at least one base terminal of the at least one bipolar junction transistor is arranged to receive a base voltage derived from the negative voltage.

Abstract: A transducer such as a translinear proportional-to-absolute-temperature sensor uses two amplifiers, where each amplifier is used in a variety of modes. The first amplifier generates a measurement voltage though feedback in an analog circuit. The second amplifier samples and integrates the measurement in a switched-capacitor mode, and the output is stored on a capacitor. Then the first amplifier is set to measure its offset. The offset is sampled and integrated by the second amplifier, and the output is stored on a second capacitor. Then the first and second amplifiers are set to buffer the voltages stored on the capacitors. The measurement can then be offset-adjusted by digital or analog means. The adjusted measurement is then available to be used for calibration of, e.g., an image sensor. Other transducers, such as pressure sensors, strain sensors, gyroscopes, magnetometers, accelerometers, and xyz positioning sensors may employ the same dual amplifier approach.