Instruments And Devices For Fault Testing Patents (Class 324/555)
  • Publication number: 20110270565
    Abstract: A test fixture includes a first RS-232 connector and a second RS-232 connector. The data terminal ready (DTR) pin of the first RS-232 connector is connected to the DTR pin of the second RS-232 connector, and the clear to send (CTS) pin of the first RS-232 connector is connected to the CTS pin of the second RS-232 connector. The DTR pins are further connected to a power pin of each of the test computers. The test fixture sets a high level voltage for the connected DTR pins, and sets a low level voltage for the connected CTS pins according to the commands of turning on the test computers sent by the control computer, to turn on the test computers. An auto shutdown software included in each of the test computers is executed to shut down the test computers.
    Type: Application
    Filed: August 17, 2010
    Publication date: November 3, 2011
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD.
    Inventors: ZHI-CHUN LIANG, JUN-MIN CHEN, ZHI-JIAN LONG, FANG TIAN
  • Patent number: 8022712
    Abstract: The invention relates to a testing adapter suitable for testing a wireless telecommunication device. The testing adapter comprises a first contact member and a second contact member, the first contact member and the second contact member having at least one degree of freedom relative to each other and arranged to provide an attachable and detachable mechanical coupling with a surface of a component recess of the wireless telecommunication device on the basis of the at least one degree of freedom.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: September 20, 2011
    Assignee: JOT Automation Oy
    Inventors: Tuomo Mämmilä, Mika Piirainen, Mika Kellokoski
  • Patent number: 8013618
    Abstract: A voltage detection apparatus includes: a battery including unit cells mutually connected in series; a first block including at least one of the unit cells; a second block including at least one of the unit cells, and provided adjacent to the first block; a first voltage detector connected to the first block, which detects a voltage between both ends of the unit cell in the first block, and which includes: a current source; a current detection element connected to the current source; and a voltage measuring unit which detects a voltage between both ends of the current detection element; and a second voltage detector connected to the second block, which has a similar construction with the first voltage detector. An abnormality detector of the voltage detection apparatus detects an abnormality of the voltage detectors in accordance with the voltages between both ends of the current detection elements.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: September 6, 2011
    Assignee: Yazaki Corporation
    Inventors: Satoshi Ishikawa, Kimihiro Matsuura, Ryosuke Kawano
  • Patent number: 8008922
    Abstract: Apparatus and methods for testing a light fixture power circuit are therefore provided. The light fixture power circuit may energize a fluorescent lamp by providing power at first and second power terminals. The lamp holder may include a lamp pin guide for guiding the tube's contact pins toward the first and second power terminals. The apparatus may have probes that simulate the tube's contact pins. The probes may be robotically inserted into the lamp holder in a manner that is similar to the manner in which the contact pins would be inserted. This may eliminate the requirement to use fluorescent tubes to test the light fixture power circuit. The apparatus may include circuitry for testing the impedance of the light fixture power circuit at the first and second power contacts.
    Type: Grant
    Filed: February 23, 2009
    Date of Patent: August 30, 2011
    Assignee: Leviton Manufacturing Co., Inc.
    Inventors: Jesus Ortiz Balcazar, Leonel Garcia Chavez
  • Publication number: 20110193561
    Abstract: In an embodiment, a chuck to support a solar cell in hot spot testing is provided. This embodiment of the chuck comprises a base portion and a support portion disposed above the base portion. The support portion is configured to support the solar cell above the base portion and to define a space between a bottom surface of the solar cell and the base portion that thermally separates a portion of the bottom surface of the solar cell from the base portion.
    Type: Application
    Filed: February 10, 2010
    Publication date: August 11, 2011
    Applicant: SunPower Corporation
    Inventors: Jose Francisco Capulong, Emmanuel Abas
  • Publication number: 20110187386
    Abstract: A method of detecting a fault within a micro electro-mechanical device is provided. The micro electro-mechanical device has a support structure and an actuating arm that is movable relative to the support structure because of thermal expansion of at least part of the actuating arm caused by heat inducing current flow through at least that part. The method comprises the steps of passing a first current pulse having a predetermined duration tp through at least the part of the actuating arm and determining movement of the actuating arm in response thereto.
    Type: Application
    Filed: April 3, 2011
    Publication date: August 4, 2011
    Inventor: Kia Silverbrook
  • Patent number: 7990157
    Abstract: A card for simulating peripheral component interconnect (PCI) loads of a computer motherboard uses a PCI interface to be inserted into a PCI slot of the computer motherboard to receive first to third voltage signals from the computer. First to third load modules of the card receive voltage signals from the computer via the PCI interface to simulating first to third power consumption of the computer.
    Type: Grant
    Filed: July 15, 2009
    Date of Patent: August 2, 2011
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industy Co., Ltd.
    Inventors: Hai-Qing Zhou, Chung-Chi Huang
  • Patent number: 7986149
    Abstract: In one embodiment, a method for sensing an output fault condition is disclosed. The method includes monitoring an error signal that indicates an output fault condition, and monitoring an input signal having a duration. An error flag is set if a fast switching mode is detected and if the error signal is asserted within a specified time interval during the input signal duration.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: July 26, 2011
    Assignee: Infineon Technologies Austria AG
    Inventors: Andrei Covalenco, Bogdan Bumbacea
  • Publication number: 20110169520
    Abstract: An apparatus for measuring minority carrier lifetime is provided. The apparatus includes a resonant circuit having an inductor and a capacitor and configured to resonate at a measurement frequency. The apparatus also includes a ferromagnetic core having a first portion and a second portion. The first portion defines a gap and can be configured to direct therealong a magnetic field established by the inductor, such that lateral spreading of the magnetic field outside of the first portion is inhibited, and to direct the magnetic field generally uniformly across the gap. The second portion can be configured to direct the magnetic field therealong and, in conjunction with the first portion, into a closed loop. A radiation source can be configured to irradiate an area proximal to the gap defined by the first portion of the ferromagnetic core.
    Type: Application
    Filed: January 14, 2010
    Publication date: July 14, 2011
    Applicant: MKS INSTRUMENTS, INC.
    Inventors: G. Lorimer MILLER, Joseph W. FOSTER, David C. TIGWELL
  • Publication number: 20110169501
    Abstract: A sub-delay element has the same configuration as that of a main delay element, and applies a delay ? that corresponds to a bias voltage to a selected clock signal output from a first selector. A phase detectorgenerates a phase detection signal that corresponds to the phase difference between a selected clock signal that has propagated through the sub-delay element and a selected clock signal that has propagated through a bypass path. A counter performs a count operation according to the phase detection signal. A D/A converter supplies a bias voltage that corresponds to the count value of the counter to the main delay element and the sub-delay element. An initialization unit instructs a DLL circuit to actually operate, and sets the reference voltage to be supplied to the D/A converter based upon the fluctuation in the count value of the counter.
    Type: Application
    Filed: September 24, 2008
    Publication date: July 14, 2011
    Applicant: ADVANTEST CORPORATION
    Inventor: Naoki Sato
  • Publication number: 20110163755
    Abstract: A printed circuit board (“PCB”) test fixture is provided comprising a PCB support, an electrical tester, first and second enclosure portions, and an actuator. The PCB support is configured for supporting a PCB being tested in a PCB test position. The first enclosure portion includes a pressing device which is configured for effecting, with respect to a PCB supported in the PCB test position on the PCB support, pressing of a circuit of the PCB against the electrical tester so as to provide an operative circuit. The second enclosure portion extending peripherally about the PCB support. The actuator is coupled to a one of the first enclosure portion and the second enclosure portion and configured to effect an application of force to the one of the first enclosure portion and the second enclosure portion. The PCB support is disposed between the first and second enclosure portions.
    Type: Application
    Filed: January 5, 2010
    Publication date: July 7, 2011
    Applicant: RESEARCH IN MOTION LIMITED
    Inventors: Hongjun JIANG, Marek REKSNIS, Arkady IVANNIKOV
  • Publication number: 20110163760
    Abstract: A test circuit and system for testing one or more electrical properties of an electronic circuit or other device under test (DUT) by applying and monitoring test signals to the DUT is disclosed. The test circuit can utilize a plurality of universal interface channel circuits in a single automated test system to provide a unique and flexible approach for testing electronic circuits or devices that has many advantages. A single data acquisition circuit can coupled to one or more universal interface channel circuits. Each of the universal interface channel circuits can be independently commanded by the data acquisition circuit to provide one of a variety of test signals to a DUT as desired.
    Type: Application
    Filed: January 6, 2010
    Publication date: July 7, 2011
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: ERIC WADE ROUSE, PAUL DOUGLAS KELLEY
  • Patent number: 7969158
    Abstract: A noise-reduction method for processing a port is applied to a test target for testing or being burned in with software. At least one zero-Ohm resistor is provided with a first end thereof electrically connected to a device under test (DUT) of the test target and a second end thereof connected to a test port. Moreover, at least one grounding zero-Ohm resistor is provided with one end connected to ground and the other end is a floating end. After the test target is finished debugging or burned in with software, the connection of the first end and the DUT is disabled, and the second end is connected to ground through the floating end to reduce noise generation and improve a flexibility in circuit layout.
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: June 28, 2011
    Assignee: Foxconn Communication Technology Corp.
    Inventors: I-Chen Chen, Chien-Jung Lin, Chien-Hsun Ho
  • Patent number: 7969159
    Abstract: A system and method for determining the status of each monitored conductor, and optionally indicating peak current or other parameters are provided. Wireless self-powered sensor elements can eliminate much of the wiring required in traditional systems, and greatly ease the installation in difficult underground locations.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: June 28, 2011
    Assignee: Power Monitors, Inc.
    Inventors: Walter Curt, Christopher Mullins
  • Patent number: 7969157
    Abstract: A fault detection circuit connects to and determines the occurrence of failure in an inverter circuit. The inverter circuit comprises three outputs to connect three groups of lamps respectively, and the fault detection circuit comprises a magnetic unit and a signal detection unit. The magnetic unit comprises first, second and third flux generating windings electrically connected to the three outputs of the inverter circuit, and a flux detection winding. If no fault occurs on the outputs of the inverter circuit, total flux generated by the flux generating windings is cancelled out. As long as any fault occurs on the outputs of the inverter circuit, flux generated by the flux generating windings cannot be canceled out, and the flux detection winding is electromagnetically coupled accordingly and driven by the generated flux to output a coupling signal, based on which the signal detection unit generates an alert signal accordingly.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: June 28, 2011
    Assignees: Ampower Technology Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventors: Chih-Chan Ger, Chi-Chang Lu, Chia-Kun Chen
  • Patent number: 7969046
    Abstract: The present invention is to provide a power supply control apparatus which can connect a ground to a suitable electric potential when the ground is disconnected. The power supply control apparatus includes a control circuit having a switch element and a switch control unit, and a load. One terminal of load is connected to a direct-current power supply through the switch element, and the other terminal is connected to a ground electric potential. The switch control unit has a ground terminal connected to the ground electric potential and outputting a ground current flowing toward the ground electric potential. The control circuit includes a bypass device having a load side bypass system for passing the ground current to the ground electric potential through the load when connection between the ground terminal and the ground electric potential is disconnected.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: June 28, 2011
    Assignees: Yazaki Corporation, Toyota Jidosha Kabushiki Kaisha
    Inventors: Masashi Nakayama, Shigemi Ishima, Kazuhiro Aoki, Akihito Tsukamoto
  • Publication number: 20110148433
    Abstract: A high-voltage transformer for providing an alternating voltage in the kV range, comprising at least one secondary winding wound on a coil carrying body surrounding a transformer core, and an insulation housing encapsulating the secondary winding is provided to electrically insulate the secondary winding. Said insulation housing is walled by the coil carrying body carrying the secondary winding and by an enveloping body made of plastic and enveloping the secondary winding so that an annular gap is formed, wherein the annular gap between the secondary winding and the enveloping body is filled with an insulating fluid. The annular gap has a gap width of less than or equal to 20 mm viewed in the cross-section, and the enveloping body has a wall thickness of less than or equal to 20 mm, wherein the plastic is polypropylene, and a separate expansion volume is not provided for the insulating fluid.
    Type: Application
    Filed: March 3, 2011
    Publication date: June 23, 2011
    Applicant: B2 ELECTRONIC GMBH
    Inventors: Rudolf Blank, Stefan Baldauf
  • Publication number: 20110133752
    Abstract: An electronic device, and associated method, provided with a circuit board (10), with a set of input contacts (IN/COM), a set of output contacts (OUT/COM) and an electrical circuit (18) connected between the input contacts (IN/COM) and the output contacts (OUT/COM) and a controller. The controller carries out a real-time test of the circuit board using a test signal introduced into the electrical circuit, the electrical circuit (18) being designed as a passive network having a characteristic transfer function and provided with at least one capacitive element, wherein the capacitive element is a conductor surface (221) forming a capacitor in the assembled state with a corresponding, device-side conductor surface (222?), which is connected to the electrical circuit (18) via a contact element in the assembled state, whereby the capacitive value of the capacitive element in the assembled state differs from the capacitive value of the capacitive element in the disassembled state.
    Type: Application
    Filed: December 2, 2010
    Publication date: June 9, 2011
    Applicant: SARTORIUS AG
    Inventors: Swen Weitemeier, Christian Oldendorf
  • Publication number: 20110133751
    Abstract: Provided is a signal generating apparatus comprising a DA converter that outputs an output signal corresponding to input data supplied thereto; a sample/hold unit that is provided between the DA converter and an output end of the signal generating apparatus, and that samples an output voltage of the DA converter and holds the sampled output voltage; a comparing section that compares (i) a level of a signal output from an analog circuit that propagates the output signal to output a signal corresponding to the input data to (ii) a level of the signal output by the DA converter; and a control section that, during a holding period, (iii) provides the DA converter with comparison data instead of the input data to cause the DA converter to output a comparison voltage corresponding to the comparison data, (iv) causes the comparing section to compare a voltage of the signal output by the analog circuit to the comparison voltage, and (v) adjusts the output voltage of the DA converter according to the input data based
    Type: Application
    Filed: December 8, 2009
    Publication date: June 9, 2011
    Applicant: ADVANTEST CORPORATION
    Inventor: Yasuhide KURAMOCHI
  • Publication number: 20110133754
    Abstract: Exemplary embodiments are directed to a test arrangement for testing surge voltage in electrical high voltage components with a surge voltage generator and a voltage distributor. The surge voltage generator and voltage distributor have a tower-like structure with a first and a second structure end. A rectangular container is connected to the first and second structure and includes a first and a second container end. At least one of the surge voltage generator and the voltage distributor are movable between a first substantially horizontal position inside the container and a substantially vertical position relative to the container. Each movement between the two positions involves a pivot motion about a rotational axis perpendicular to the longitudinal direction of the surge voltage generator.
    Type: Application
    Filed: December 7, 2010
    Publication date: June 9, 2011
    Applicant: ABB TECHNOLOGY AG
    Inventors: Peter WERLE, Matthias Steiger
  • Publication number: 20110133753
    Abstract: An electronic device, and associated method, provided with a circuit board (10), with a set of input contacts (IN/COM), a set of output contacts (OUT/COM) and an electrical circuit (18) connected between the input contacts (IN/COM) and the output contacts (OUT/COM) and a controller. The controller carries out a real-time test of the circuit board using a test signal introduced into the electrical circuit, the electrical circuit (18) being designed as a passive network having a characteristic transfer function and provided with at least two separate partial circuits (18?, 18?) wherein the separate partial circuits are electrically connected in the assembled state by cooperation with at least one of: at least one device components and/or assembly components (181).
    Type: Application
    Filed: December 2, 2010
    Publication date: June 9, 2011
    Applicant: SARTORIUS AG
    Inventors: Swen Weitemeier, Christian Oldendorf
  • Patent number: 7944212
    Abstract: A tester is disclosed for testing a wiring state of a live electrical receptacle outlet. The tester comprises a body having a display located thereon and a plug extending from the body. The display is configured to selectively provide a text indicator. When the plug of the tester is received in the electrical outlet, the display indicates the wiring state of the electrical outlet.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: May 17, 2011
    Assignee: Actuant Corporation
    Inventors: Patrick J. Radle, Anthony W. Gilbert, David L. Wiesemann, Daryl C. Brockman
  • Publication number: 20110109321
    Abstract: Provided is a test apparatus that tests a device under test, comprising a digital signal generator that outputs in parallel one or more n-bit digital test signals, where n is an integer greater than or equal to 1; a plurality of driver circuits that are connected respectively to a plurality of digital terminals of the device under test; and an analog signal generator that generates an analog test signal by converting, into an analog signal, an n×m-bit digital multi-bit signal based on the one or more digital test signals output by the digital signal generator to the plurality of driver circuits, where m is an integer greater than or equal to 2.
    Type: Application
    Filed: November 11, 2009
    Publication date: May 12, 2011
    Applicant: ADVANTEST CORPORATION
    Inventors: Masayuki KAWABATA, Toshiyuki OKAYASU
  • Publication number: 20110109322
    Abstract: A testing system utilizing a common power supply and a display device to test different types of a main board circuit is disclosed. The testing system includes a power supply device for outputting a predetermined power; a liquid crystal display for receiving a control signal from the main board circuit to perform a testing procedure; and an adapter. The adapter includes a first circuit coupled electrically between the power supply device and the main board circuit for converting the predetermined power into a power needed by the main board circuit, and a second circuit coupled electrically between the main board circuit and the liquid crystal display for converting a control signal generated by the main board circuit into a signal format required to perform the testing procedure on the liquid crystal display.
    Type: Application
    Filed: September 10, 2010
    Publication date: May 12, 2011
    Applicant: Wistron Corporation
    Inventors: Kai-Fu Shi, Zhen-Wu Xu
  • Patent number: 7940059
    Abstract: A method for measuring an on resistance in an H-bridge including first and second transistors connected to a first output terminal, third and fourth transistors connected to a second output terminal, and a measurement switch connected to the first and second output terminals. The first and third transistors are connected to a first power supply terminal. The second and fourth transistors are connected to a second power supply terminal. The method includes supplying the first transistor with measurement current during a first period, measuring a first voltage at the first power supply terminal via the third transistor using the second output terminal during the first period, measuring a second voltage at the first output terminal via the measurement switch using the second output terminal during the first period, and determining the on resistance of the first transistor based on the measurement current, first voltage, and second voltage.
    Type: Grant
    Filed: August 25, 2008
    Date of Patent: May 10, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Akihiro Takahashi, Hidetaka Fukazawa
  • Patent number: 7936172
    Abstract: A self test adapter (STA) for automatic test equipment (ATE) is provided. The STA includes an enclosure. A backplane is housed by the enclosure. A dual data bus is integrated into the backplane. At least one STA card module is inserted into the backplane. The at least one STA card module has a port for interconnection with an ATE station receiver. The at least one STA card module includes a generic region adapted for interfacing with an additional STA card module over the dual data bus, and a resource specific region adapted for self test of at least one ATE station resource.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: May 3, 2011
    Assignee: Honeywell International Inc.
    Inventors: Kenny Nordstrom, Ralph Jones, Krishna Munirathnam
  • Patent number: 7932724
    Abstract: A circuit assemblage for functional checking of a power transistor includes a power transistor having an insulated gate, a first power electrode configured as a drain or as a collector, and a second power electrode configured as a source or an emitter, the first and second power electrode being connected to a power circuit having a DC voltage source and an electrical DC load. The circuit assemblage further includes a control application device having a signal output that is connected to the gate; a capacitance measuring device for measuring the gate terminal capacitance between the gate terminal contact and the second power electrode terminal contact; and an evaluation device for comparing the gate terminal capacitance with the gate capacitance, and outputting a fault signal as a function of the comparison.
    Type: Grant
    Filed: November 10, 2006
    Date of Patent: April 26, 2011
    Assignee: Robert Bosch GmbH
    Inventor: Klaus Voigtlaender
  • Patent number: 7924031
    Abstract: An in-situ method for monitoring the health of a composite component utilizes a condition sensor made of electrically conductive particles dispersed in a polymeric matrix. The sensor is bonded or otherwise formed on the matrix surface of the composite material. Age-related shrinkage of the sensor matrix results in a decrease in the resistivity of the condition sensor. Correlation of measured sensor resistivity with data from aged specimens allows indirect determination of mechanical damage and remaining age of the composite component.
    Type: Grant
    Filed: August 23, 2006
    Date of Patent: April 12, 2011
    Inventors: Kenneth S. Watkins, Jr., Shelby J. Morris
  • Patent number: 7902834
    Abstract: An upgradeable test set is that includes a stimulator circuit to transmit test signals to an electrical equipment under test, a coupling to removeably couple at least the stimulator circuit to one of a plurality of front-end interfaces. The plurality of front-end interfaces include a first front-end interface having a first display and a first input device and a second front-end interface having a second display and a second input device. The first display and the second display have different display characteristics, and the first input device and the second input device have different characteristics. The one of the front-end interfaces communicates a test control parameter to the stimulator circuit and a response of the electrical equipment under test is communicated to the one of the front-end interfaces. The case is configured to enclose the stimulator circuit, the one of the front-end interfaces, and the coupling.
    Type: Grant
    Filed: May 2, 2008
    Date of Patent: March 8, 2011
    Assignee: AVO Multi-Amp Corporation
    Inventors: Gregory R. Wolfe, Peter H. Merl, Warren G. Southard
  • Publication number: 20110043952
    Abstract: The invention relates to a device for the prevention of serious faults in electrical mains supply networks by spectral analysis of the network voltage. The spectrum determined by a voltage A/D converter and a spectral analysis device is subjected to a classification by frequency intervals. The values for the frequency interval classes are correlated in the comparator with frequency interval class reference patterns for corresponding determined faults.
    Type: Application
    Filed: February 25, 2005
    Publication date: February 24, 2011
    Inventors: Werner Haussel, Michael Fett, Martin Hofbeck
  • Patent number: 7888947
    Abstract: A method for use with automatic test equipment (ATE) includes programming the ATE to generate bursts, each of which corresponds to a signal characteristic produced by the ATE, obtaining power levels for the bursts, and determining if the power levels for the bursts correspond to expected power levels for signal characteristics corresponding to the bursts.
    Type: Grant
    Filed: November 21, 2007
    Date of Patent: February 15, 2011
    Assignee: Teradyne, Inc.
    Inventors: Rodney Singleton, Senay Abbay, Daniel Busuioc
  • Patent number: 7884617
    Abstract: An electro-static discharge (ESD) detection circuit is provided. The ESD detection circuit includes: a first power pad for receiving a first supply voltage; a second power pad for receiving a second supply voltage; an RC circuit having an impedance component coupled between the first power pad and a first terminal and having an capacitive component coupled between the first terminal and a second terminal, wherein the second terminal is not directly connected to the second supply voltage; a trigger circuit couples to the first power pad, the second power pad, and the RC circuit, for generating an ESD trigger signal according to a voltage level at the first terminal and a voltage level at the second terminal, and a bias circuit coupled between the first power pad and the second power pad for providing a bias voltage to the second terminal.
    Type: Grant
    Filed: December 14, 2008
    Date of Patent: February 8, 2011
    Assignee: Faraday Technology Corp.
    Inventors: Ming-Dou Ker, Po-Yen Chiu, Chun Huang
  • Publication number: 20110025344
    Abstract: A holding member for use in a test includes a base made of silicon or glass and chips in which devices are formed is mountable thereon. Positioning members made of resist sheets are formed on the top surface of the base. A resist film is formed on the bottom surface of the base, and suction grooves (intersection portions, connection portions) and support members are formed in the resist film. Suction holes are formed in regions of the top surface of the base where the chips are mounted, wherein the suction holes are formed through the base and communicate with the suction groove.
    Type: Application
    Filed: November 5, 2008
    Publication date: February 3, 2011
    Applicant: Tokyo Electron Limited
    Inventors: Yasunori Kumagai, Shigekazu Komatsu
  • Publication number: 20110025370
    Abstract: A system and method is provided for ground testing of a yaw system of a nacelle (3) prior to erection of a wind turbine (1). A portable transformer box (10) is provided which will allow the nacelle preparation team to operate the yaw and hydraulic systems while the nacelle is grounded prior to erection.
    Type: Application
    Filed: July 31, 2009
    Publication date: February 3, 2011
    Inventor: Donald J. Oswald
  • Publication number: 20110025171
    Abstract: There is provided a method for testing a piezoelectric/electrostrictive actuator, wherein the displacement of a piezoelectric/electrostrictive actuator is estimated on the basis of the relations between one or more frequency characteristic values selected from the group consisting of the heights and areas of the peaks of the resonance waveforms and the difference of the maximum and minimum of the first order or first to higher orders of the resonance frequency characteristic values of the piezoelectric/electrostrictive actuator and the k-th order (k=1 to 4) of the first or first to higher orders of resonance frequencies. According to this piezoelectric/electrostrictive actuator testing method, a piezoelectric/electrostrictive actuator can be tested with high precision without actually driving the same as a product and without being accompanied by any disassembly/breakage.
    Type: Application
    Filed: October 15, 2010
    Publication date: February 3, 2011
    Applicant: NGK Insulators, Ltd.
    Inventors: Naoki Goto, Takao Ohnishi
  • Publication number: 20110018552
    Abstract: A coupon board is cut out together with a printed wiring board from a sheet material in which a solder resist film is formed on a surface of a glass cloth fiber. The coupon board is for evaluating characteristics of the printed wiring board. The coupon board includes a region on which the solder resist film is not formed, and which extends parallel with one side of the printed wiring board.
    Type: Application
    Filed: July 1, 2010
    Publication date: January 27, 2011
    Applicant: FUJITSU LIMITED
    Inventors: Kaoru Sugimoto, Katsuhiko Kobayashi
  • Publication number: 20110012617
    Abstract: A digital-to-analog converter (DAC)/amplifier testing system for use in an electron-beam (e-beam) mask writer, the e-beam mask writer including a plurality of DAC/amplifier circuits to output analog voltage signals, each DAC/amplifier circuit having a first output terminal and a second output terminal, the first output terminals of the plurality of DAC/amplifier circuits being respectively coupled to deflection plates of the e-beam mask writer to provide the output analog voltages as deflection voltages, is provided. The testing system including a summation circuit to sum voltage signals and to output a summation signal indicating the sum of the received analog voltage signals and an analyzer circuit to digitize the summation signal and to detect to compare the digitized summation signal with an error tolerance range to detect whether at least one of the DAC/amplifier circuits is experiencing an operating error.
    Type: Application
    Filed: July 16, 2009
    Publication date: January 20, 2011
    Inventors: Yoshikuni GOSHIMA, Seiichi Tsuchiya, Yoshimasa Sanmiya, John William Kay, Chising Lai
  • Patent number: 7872467
    Abstract: A small light-weight battery operated calibrator device provides a precise sine wave output for use in calibration of test equipment, such as a RF Power Meter or a Spectrum Analyzer. The calibration device includes two power levels, one ?40 dBm and one 0 dBm. The purpose of the two power levels is to obtain a slope and offset for correction of the RF power measuring device being calibrated. Operation indication LED lights are provided to indicate which of the two powers are in use, and if battery power is below acceptable levels. Miniature low power components including a crystal oscillator and a divide by 2 integrated circuit that generates a precise square wave and a low pass filter for converting the square wave into a precise sine wave allows the calibrator to be battery operated and stored as a calibration component.
    Type: Grant
    Filed: February 18, 2010
    Date of Patent: January 18, 2011
    Assignee: Anritsu Company
    Inventor: Donald Anthony Bradley
  • Publication number: 20110006783
    Abstract: A card for simulating peripheral component interconnect (PCI) loads of a computer motherboard uses a PCI interface to be inserted into a PCI slot of the computer motherboard to receive first to third voltage signals from the computer. First to third load modules of the card receive voltage signals from the computer via the PCI interface to simulating first to third power consumption of the computer.
    Type: Application
    Filed: July 15, 2009
    Publication date: January 13, 2011
    Applicants: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: HAI-QING ZHOU, CHUNG-CHI HUANG
  • Patent number: 7868625
    Abstract: The slot interposer probe consists of a board with a male edge connector and a female edge connector connected to its opposed edges and circuitry electrically connecting the male edge connector to the female edge connector. The female edge connector may be a straddle-mount connector. The board may have an inner layer sandwiched between two outer layers. There may be a probe having a high-speed buffer connected to a plurality of capacitors, isolation resistors, and vias that intercepts signals carried by transmission lines on the inner layer. The vias may have a length equal to the inner layer's width. The high-speed buffer receives intercepted signals from the vias, copies and amplifies the signals, and drives them through coaxial cables to an acquisition module. The invention also includes a method of intercepting signals between a first electrical device and a second electrical device.
    Type: Grant
    Filed: May 15, 2008
    Date of Patent: January 11, 2011
    Assignee: Tektronix, Inc.
    Inventors: Devin G. Burt, Joshua J. O'Brien, David W. Koch, Roxann R. Jones
  • Patent number: 7863922
    Abstract: Provided is a method of evaluating dielectric breakdown by applying a current to an insulating film, in which measurement for a forward direction current and measurement for a backward direction current are performed in a short period of time. For this purpose two MOS diodes in which an electrode of one MOS diode and a base of another MOS diode are short-circuited respectively are prepared to form a circuit to which the current is applied, providing current flow in one insulating film reverse to current flow in another insulating film, which enables the application of both the forward direction current and the backward direction current.
    Type: Grant
    Filed: February 2, 2009
    Date of Patent: January 4, 2011
    Assignee: Seiko Instruments Inc.
    Inventor: Kiyohiro Tsuru
  • Publication number: 20100301886
    Abstract: A test board is provided. The test board includes a power connecting interface, diode modules, a power module a detecting module, and a processor. The power connecting interface includes power pins, wherein each of the power pins is electrically connected to a motherboard power socket to receive a power signal. Each of the diode modules is electrically connected to one of the power pins and includes at least one diode. The power module is electrically connected to the diode modules to receive the power signal through each of the diode modules. The detection module is electrically connected to points between the diode modules and the power connecting interface to generate a detection result according to the voltage between each diode module and the power connecting interface. The processor is used to determine the connecting state between the power pin and the corresponding motherboard power socket according to the detection result.
    Type: Application
    Filed: July 20, 2009
    Publication date: December 2, 2010
    Applicant: INVENTEC CORPORATION
    Inventors: Chih-Jen CHIN, Chun-Hao CHU, Ting-Hong WANG, Sheng-Yuan TSAI
  • Publication number: 20100283480
    Abstract: Provided is a test apparatus that tests a device under test, wherein the device under test includes an internal circuit that generates a plurality of internal clocks having different phases based on a reference clock provided thereto, selects from among the internal clocks an internal clock having a predetermined relative phase with respect to an input signal having a frequency substantially equal to that of the internal clocks, and samples the input signal according to the selected internal clock.
    Type: Application
    Filed: April 26, 2010
    Publication date: November 11, 2010
    Applicant: ADVANTEST CORPORATION
    Inventors: Kenichi NAGATANI, Masahiro ISHIDA
  • Publication number: 20100271046
    Abstract: A method, an apparatus and a computer program product are provided for implementing At-Speed Wafer Final Test (WFT) with total integrated circuit chip coverage including high speed off-chip receiver and driver input/output (I/O) circuits. An integrated circuit (IC) chip includes off-chip Controlled Collapse Chip Connection (C4) nodes and a driver and a receiver of the off-chip receiver and driver input/output (I/O) circuits connected to respective off-chip C4 nodes. Through Silicon Vias (TSVs) are added to the connections of the driver and the receiver and the respective off-chip C4 nodes to a backside of the IC chip. A metal wire is added to the IC chip backside connecting the TSVs and creating a connection path between the driver and the receiver that is used for the at-speed WFT testing of the I/O circuits.
    Type: Application
    Filed: April 24, 2009
    Publication date: October 28, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson, Dennis Martin Rickert
  • Patent number: 7821754
    Abstract: A circuit arrangement for producing a defined output signal in CMOS integrated circuit is provided in which the output of a sensor signal conditioning circuit is connected to the drain terminal of a first N channel depletion transistor, to a source terminal of a second N channel depletion transistor and to the output (OUT) of an integrated CMOS circuit. The gate terminals of the first and second N channel depletion transistors are connected to the output (VP) of a control circuit and the first terminal of a discharge resistance. The second terminal of the discharge resistance and the source terminal of the first N channel depletion transistor are connected to a potential VSS, and the drain terminal of the second N channel depletion transistor is connected to a potential VDD.
    Type: Grant
    Filed: August 11, 2006
    Date of Patent: October 26, 2010
    Assignee: Zentrum Mikroelektronik Dresden AG
    Inventor: Mathias Krauss
  • Publication number: 20100264934
    Abstract: A processing device is provided with a circuit connected to a first conductive portion and a second conductive portion. An AC voltage source produces an AC waveform voltage obtained by adding a bias voltage to an AC voltage for capacitance measurement. The AC waveform voltage is applied between the first conductive portion and the second conductive portion through the measurement probes. The moment the AC waveform voltage is applied to the circuit with a switch closed, an inrush current flows through the circuit based on a potential difference of the bias voltage. This inrush current causes dielectric breakdown in the conductive resin, thereby securing the continuity of the conductive resin. With the continuity of the conductive resin secured, a capacitance of the piezoelectric body is measured by the AC waveform voltage, and it is determined whether or not the piezoelectric body is normal.
    Type: Application
    Filed: April 14, 2010
    Publication date: October 21, 2010
    Applicant: NHK Spring Co., Ltd.
    Inventors: Masaru INOUE, Osamu Okawara, Hideki Fuchino
  • Patent number: 7816925
    Abstract: An electrical continuity tester for testing the continuity of a cable between one end to another end, includes a main housing having first and second ends; a first test port disposed at the first end, the first test port for being connected to one end of a cable being tested; a circuit disposed within the main body operably connected to the first test port, the circuit including a first indicator for indicating the continuity of a cable being tested; a coupler removably secured to the main housing; and a terminator removably secured to the coupler, the terminator for connecting to another end of a cable being tested, the terminator including a second indicator for indicating the continuity of the cable being tested when the first test port is connected to the one end of the cable.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: October 19, 2010
    Inventor: Robert D. Gale
  • Publication number: 20100244866
    Abstract: A method of testing an integrated circuit of a device is described. Air is allowed through a fluid line to modify a size of a volume defined between the first and second components of an actuator to move a contactor support structure relative to the apparatus and urge terminals on the contactor support structure against contacts on the device. Air is automatically released from the fluid line through a pressure relief valve when a pressure of the air in the fluid line reaches a predetermined value. The holder is moved relative to the apparatus frame to disengage the terminals from the contacts while maintaining the first and second components of the actuator in a substantially stationary relationship with one another. A connecting arrangement is provided including first and second connecting pieces with complementary interengaging formations that restricts movement of the contactor substrate relative to the distribution board substrate in a tangential direction.
    Type: Application
    Filed: March 25, 2009
    Publication date: September 30, 2010
    Applicant: Aehr Test Systems
    Inventors: Scott E. Lindsey, Junjye Yeh, Jovan Jovanovic, Seang P. Malathong
  • Publication number: 20100244854
    Abstract: A semiconductor device includes a common probing pad; an internal voltage generation unit having a plurality of internal voltage generation blocks configured to generate a plurality of internal voltages; and a probing voltage selection unit configured to transfer an internal voltage selected from the internal voltages to the common probing pad in response to a plurality of voltage selection signals.
    Type: Application
    Filed: June 30, 2009
    Publication date: September 30, 2010
    Inventor: Khil-Ohk Kang
  • Publication number: 20100238972
    Abstract: An apparatus that allows for the testing of multiple wraps of cable in environments of varying temperature, pressure, and in different fluids in a single apparatus, and can be tested against the varying loads the cable may encounter is disclosed. In the illustrative embodiment of the present invention, the multiple wraps of cable are simulated by layering electrically-insulated portions of the cable on top of one another inside an environmentally controlled container. This container has two parts: a thermally-insulated container and a pressure container.
    Type: Application
    Filed: March 20, 2009
    Publication date: September 23, 2010
    Applicant: LOCKHEED MARTIN CORPORATION
    Inventor: Alain T. Pellen