Abstract: A sheet electric resistance measuring instrument includes first and second housings that are paired with each other and that sandwich a sheet from both sides of the sheet, a pair of electrodes that are provided on the first housing and that measure an electric resistance of the sheet sandwiched between the pair of electrodes and the second housing, and a contact member that is disposed between the pair of electrodes on the first housing and that is brought into contact with the sheet.

Abstract: A method for electrically characterizing a layer disposed on a substrate and electrically insulated from the substrate is disclosed. The method can include forming a test pattern, contacting the test pattern with electrical contact elements at contact regions, and measuring an electrical parameter of the layer by passing a first set of test currents between contact regions. The test pattern can be formed by pushing a pattern forming head against a top surface of the layer, introducing a first fluid into the cavity, and converting the sacrificial portion of the layer into an insulator using the first fluid and forming the test pattern under the test-pattern-shaped inner seal.

Abstract: An electronic device, which includes at least a first part and a second part bonded to each other is provided. The first part includes a first bonding area. The first bonding area includes at least one first testing area. The first testing area includes a plurality of testing pads. The second part includes a second boding area corresponding to the first bonding area. The second bonding area includes a plurality of testing terminals, and includes at least one second testing area respectively corresponding to the at least one first testing area. The second testing area includes a plurality of testing pins. The plurality of testing pads, the plurality of testing terminals and the plurality of testing pins are configured to form a current channel and a voltage testing channel, for measuring a resistance of bonded testing pads and testing pins on both the current channel and the voltage testing channel.

Abstract: A lidar sensor assembly includes a detector array having a plurality of photodetectors. An integrated circuit is bonded to the detector array via a plurality of connection bumps. A reference trace is defined by conductive material on at least one of the integrated circuit and the detector array. A test trace is defined by conductive material on the detector array, at least two of the connection bumps, and conductive material on the integrated circuit. A resistance measuring device is configured to independently measure a reference resistance along the reference trace and a test resistance along the test trace. The assembly also includes a processor in communication with the resistance measuring device. The processor is configured to receive the reference resistance and the test resistance, subtract the reference resistance from the test resistance to produce a bond resistance, and compare the bond resistance to a predetermined resistance value.

Abstract: A resistance measurement device for measuring sheet resistance of an electrically conductive film that is long in one direction includes a probe unit disposed to face the electrically conductive film; a scanning unit that allows the probe unit to scan in a cross direction crossing the one direction over both a conveyance region and a non-conveyance region of the electrically conductive film; and an arithmetic unit that calculates a sheet resistance of the electrically conductive film based on a voltage measured by the probe unit. The arithmetic unit has a memory that memorizes a reference voltage measured in the non-conveyance region, and corrects, based on the reference voltage, an actual voltage measured by allowing the probe unit to scan in the cross direction in the conveyance region.

Abstract: One example describes a method of manufacturing Czochralski (CZ) silicon wafers. The method includes slicing an n-type CZ silicon ingot to form a plurality of CZ silicon wafers, determining a boron concentration of each CZ silicon wafer, dividing the CZ silicon wafers into sub-groups based on the boron concentration, wherein an average value of the boron concentration differs among the sub-groups, and labeling each sub-group of CZ silicon wafers with a different label which is indicative of the boron concentration.

Abstract: Disclosed is a system and method for monitoring a characteristic of an environment of an electronic device. The electronic device may include a printed circuit board and a component. A sensor is placed on the printed circuit board, and may be between the component and the board, and connects to a monitor, or detector. An end user device may be used to store, assess, display and understand the data received from the sensor through the monitor.

Abstract: The present disclosure provides a system and method for providing electrostatic discharge protection. A probe card assembly is provided which is electrically connected to a plurality of input/output channels. The probe card assembly can be contacted with a secondary assembly having an interposer electrically connected to one or more wafers each wafer having a device under test. Voltage can be forced on ones of the plural input/output channels of the probe card assembly to slowly dissipate charges resident on the wafer to thereby provide electrostatic discharge protection. A socket assembly adaptable to accept a 3DIC package is also provided, the assembly having a loadboard assembly electrically connected to a plurality of input/output channels. Once the 3DIC package is placed within the socket assembly, voltage is forced on ones of the input/output channels to slowly dissipate charges resident on the 3DIC package to thereby provide electrostatic discharge protection.

Abstract: Metal film thickness can be determined using the sheet resistance, resistivity, and temperature coefficient of resistivity for the metal film. Variation in film thickness measurements caused by resistivity can be reduced or eliminated. A probe head may be used for some of the measurements of the metal film. The probe head can include a temperature sensor used during sheet resistance measurements. A wafer on a chuck is heated, such as using the chuck or the probe head, for the measurements.

Abstract: Systems and methods for processing test results. A method of analyzing test results includes receiving a set of test result files, the set of test result files including a plurality of test results. The method also includes identifying a set of data filters based on one or more of the set of test result files or user input. The method further includes generating filtered results based on the set of data filters and the set of test result files, the filtered results including one or more of a subset of the plurality of test results or reordered test results. The method further includes providing a visual representation of the filtered results.

Abstract: The disclosure is related to an SSRM method for measuring the local resistivity and carrier concentration of a conductive sample. The method includes contacting the conductive sample at one side with an AFM probe and at another side with a contact electrode, modulating, at a modulation frequency, the force applied to maintain physical contact between the AFM probe and the sample while preserving the physical contact between the AFM probe and the sample, thereby modulating at the modulation frequency the spreading resistance of the sample; measuring the current flowing through the sample between the AFM probe and the contact electrode; and deriving from the measured current the modulated spreading resistance. Deriving the modulated spreading resistance includes measuring the spreading current using a current-to-voltage amplifier, converting the voltage signal into a resistance signal, and filtering out from the resistance signal, the resistance amplitude at the modulation frequency.

Abstract: An embodiment of an amplifier has a bandwidth defined by low and upper cutoff frequencies. The amplifier includes an input impedance matching circuit and a transistor. The transistor has a gate, a first current conducting terminal coupled to an output of the amplifier, and a second current conducting terminal coupled to a reference node. The input impedance matching circuit has a filter input coupled to an input of the amplifier, a filter output coupled to the gate of the transistor, and a multiple pole filter coupled between the filter input and the filter output. A first pole of the filter is positioned at a first frequency within the bandwidth, and a second pole of the filter is positioned at a second frequency outside the bandwidth. The input impedance matching circuit is configured to filter the input RF signal to produce a filtered RF signal at the filter output.

Abstract: An apparatus for, and methods of use for, measuring film thickness on an underlying body are provided. The apparatus may include at least one Impedance Resonance (IR) sensor, which may include at least one sensing head. The at least one sensing head may include an inductor having at least one excitation coil and at least one sensing coil. The excitation coil may propagate energy to the sensing coil so that the sensing coil may generate a probing electromagnetic field. The apparatus may also include at least one power supply, at least one RF sweep generator electrically connected to the excitation coil; at least one data acquisition block electrically connected to the sensing coil; at least one calculation block; and at least one communication block. Methods of monitoring conductive, semiconductive or non-conductive film thickness, and various tools for Chemical Mechanical Polishing/Planarization (CMP), etching, deposition and stand-alone metrology are also provided.

Abstract: A circuit device mounted on a substrate includes a detection circuit that monitors a characteristic of a return signal to determine an integrity of various interconnects of the device.

Abstract: There are proposed a stack type semiconductor device and a method of fabricating and testing the same. A stack type semiconductor device according to an embodiment of the present invention includes a plurality of contact pads externally exposed, a via array electrically connected to the contact pads, a semiconductor substrate configured to have vias, forming the via array, electrically conductive with each other or insulated from each other, and a bias pad configured to supply a bias to the semiconductor substrate, wherein the semiconductor substrate may be subject to back-grinding.

Abstract: An ozone gas generation processing apparatus that includes a light source of ultraviolet rays and a wafer placement section, generates ozone gas by irradiating ultraviolet rays from the light source in an atmosphere containing oxygen, and processes a wafer on the wafer placement section with the ozone gas, the ozone gas generation processing apparatus comprising a light-blocking plate that allows the generated ozone gas to pass therethrough and blocks the ultraviolet rays between the light source and the wafer placed on the wafer placement section. An ozone gas generation processing apparatus and a method of forming an oxide film silicon film can make an adjustment to make thinner an oxide film formed on a wafer surface, the wafer surface is not damaged by ultraviolet rays when processed, and a method for evaluating a silicon single crystal wafer, obtaining a more stable measurement value of C-V characteristics are provided.

Abstract: Disclosed herein is an oscillation circuit including: a control transistor changing an electric potential at an output terminal thereof by proceeding to one of a conduction state and a non-conduction state in accordance with an electric potential at an input terminal thereof; a transistor as an object of a measurement having a polarity of a channel identical to that of the control transistor, and connected in series with the control transistor between a power source and a ground; a capacitor delaying the change in the electric potential at the output terminal in accordance with a value of a leakage current leaked from the transistor as an object of a measurement when the control transistor proceeds from the conduction state to the non-conduction state; and an inversion circuit inverting the electric potential at the output terminal, thereby feeding the inverted electric potential back to the input terminal.

Abstract: A system for measuring the conductivity of a material-under-test includes a support structure, an upper magnet mounted to the support structure and a free-floating magnet below the fixed magnet. The system includes a diamagnet positioned between the fixed magnet and the free-floating magnet such that the free-floating magnet floats in the air beneath the diamagnet and a rotation detection assembly configured to detect a rotation rate of the free-floating magnet, where the rotation rate is based on a drag torque effect of a material-under-test on the free-floating magnet. The system also includes a conductivity calculation unit configured to calculate at least one of a conductivity or a resistivity of the material-under-test based on the detected rotation rate of the free-floating magnet.

Abstract: A method detects one or more cracks in a piezoelectric element interposed between a pair of electrodes and deforms according to a voltage applied thereto through the pair of electrodes. The method includes steps of applying a voltage at least at a resonance frequency of the piezoelectric element to the piezoelectric element through the pair of electrodes, measuring a dielectric tangent between the pair of electrodes under the applied voltage, and detecting if there are cracks in the piezoelectric element according to the measured dielectric tangent. The dielectric tangent of the piezoelectric element at the resonance frequency has a large peak or no peak depending on whether or not the piezoelectric element has cracks. Accordingly, the method easily and surely detects if the piezoelectric element has cracks according to the dielectric tangent of the piezoelectric element measured at the resonance frequency.

Abstract: According to one embodiment, a semiconductor module comprises a substrate, a first wiring, an electrode pad, a junction, an oscillator, and a detector. The first wiring is disposed on the substrate, and has a characteristic impedance Z0. The electrode pad is connected to the first wiring. The junction is disposed on the electrode pad, and has an impedance Z1. The oscillator is disposed in contact with the first wiring, and oscillates a pulse wave of a voltage toward the junction via the first wiring. The detector is disposed in contact with the first wiring, and detects an output wave of the pulse wave from the junction. The characteristic impedance Z0 and the impedance Z1 satisfy a following relationship (1), ? Z ? ? 0 - Z ? ? 1 Z ? ? 0 ? ? 0.05 .

Abstract: An apparatus and method of testing electrical impedance of a multiplicity of regions of a photovoltaic surface includes providing a multi-tipped impedance sensor with a multiplicity of spaced apart impedance probes separated by an insulating material, wherein each impedance probe includes a first end adapted for contact with a photovoltaic surface and a second end in operable communication with an impedance measuring device. The multi-tipped impedance sensor is used to contact the photovoltaic surface and electrical impedance of the photovoltaic material is measured between individual first ends of the probes to characterize the quality of the photovoltaic surface.

Abstract: An Integrated Circuit (IC) and a method of making the same. In one embodiment, an integrated circuit includes: a substrate; a first metal layer disposed on the substrate and including a sensor structure configured to indicate a crack in a portion of the integrated circuit; and a second metal layer disposed proximate the first metal layer, the second metal layer including a wire component disposed proximate the sensor structure.

Abstract: An analysis circuit for a field effect transistor having a displaceable gate structure, includes a measurement circuit coupled between a supply voltage connection of the analysis circuit and a drain connection of the field effect transistor and configured to output a measurement signal that is dependent on the current strength of a current flowing through the field effect transistor to a measurement connection.

Abstract: The present invention discloses a structure and a method for determining a defect in integrated circuit manufacturing process. Test keys are designed for the structure to be the interlaced arrays of grounded and floating conductive cylinders, and the microscopic image can be predicted to be an interlaced pattern of bright voltage contrast (BVC) and dark voltage contrast (DVC) signals for a charged particle beam imaging system. The system can detect the defects by comparing patterns of the detected VC signals and the predicted VC signals.

Abstract: A method for testing TSV structures includes providing a wafer having a front side and a back side, the wafer further comprising a plurality of TSV structures formed therein; thinning the wafer from the back side of the wafer; forming a first under bump metallization layer on the back side of the wafer blanketly; providing a probing card to the front side of the wafer to test the TSV structures; and patterning the first UBM layer.

Abstract: A test device for measuring permeability of a barrier material. An exemplary device comprises a test card having a thin-film conductor-pattern formed thereon and an edge seal which seals the test card to the barrier material. Another exemplary embodiment is an electrical calcium test device comprising: a test card an impermeable spacer, an edge seal which seals the test card to the spacer and an edge seal which seals the spacer to the barrier material.

Abstract: A method for determining the oxygen concentration of a sample made of a semiconductor material includes a heat treatment step of the sample to form thermal donors, the measurement of the resistivity in an area of the sample, the determination of the thermal donor concentration from a relation expressing the charge carrier mobility according to an ionized dopant impurity concentration, by adding to the dopant impurity concentration four times the thermal donor concentration, and from the measured resistivity value. The method finally includes determining the oxygen concentration from the thermal donor concentration.

Abstract: A quality control process for determining the concentrations of boron and phosphorous in a UMG-Si feedstock batch is provided. A silicon test ingot is formed by the directional solidification of molten UMG-Si from a UMG-Si feedstock batch. The resistivity of the silicon test ingot is measured from top to bottom. Then, the resistivity profile of the silicon test ingot is mapped. From the resistivity profile of the silicon test ingot, the concentrations of boron and phosphorous of the UMG-Si silicon feedstock batch are calculated. Additionally, multiple test ingots may be grown simultaneously, with each test ingot corresponding to a UMG-Si feedstock batch, in a multi-crucible crystal grower.

Abstract: An integrated circuit chip includes a mainline function logic path communicatively connected to a first input/output (I/O) pin, a test logic path communicatively connected to the first I/O pin, a latch disposed between the communicative connection between the test logic function path and the first I/O pin, a second I/O pin communicatively connected to the latch, the second I/O pin operative to send a signal operative to change a state of the latch.

Abstract: A simulation method includes determining a relationship between stress time and a degradation rate of drain current on a basis of a table in which data of a lifetime of a transistor, or the degradation rate of the transistor, is written, and calculating an amount of change in drain current accordance with the degradation rate, using a table in which information indicating a change in the drain current, being dependent on voltage, is written, based on actually measured data of drain current of the transistor after degradation, drain current in an initial state of a particular transistor model, and the relationship between stress time and the degradation rate of drain current.

Abstract: A method is provided of processing substrate holder material for a substrate holder on which on a first side of said substrate holder a semiconductor substrate is to be placed for layered deposition of various semiconductor materials on the semiconductor substrate using induction heating. The method includes the operations of determining a first electrical resistivity at at least one measuring position on said substrate holder material, comparing said first electrical resistivity with a second reference electrical resistivity and adapting said substrate holder material in correspondence with said comparison. Also a substrate holder is provided which is processes by such a method.

Abstract: A testing apparatus is provided to test whether a distance between a first and a second portions of an object is eligible. The testing apparatus includes a worktable, a positioning mechanism to support the object, a pressing mechanism to secure the object, and an actuating mechanism. The actuating mechanism outputs signals to reflect the relative position of the correspond to-be-tested portion and the actuating mechanism, therefore a controlling device indicates whether the distance between the to-be-tested portion and the base plane is eligible or not according the outputting signals of the corresponding actuating mechanism.

Abstract: The present invention discloses a structure and a method for determining a defect in integrated circuit manufacturing process. Test keys are designed for the structure to be the interlaced arrays of grounded and floating conductive cylinders, and the microscopic image can be predicted to be an interlaced pattern of bright voltage contrast (BVC) and dark voltage contrast (DVC) signals for a charged particle beam imaging system. The system can detect the defects by comparing patterns of the detected VC signals and the predicted VC signals.

Abstract: An apparatus and method for testing electromigration in semiconductor devices includes providing an electromigration test structure, where the electromigration test structure includes a first metal line; a metal bridge operatively coupled to the first metal line; a second metal line operatively coupled to the metal bridge; a barrier layer surrounding the electromigration test structure; current contact pads; and voltage contact pads. The current contact pads are connected to a current source and the voltage contact pads are connected to a voltage source. The barrier layer is exposed to the elevated current density as current travels from the first metal line across the barrier layer through the metal bridge to the second metal line.

Abstract: The invention relates to a measuring arrangement, a semiconductor arrangement and a method for operating a reference source, wherein at least one semiconductor component and a voltage source are connected to a measuring unit and the measuring unit provides a measured value that is proportional to the number of defects.

Abstract: A process device is configured to meet a desired Safety Integrity Level (SIL). A device interface is configured to couple to the process device and provide an output related to operation of a component of the process device. A component monitor monitors operation of the component and identifies a safety event of the component. A safety response module responds to a safety event of the component in accordance with a safety response.

Abstract: A device for measuring the resistivity ?c of an interface between a semiconductor and a metal, including at least: one dielectric layer, at least one semiconductor-based element of a substantially rectangular shape, which is arranged on the dielectric layer, having a lengthwise L and widthwise W face in contact with the dielectric layer and having a thickness t, and at least two interface portions containing the metal or an alloy of said semiconductor and said metal, wherein each of two opposing faces of the semiconductor element, having a surface equal to t×W and being perpendicular to the face in contact with the dielectric layer, being completely covered by one of the interface portions.

Abstract: The present invention is a method for evaluating a silicon wafer by measuring, after fabricating a MOS capacitor by forming an insulator film and one or more electrodes sequentially on a silicon wafer, a dielectric breakdown characteristic of the insulator film by applying an electric field from the electrodes thus formed to the insulator film, the method in which the silicon wafer is evaluated at least by setting an area occupied by all the electrodes thus formed to 5% or more of an area of a front surface of the silicon wafer when the one or more electrodes are formed. This provides an evaluation method that can detect a defect by a simple method such as the TDDB method with the same high degree of precision as that of the DSOD method.

Abstract: Probes are electrically connected to a surface of a tunnel junction film stack comprising a free layer, a tunnel barrier, and a pinned layer. Resistances are determined for a variety of probe spacings and for a number of magnetizations of one of the layers of the stack. The probe spacings are a distance from a length scale, which is related to the Resistance-Area (RA) product of the tunnel junction film stack. Spacings from as small as possible to about 40 times the length scale are used. Beneficially, the smallest spacing between probes used during a resistance measurement is under 100 microns. A measured in-plane MagnetoResistance (MR) curve is determined from the “high” and “low” resistances that occur at the two magnetizations of this layer. The RA product, resistances per square of the free and pinned layers, and perpendicular MR are determined through curve fitting.

Abstract: A method of characterizing semiconductor device includes providing a silicon-on-insulator (SOI) substrate with at least a body-tied (BT) SOI device and a BT dummy device for measurement, respectively measuring tunneling currents (Igb) and scattering parameters (S-parameters) of the BT SOI device and the BT dummy device, subtracting Igb of BT dummy device from that of the BT SOI device to obtain Igb of a floating body (FB) SOI device, filtering characteristics of the BT dummy device out to extract S-parameters of the FB SOI device, and analyzing the S-parameters of the FB SOI device to obtain gate-related capacitances of the FB SOI device.

Abstract: Probes are electrically connected to a surface of a tunnel junction film stack comprising a free layer, a tunnel barrier, and a pinned layer. Resistances are determined for a variety of probe spacings and for a number of magnetizations of one of the layers of the stack. The probe spacings are a distance from a length scale, which is related to the Resistance-Area (RA) product of the tunnel junction film stack. Spacings from as small as possible to about 40 times the length scale are used. Beneficially, the smallest spacing between probes used during a resistance measurement is under 100 microns. A measured in-plane MagnetoResistance (MR) curve is determined from the “high” and “low” resistances that occur at the two magnetizations of this layer. The RA product, resistances per square of the free and pinned layers, and perpendicular MR are determined through curve fitting.

Abstract: A diagnostic method of and computer system for root-cause analysis of performance variations of FETs in integrated circuits and a method and computer system for monitoring a field effect transistor manufacturing process. The diagnostic method includes measuring source currents in the linear and saturated regions of two FETs, calculating ratios of the source currents in the linear and saturated regions for the and two FETs and comparing the ratios of the two FETs to determine a probable root cause for a performance variation between the two FETs. One of the FETs has a known good performance.

Abstract: One exemplary embodiment is a method for detecting existence of an undesirable particle between a planar lithographic object, such as a semiconductor wafer or a lithographic mask, and a chuck during semiconductor fabrication. The exemplary method in this embodiment includes placing the planar lithographic object, such as the semiconductor wafer, over the chuck. The method further includes measuring a change in at least one electrical characteristic formed by and between the chuck and the planar lithographic object, such as measuring a change in capacitance between the chuck and semiconductor wafer, caused by the undesirable particle.

Abstract: A test structure for testing electrical properties of a material comprises a first loop and a second loop, which are connected to form a closed test loop. A signal generator, for generating a test signal, is coupled to the first loop and the second loop. A signal propagation switching logic is coupled to the first loop and to the second loop for alternatingly flipping the test signal between the first and second loops, such that the test signal moves uninterrupted through the closed test loop. A probe logic detects any degradation of the test signal as the test signal travels along the closed test loop.

Abstract: A semiconductor chip includes a line structure arranged along a peripheral region of the semiconductor chip region in order to inspect a crack, a first pad and second pad arranged on different end portions of the line structure, a second pad arranged on another end portion of the line structure, an inspection device activated during a crack test mode to electrically connect the first pad, the line structure and the second pad. The inspection device may include a first switching circuit connected between the first pad and the line structure, the first switching circuit being deactivated during a normal operation mode and being activated a crack test mode; and a second switching circuit connected between the second pad and the line structure, the second switching circuit being deactivated during the normal operation mode and being activated during the crack test mode.

Abstract: An evaluation board, on which is mounted a chip to be evaluated is provided. Particularly, the evaluation board includes a monitoring window for monitoring a power supply part, a ground part, and a surface of the chip, a first signal input part for inputting signals to the chip, and a second signal input part for inputting signals to the chip, wherein the second signal input part is placed as to sandwich said monitoring window between itself and the first signal input part.

Abstract: A quality control process for determining the concentrations of boron and phosphorous in a UMG-Si feedstock batch is provided. A silicon test ingot is formed by the directional solidification of molten UMG-Si from a UMG-Si feedstock batch. The resistivity of the silicon test ingot is measured from top to bottom. Then, the resistivity profile of the silicon test ingot is mapped. From the resistivity profile of the silicon test ingot, the concentrations of boron and phosphorous of the UMG-Si silicon feedstock batch are calculated. Additionally, multiple test ingots may be grown simultaneously, with each test ingot corresponding to a UMG-Si feedstock batch, in a multi-crucible crystal grower.

Abstract: The resistance measuring device of the present invention includes switch transistors and switch conductive lines disposed between the bonding pads on a first substrate and between the bumps on a second substrate, such that the bonding pads and the bumps are conducted when the transistors are turned on, and the bonding resistance between at least one of the bonding pads and its corresponding bump can be directly measured.

Abstract: The present invention is directed to a number of improvements in methods for reliability simulations in aged circuits whose operation has been degraded through hot-carrier or other effects. A plurality of different circuit stress times can be simulated within a single run. Different aging criteria may be used for different circuit blocks, circuit block types, devices, device models and device types. The user may specify the degradation of selected circuit blocks, circuit block types, devices, device models and device types independently of the simulation. Device degradation can be characterized in tables. Continuous degradation levels can be quantized. Techniques are also described for representing the aged device in the netlist as the fresh device augmented with a plurality of independent current sources connected between its terminals to mimic the effects of aging in the device. The use of device model cards with age parameters is also described.

Abstract: A contact resistance test structure, a method for fabricating the contact resistance test structure and a method for measuring a contact resistance while using the contact resistance test structure are all predicated upon two parallel conductor lines (or multiples thereof) that are contacted by one perpendicular conductor line absent a via interposed there between. The test structure and related methods are applicable within the context of three-dimensional integrated circuits.