Abstract: The present disclosure relates to a metal comb structure including a first comb which includes a first set of metal fingers each of the metal fingers being connected at one end thereof by a connecting member from which the metal fingers extend. The metal comb structure also includes a second comb which includes a first set of metal fingers inter-digitated with the metal fingers of the first comb, a first set of vias associated with the metal fingers of the second comb and a connecting member connected to the vias thereby connecting the metal fingers of the second comb. The vias extend from the metal fingers of the second comb such that the connecting member of the second comb is located outside a plane defined by the metal fingers of the first and second combs.

Abstract: A method of monitoring and testing electro-migration and time dependent dielectric breakdown includes forming an addressable wiring test array, which includes a plurality or horizontally disposed metal wiring and a plurality of segmented, vertically disposed probing wiring, performing a single row continuity/resistance check to determine which row of said metal wiring is open, performing a full serpentine continuity/resistance check, and determining a position of short defects.

Abstract: Built-in electrical test structures are measured for lead-to-lead shorting during the fabrication of MR elements on a wafer. The test structures are fabricated in the same fashion as the MR elements, however, the active sensor region or track width is omitted from the test structures. Thus, the left and right leads for each test structure are electrically isolated from each other in their “track width” region. If there is lead-to-lead shorting on a test structure, then the left and right leads are electrically connected in the track width region. A simple resistance measurement between the left and right leads determines the extent of any lead shorting by giving a quantitative resistance value.

Abstract: In a test structure for determining dielectric breakdown events of a metallization system of semiconductor devices, a built-in compliance functionality may allow reliable switching off of the test voltage prior to causing high leakage currents, which may conventionally result in significant damage. Consequently, further failure analysis may be possible after the occurrence of a dielectric breakdown event.

Abstract: A measurement system for taking a reading in a test zone on a surface of a substrate. A chamber forms an environment, a surface treatment station dispenses a stabilizing chemical in the test zone, a charge deposition station deposits a charge in the test zone, and a QV measurement station takes a QV based measurement in the test zone. Where the surface treatment station, the charge deposition station, and the QV measurement station all interact with the substrate within the chamber. In this manner, reliable QV measurements are taken on the substrate by controlling charge spreading with the stabilizing chemical. QV measurement stability is also improved by reducing the influence of the time trending on substrates with reactive dielectrics, such as on silicon oxynitride and high-k surfaces.

Abstract: A pair of conductive rubber electrodes including measurement surfaces opposite to a surface of a dielectric layer of an electrostatic chuck as an objective of measurement, in which the measurement surfaces are arranged at an interval individually on the same plane, are provided. A direct-current power supply and an ammeter are connected to the pair of conductive rubber electrodes. The conductive rubber electrodes have resistance values equal to each other, and have a shape in which the measurement surfaces have areas equal to each other, in which volume resistivities are 1×105 ?·cm or less, and hardness is within a range of 60 to 80 Hs in JIS-A hardness. An interval between the conductive rubber electrodes is six times or more a thickness of the dielectric layer of the electrostatic chuck as the objective of the measurement.

Abstract: A sensor device for insertion into a water channel in a washing machine is provided with two electrodes as sensors on a sensor carrier. These electrodes are in direct contact with the water through apertures. The electrodes are connected to a transformer on the sensor carrier directly and without any further components or couplings being required. The other side of the transformer is connected to an activating and evaluating means, in particular to a microprocessor positioned on the same carrier.

Abstract: Nanoscale impedance microscopy and related methods, circuit and/or apparatus capable of quantitatively measuring magnitude and phase of alternating current flow.

Abstract: A resistance wiring and a judgement circuit for judging a potential in a middle of a path of the resistance wiring are provided on a periphery of a semiconductor chip. One end of the resistance wiring is connected to a power supply and the other end thereof is grounded. Connection points of the resistance wiring to the power supply and the ground are disposed at a corner on the periphery of the semiconductor chip, while a connection point of the resistance wiring to the judgement circuit is disposed at a corner diagonal to the corner on the periphery. When breakages such as chipping and peeling of an interlayer insulating film is caused on the periphery, resistance of the resistance wiring changes.

Abstract: A structure and method for monitoring extrusion failures. The structure includes: a test wire having first and second ends; first and second vias contacting first and second ends of the test wire; a first monitor structure electrically isolated from the test wire and surrounding a periphery of the test wire; and a second monitor structure over the test wire, the second monitor structure electrically isolated from the test wire, the second monitor structure extending over at least the first end of the test wire.

Abstract: A method and apparatus for manufacturing photovoltaic cells is provided. In one embodiment, a method for evaluating transparent conductive oxide (TCO) delamination from a substrate is provided. The method comprises providing a glass substrate with a TCO film laminated on a first surface of the glass substrate, depositing a metal layer on a second surface of the glass substrate opposite the first surface, heating the substrate while applying a bias to the substrate, cooling the substrate in a humidity controlled environment for a fixed time period, dividing the TCO film into a plurality of electrically insulated channels using a laser scribing process, and measuring a resistance of each of the plurality of electrically insulated channels.

Abstract: A method for detection and analysis of impurity content of refined metallurgical silicon includes: (1) select the measuring points on the crystal rods or crystal ingots along the crystallization direction, measuring the resistivity at each measuring point and acquire the measured value of resistivity according to the distribution of crystallized fraction; (2) get the estimated value of the content of boron and phosphorus at each measuring point and calculate the estimated net redundant carrier concentration and the measured value of resistivity; (3) compare the estimated value of net redundant carrier concentration with that of the measured value, and adjust the estimated value of impurity content in the silicon material to get the new estimated net redundant carrier concentration, and use regression analysis to determine the impurity content distribution of boron and phosphorus; (4) get the average impurity content of boron and phosphorus in the silicon material according to the distribution status of impuri

Abstract: An apparatus for measuring a structural characteristic between a polysilicon shape and a silicon area. The apparatus for measuring a structural characteristic between a polysilicon shape and a silicon area comprises the silicon area, and a plurality of polysilicon shapes each having a unique orientation relative to the silicon area wherein each of the polysilicon shapes is formed having an angle less than or equal to a critical angle. The critical angle is an angle at or below which a sidewall spacer no longer is formed on a polysilicon shape, thereby causing the polysilicon shape to short circuit to an underlying portion of the silicon area by way of a silicide bridge.

Abstract: A method and system for identifying a defect or contamination on the surface of a semiconductor or in a semiconductor. The method and system involves providing a semiconductor with a surface, such as a semiconductor wafer, providing a non-vibrating contact potential difference sensor, providing a source of illumination with controllable intensity or distribution of wavelengths, using the illumination source to provide controlled illumination of the surface of the wafer under or near the non-vibrating contact potential sensor probe tip, using the non-vibrating contact potential difference sensor to scan the wafer surface during controlled illumination, generating data representative of changes in contact potential difference across the wafer surface, and processing that data to identify a pattern characteristic of a defect or contamination.

Abstract: A composite membrane includes a mixed ionic and electronic conducting membrane; and an porous catalyst layer on at least one surface of the membrane, said electrocatalytic layer comprised of an oxygen ion conductor and electronic conductor.

Abstract: A method for measuring a property of interconnections is provided. The method includes the following steps. A plurality of interconnection test patterns are provided. A pad to which the plurality of interconnection test patterns are parallelly connected is formed. At least one resistor is formed between at least one of the plurality of interconnection test patterns and the pad. The property of the plurality of interconnection test patterns is measured by applying a current, a voltage and/or a mechanical stress to the pad.

Abstract: There is provided a method for simulating ion implantation which includes the steps of calculating an integral value ?a/c by integrating concentration distribution of Ge in a test silicon substrate from the thickness of an amorphous layer to infinite, acquiring a form parameter of the Ge concentration distribution in a product silicon substrate by referring to a database, creating a distribution function which approximates the Ge concentration distribution by using the form parameter, and obtaining such a depth that an integral value obtained by integrating the distribution function from the depth to infinite can be equal to the integral value ?a/c, and then specifying that the depth is the thickness of an amorphous layer.

Abstract: The present invention is directed to a number of improvements in methods for hot-carrier device degradation modeling and extraction. Several improvements are presented for the improvement of building device degradation models, including allowing the user to select a device parameter used to build the device degradation model independent of the device parameter selected. The user can also select the functional relation between stress time and degradation level. To further improve accuracy, multiple acceleration parameters can be used to account for different regions of the degradation process. Analytical functions may be used to represent aged device model parameters, either directly or by fitting measured device parameters versus device age values, allowing devices with different age values to share the same device model. The concept of binning is extended to include device degradation. In addition to a binning based on device width and length, age is added.

Abstract: Contact holes (openings) (17) are created in the upper electrode (14) and the dielectric film (15) of a polysilicon-insulator-polysilicon (PIP) capacitive element to form a plurality of evaluation patterns wherein the lower electrode (13) and upper layer wiring lines (20) for measurement are electrically connected through contacts (16). At least four evaluation patterns are created by a combination of two or more values of a distance L with different values of a width W. Since it can be assumed that a difference in the resistance value between the respective evaluation patterns is only due to the effect of a change in a rectangular region (W*L) between the contact holes (openings) (17), it is possible to easily calculate the sheet resistance of the high-resistance portion from a change in the resistance value of each of the measurement patterns.

Abstract: A method of electrically characterizing a magnetic tunnel junction film stack having three metal layers separated by two dielectric layers comprises three steps. In a first step, four or more probes are electrically coupled to a surface of the magnetic tunnel junction film stack. In a second step, electrical resistance is determined with the four or more probes for each of a plurality of spacings between the probes. Finally, in a third step, the plurality of resistance measurements are fitted with one or more equations that relate electrical resistance to probe spacing.

Abstract: Once accepting an interrupt, the control is such as to not accept any interrupt including that highest priority within the group to which the interrupt about to be processed belongs by referring to the interrupt management table. Then the vector number for the highest priority in the group from among the received interrupts is selected. Then the processing of a handler for the selected vector number is executed. The priority of the executed interrupt processing is reset to the lowest priority in the group.

Abstract: The present invention relates to a method for evaluating the SOI wafer in a method for evaluating an SOI wafer in which a sheet resistance of a buried diffusion layer of an SOI wafer that has at least an SOI layer on an insulator layer and has a buried diffusion layer whose impurity concentration is higher than other region of the SOI layer in an interface area with the insulator layer of the SOI layer is evaluated, the method including the steps of measuring a sheet resistance of the whole SOI layer or the whole SOI wafer, and estimating the sheet resistance of the buried diffusion layer by assuming respective layers that compose the SOI wafer to be resistors connected in parallel and converting the measured result of the sheet resistance measurement. As a result of this, there is provided a method for evaluating the SOI wafer that can directly measure the SOI wafer itself to be the product to thereby evaluate the sheet resistance of the buried diffusion layer thereof, without fabricating a monitor wafer.

Abstract: Measurements of parameters of MOS transistors, also known as MOSFETs, such as threshold potentials, require accurate estimates of source and drain series resistance. In cases where connections to the MOSFET include significant external series resistance, as occurs in probing transistors that are partially fabricated or deprocessed, accurate estimates of external resistances are also required. This invention comprises a method for estimating series resistances of MOSFETs, including resistances associated with connections to the MOSFET, such as probe contacts. This method is applicable to any MOSFET which can be accessed on source, drain, gate and substrate terminals, and does not require other test structures or special connections, such as Kelvin connections.

Abstract: A diagnostic method of and computer system for root-cause analysis of performance variations of FETs in integrated circuits and a method and computer system for monitoring a field effect transistor manufacturing process. The diagnostic method includes measuring source currents in the linear and saturated regions of two FETs, calculating ratios of the source currents in the linear and saturated regions for the and two FETs and comparing the ratios of the two FETs to determine a probable root cause for a performance variation between the two FETs. One of the FETs has a known good performance.

Abstract: A system (28) includes a microelectronic device (10) including first transistors (22) and second transistors (24), a power supply (40) electrically connected to the first and second transistors to provide power to the first and second transistors such that current flows through the first and second transistors, a switch (32) in operable communication with the second transistors, the switch allowing current to flow from the power supply through the second transistors when in a first mode of operation and preventing current from flowing from the power supply through the second transistors when in a second mode of operation, control circuitry in operable communication with the switch, and current sensing circuitry coupled to the first transistors to detect a test amount of current flowing through at least one of the first transistors when the switch is in the first mode of operation.

Abstract: A method for determining consistency of a permeability of a ferromagnetic material in integrated circuits in which a test strip of the subject ferromagnetic material is included for testing with an impedance measurement instrument, such as an inductance-capacitance-resistance (LCR) meter, with which the resistance of the strip of ferromagnetic material over a range of measurement signal frequencies is determined based upon the measured impedance values. The measured impedance values, measurement signal frequencies and selected permeability values are then used in numerical simulations to produce multiple resistance versus frequency curves each of which corresponds to one of the selected permeability values.

Abstract: An integrated circuit product includes: 1) a package, 2) a semiconductor die mounted within the package, 3) a first terminal and a second terminal for connecting the integrated circuit product to an external circuit, 4) one or more bond wires for transferring a current received at the first terminal to the second terminal; and 5) a circuit included in the semiconductor die that measures a voltage difference attributable to the resistance of the bond wires to measure the magnitude of the current passing through the first terminal.

Abstract: This invention discloses a method for detection and analysis of impurity content of refined metallurgical silicon, comprising: (1) select the measuring points on the crystal rods or crystal ingots along the crystallization direction, measuring the resistivity at each measuring point and acquire the measured value of resistivity according to the distribution of crystallized fraction; (2) get the estimated value of the content of boron and phosphorus at each measuring point and calculate the estimated net redundant carrier concentration and the measured value of resistivity; (3) compare the estimated value of net redundant carrier concentration with that of the measured value, and adjust the estimated value of impurity content in the silicon material to get the new estimated net redundant carrier concentration, and use regression analysis to determine the impurity content distribution of boron and phosphorus; (4) get the average impurity content of boron and phosphorus in the silicon material according to the d

Abstract: An apparatus for predicting the reliability of an electronic system is provided. The apparatus includes at least one component, a stress sensor operable to measure stress of the at least one component, a resistance sensor operable to measure an electrical resistance of the at least one component, and an electronic control system coupled to the stress sensor and resistance sensor operable to predict the reliability of the electronic system using the stress and electrical resistance of the at least one component.

Abstract: A system and method are disclosed for determining the effective channel width (Weff) and the effective channel length (Leff) of metal oxide semiconductor devices. One advantageous embodiment of the method provides a plurality of metal oxide semiconductor field effect transistor capacitors in which each capacitor has a same value of drawn channel length but a different value of drawn channel width. A value of Fowler-Nordheim tunneling current is measured from each capacitor. Channel width offset is the difference between the drawn channel width and the effective channel width. A value of channel width offset is obtained from the measured values of the Fowler-Nordheim tunneling currents and used to determine the value of effective channel width. A similar method is used to determine the value of the effective channel length.

Abstract: Methods, systems and program products are disclosed for performing a stress test of a line in an integrated circuit (IC) chip. One embodiment of the method includes: applying a constant current Is to the line; and stress testing the line while applying the constant current Is such that the constant current Is is not altered by a resistance change due to an onset of electromigration.

Abstract: An integrated circuit has an analog output circuit for outputting an analog signal and a leadless terminal for connecting an output line of the analog output circuit to a circuit board by soldering, and measures and transfers an analog output voltage of the leadless terminal in a state in which it is mounted on the circuit board. A measuring unit has a switching unit for connecting the analog output circuit to the measuring unit upon failure diagnosis, and an AD converter for measuring the analog output voltage of the leadless terminal in a failure diagnosis state obtained by the switching unit; and causes the analog output voltage of the leadless terminal to be determined whether it is a normal voltage or an abnormal voltage by transferring the voltage measured by the AD converter to a determination unit through serial transfer.

Abstract: Measurements of parameters of MOS transistors, also known as MOSFETs, such as threshold potentials, require accurate estimates of source and drain series resistance. In cases where connections to the MOSFET include significant external series resistance, as occurs in probing transistors that are partially fabricated or deprocessed, accurate estimates of external resistances are also required. This invention comprises a method for estimating series resistances of MOSFETs, including resistances associated with connections to the MOSFET, such as probe contacts. This method is applicable to any MOSFET which can be accessed on source, drain, gate and substrate terminals, and does not require other test structures or special connections, such as Kelvin connections.

Abstract: A method for measuring work function includes the steps of: (a) providing a field emission electron source having a carbon nanotube tip as a cathode electrode and a spaced anode electrode, having a predetermined spaced distance therebetween; (b) applying a voltage between the cathode electrode and the anode electrode and measuring a first current-voltage curve of the field emission electron source in a vacuum environment; (c) forming a layer of field emission material at least on the surface of the carbon nanotube tip; (d) measuring a second current-voltage curve of the now-treated field emission electron source in the same conditions as that in the step (b); (e) achieving two Fowler-Nordheim curves calculated from the two current-voltage curves according to the Fowler-Nordheim equation; and (f) comparing the two Fowler-Nordheim curves and calculating the work function of the field emission material therefrom.

Abstract: According to an aspect of an embodiment, a high-sensitive resistance measuring device of solder bumps comprises a resistance variation detection unit which detects a differential voltage (?V=V1?V2), which is obtained by subtracting a second voltage (V2) generated in a reference bump connection unit by a constant current (I) from a second constant current source from a first voltage (V1) generated in a monitored bump connection unit by the constant current I from a first constant current source, as a resistance variation voltage representing a resistance variation (?R) of the monitored bump connection unit.

Abstract: A method for measuring a property of interconnections is provided. The method includes the following steps. A plurality of interconnection test patterns are provided. A pad to which the plurality of interconnection test patterns are parallelly connected is formed. At least one resistor is formed between at least one of the plurality of interconnection test patterns and the pad. The property of the plurality of interconnection test patterns is measured by applying a current, a voltage and/or a mechanical stress to the pad.

Abstract: The present invention relates to a method of fabricating a vertical probe head, whereas the vertical probe head is formed by the combination of at least a probe, a bottom guide plate and a top guide plate having at least a hole matching the probe. The probe is fabricated by a LIGA-like process combining with the processes of photolithography, etching and electroforming, and so on, so that the probe is equipped with comparatively better precision, strength and reliability and yet can be custom-made for satisfying various demands. In addition, both the top and bottom guide plates are made by a means of non-mechanical machining, which respectively is fabricated by processing a substrate using means of photolithography, etching and mask so as to fabricate holes for matching with the aforesaid probe.

Abstract: The accuracy of effective channel width extraction in drain current method is improved. There are prepared a transistor with a wide channel width serving as a reference, and a transistor with a narrow channel width that becomes a candidate for extraction (step ST1.1). From the characteristic curve of a plane formed by mask channel width and source-drain conductance, there is extracted a virtual point at which the change of source-drain conductance is estimated to be approximately zero even if the gate overdrive is finely changed. Then, the value of function F is calculated which is defined by the difference between the change of the conductance at the coordinate of the virtual point and the product obtained by multiplying the conductance per unit width by the change of the mask channel width (step ST1.6). From a shift amount (?) which minimizes the standard deviation of the function F to be obtained (step ST1.

Abstract: A device for measuring the resistivity ?c of an interface between a semiconductor and a metal, comprising at least: one dielectric layer, at least one semiconductor-based element of a substantially rectangular shape, which is arranged on the dielectric layer, having a lengthwise L and widthwise W face in contact with the dielectric layer and having a thickness t, at least two interface portions containing the metal or an alloy of said semiconductor and said metal, each of the two opposing faces of the semiconductor element, having a surface equal to t×W and being perpendicular to the face in contact with the dielectric layer, being completely covered by one of the interface portions.

Abstract: A method for determining film continuity and growth modes in thin dielectric films includes: depositing a material on the substrate using a first value of a growth metric; depositing an amount of charge on a surface of the material; repetitively measuring a surface voltage of the material until an onset of tunneling to provide a Vtunnel (or Etunnel) value; repeating the above steps for different values of the growth metric; and comparing the Vtunnel (or Etunnel) values for different values of the growth metric to provide a measure of the continuity of the material on the substrate. The growth modes of the material can be determined by comparing the first derivative of the Vtunnel or Etunnel per growth metric curve versus the growth metric, and examining the linearity of the results of the comparison. The growth metric parameters may include thickness, time, precursor cycles, or temperature.

Abstract: Contact holes (openings) (17) are created in the upper electrode (14) and the dielectric film (15) of a polysilicon-insulator-polysilicon (PIP) capacitive element to form a plurality of evaluation patterns wherein the lower electrode (13) and upper layer wiring lines (20) for measurement are electrically connected through contacts (16). At least four evaluation patterns are created by a combination of two or more values of a distance L with different values of a width W. Since it can be assumed that a difference in the resistance value between the respective evaluation patterns is only due to the effect of a change in a rectangular region (W*L) between the contact holes (openings) (17), it is possible to easily calculate the sheet resistance of the high-resistance portion from a change in the resistance value of each of the measurement patterns.

Abstract: A method is disclosed for measuring alignment of polysilicon shapes relative to a silicon area wherein the presence of an electrical coupling is used to determine the presence of bias or misalignment. Bridging vertices on the polysilicon shapes are formed. Bridging vertices over the silicon area create low resistance connections between those bridging vertices and the silicon area; other bridging vertices over ROX (recessed oxide) areas do not create low resistance connections between those other bridging vertices and the silicon area. Determining which bridging vertices have low resistance connections to the silicon area and how many bridging vertices have low resistance connections to the silicon area are used to determine the bias and misalignment of the polysilicon shapes relative to the silicon area.

Abstract: Various embodiments of the present invention describe circuits for and methods of detecting a defect in a component formed in a substrate of an integrated circuit. According to one embodiment, a circuit comprises a plurality of components formed in a substrate and coupled in series by a plurality of signal paths extending from a first end to a second end. An input signal coupled to the first end of the first signal path is detected a signal detector coupled to a second end of the first signal path to determine whether there is a defect in a component formed in the substrate. Switching networks at the inputs and the outputs of the plurality signal paths enable determining a particular signal path that had a defect. Alternate embodiments describe circuits for determining the location of a defective component in a signal path. Various methods of detecting defective components are also described.

Abstract: A device and method for electrical contacting for the testing of semiconductor devices is disclosed. One embodiment provides for the electrical connection of the semiconductor device with a test system, including devices for the contacting of connection pins or contact pads of the semiconductor device to be tested. The devices for the contacting of the connection pins or the contact pads of the semiconductor device to be tested include contact holders with at least one exchangeable contact tip.

Abstract: A semiconductor substrate or wafer inspection device for detecting defects on wafer surfaces includes an air-cushion stage which can be displaced in two directions (X,Y) that are perpendicular to one another. Several air nozzles are provided for this purpose. At least one valve is connected to at least one electric control unit, the valve being configured in such a way that a normal pressure prevails in the air nozzles when the electric control unit delivers a corresponding signal.

Abstract: A method for testing a TMR element includes a step of measuring a plurality of resistances of the TMR element by feeding a plurality of sense currents with different current values each other through the TMR element, a step of calculating a ratio of change in resistance from the measured plurality of resistances of the TMR element, and a step of evaluating the TMR element using the calculated ratio of change in resistance.

Abstract: A micro Kelvin probe assembly and method of accomplishing a micro Kelvin measurement that determines the resistance or impedance of a device under test (DUT) that has two spaced contacts. An ammeter is used to flow current through the DUT, and a voltmeter is used to measure the voltage drop across the DUT. There is a printed circuit board (PCB) carrying two pairs of contacts, with a trace leading to each contact. Anisotropic conductive elastomer (ACE) material as an electrical interposer is placed in electrical contact with each of the PCB contacts. The DUT is placed on the ACE such that each DUT contact is directly opposite one pair of PCB contacts. The ammeter is connected to one trace leading to one contact of each pair of PCB contacts to flow current through the DUT, and the voltmeter is connected to the other trace leading to the other contact of each pair of PCB contacts, so that voltmeter can measure the voltage drop across the DUT without an effect caused by the interposer.

Abstract: A micro Kelvin probe assembly and method of accomplishing a micro Kelvin measurement that determines the resistance or impedance of a device under test (DUT) that has two spaced contacts. An ammeter is used to flow current through the DUT, and a voltmeter is used to measure the voltage drop across the DUT. There is a printed circuit board (PCB) carrying two pairs of contacts, with a trace leading to each contact. Anisotropic conductive elastomer (ACE) material as an electrical interposer is placed in electrical contact with each of the PCB contacts. The DUT is placed on the ACE such that each DUT contact is directly opposite one pair of PCB contacts. The ammeter is connected to one trace leading to one contact of each pair of PCB contacts to flow current through the DUT, and the voltmeter is connected to the other trace leading to the other contact of each pair of PCB contacts, so that voltmeter can measure the voltage drop across the DUT without an effect caused by the interposer.

Abstract: A method of determining the time to failure of parallel electro migration test structures is described. The method generally includes the steps of: measuring the resistance of the complete structure; calculating the resistance of the n individual parallel structures from the measured resistance; calculating the resistance of the complete structure after the failure of m individual parallel structures, for m=1 to n; and recording the time of failure for each m as the time when the resistance is approximately the value predicted for m fails.

Abstract: The present invention is directed to a contact resistance test structure and methods of using same. In one illustrative embodiment, the method includes forming a test structure comprised of two gate electrode structures, forming a plurality of conductive contacts to a doped region between the two gate electrode structures, forcing a current through the test structure and determining a resistance of at least one of the conductive contacts based upon, in part, the forced current.