Abstract: Disclosed herein are a methods for testing operability of a thermocouple device and operability of a safety valve solenoid and ECO fuse circuit all in a fuel gas control system for a gas fired appliance. Also disclose are apparatus for carrying out such methods, the apparatus comprising a test instrument, for applying selected millivolt DC currents to the safety valve solenoid and ECO fuse circuit and for measuring millivolt DC current output of the thermocouple device, and-an adaptor for connecting the test instrument to the safety valve solenoid and ECO fuse circuit of the fuel gas control system.

Abstract: The compare path bandwidth control for high performance automatic test systems provides a standard dual comparator mode with single ended transmission lines for low frequency applications with a capability of receiving a differential signal when using the dual comparators (40), (41) as an effective single comparator for high frequency applications.

Abstract: To remove ringing from pulse. A buffer amplifier (30) is inserted in series into a path through which a signal is transmitted. Ringing caused in the output of the buffer amplifier (30) is detected by an L side comparator (31) and an H side comparator (32). When ringing is detected, a current is supplied into the input of the buffer amplifier (30) through an L side current supply circuit (33) or an H side current supply circuit (34). By supplying a current from the L side and H side current supply circuits (33, 34), the overshooting portion due to ringing can be suppressed.

Abstract: A disk drive test device for performing a test (e.g., power only self test, tests which use a serial interface) on at least one disk drive at a time. The test device includes an electrical connector which is configured so as to be able to provide the necessary electrical interconnections for executing a test on disk drives having different types of drive interface connectors (i.e., the same electrical connector may be used with at least 2 different types of drive interface connectors). There is no need to use an in-line adapter to electrically interconnect a disk drive having a first drive interface connector or to electrically interconnect a disk drive having a second drive interface connector. There is also is no need to change out the electrical connector when performing a test on disk drives which use this different types of drive interface connectors.

Abstract: There are provided a timing calibration apparatus and a timing calibration method capable of carrying out the calibration of timing on an IC tester with high accuracy. There is provided a probe to be sequentially contacted with pins of an IC socket on which an IC under test is to be mounted, and a calibration pulse supplied to the IC socket from the IC tester is taken in the probe. The calibration pulse is compared with the reference timing, thereby to calibrate the timing on a driver included signal path. In the probe a calibration pulse is generated, which is sequentially supplied to the pins of the IC socket, thereby to calibrate the timing on a comparator included signal path in each of channels. There are provided in the probe an optical modulator for converting an electric signal into an optical signal and an optically driven type driver. An optical cable couples between a calibration controller provided in the IC tester and the probe.

Abstract: There are provided plural integrated circuits a to i in which a self-diagnostic result obtained from a self-diagnostic circuit 12 is outputted and controlled by select signals 1, 2, 3 supplied from the outside, and each the self-diagnostic result of the plural integrated circuits is respectively supplied to one monitor through a determination signal line every plural self-diagnostic results and control is performed by control signals 1, 2, 3 so that any one of the self-diagnostic results of the plural integrated circuits supplied to the one monitor is outputted.

Abstract: For speeding up the short-circuit and component test phase when testing electrical modules on a flying probe tester that includes contacting elements movable in all directions over a respective line networks of the electrical module, it is proposed that, at the beginning of the testing phase, such groups of contact points be contacted. Further, a respective line network-to-ground/potential connection for respective measurement threat is produced with respect to all line networks occurring on the electrical module under test.

Abstract: A method and apparatus for diagnosing short circuit conditions in a circuit protects circuit components from being damaged during a diagnostic operation. The apparatus includes a control processor, a control circuit coupled to the control processor, and an A/D converter coupled to the control processor and the control circuit. In operation the control processor disables operation of an A/D converter after completion of a conversion operation, enables operation of the control circuit after operation of the A/D converter has been disabled, enables operation of the A/D converter to obtain an analog signal from the control circuit after operation of the control circuit has been enabled, and disables operation of the control circuit after enabling operation of the A/D converter to obtain the analog signal. The A/D converter converts the analog signal into a digital signal and the control processor analyzes the digital signal to determine if a short circuit condition exits in the control circuit.

Abstract: A radio-frequency reception arrangement for a magnetic resonance apparatus has a number of independent antennas and pre-amplifiers. The number of pre-amplifiers is less than the number of independent antennas. A switching matrix is arranged between the pre-amplifiers and the antennas for selective, signal-dependent connection of the pre-amplifiers to the antennas.

Abstract: A system circuit constituting a semiconductor device (LSI) incorporates a test circuit for detecting a fault in the device. The test circuit comprises a plurality of flip-flop circuits. In this invention, a period adjusting flip-flop is added to the final stage of the test circuit. In accordance therewith, the test (SCAN operation) period can be easily adjusted.

Abstract: A method and system for testing an integrated circuit using a plurality of parameters is disclose. The plurality of parameters are from a plurality of parameter sources. The integrated circuit includes a plurality of pins. The method and system include a signal converter, a controller coupled with the signal converter and a plurality of relays coupled with the controller. The signal converter is capable of being coupled with a computer system and is for converting between analog and digital signals. The signal converter receives values for the plurality of parameters from the computer and converts the values for the plurality of parameters to an analog signal indicating the values for the plurality of parameters. The controller is for receiving the analog signal from the signal converter and for providing at least one signal based on the analog signal. The plurality of relays is coupled with the integrated circuit and with the controller.

Abstract: An inspection program having custom-designed inspection procedures set is stored for each control unit in an inspection program storage section on the control unit. The inspection program is transferred, by means of communications means, to a rewritable inspection program storage section provided in an inspection apparatus. The type of a control unit which is an object of inspection is identified by means of causing the inspection apparatus to run the inspection program. Appropriate input and loads are provided for the control unit, thus causing the control unit to perform inspection procedures.

Abstract: A semiconductor integrated circuit device provided with an IC chip so as to prevent its circuits from malfunction when the IC chip is cracked. To detect chip cracks, a resistor R01 is disposed at the outer periphery of the area which wants to detect the chip crack. If the chip is cracked and the resistance value of the resistor R01 is changed, the resistance change is detected, thereby controlling internal signals such as the power on reset signal and stopping the whole operation of the circuit device so as to prevent the circuits from malfunction. Thus, the system security can also be improved.

Abstract: In an IC testing apparatus which executes a function test and a DC test, a resistor having a high resistance is connected to the output side of a DC tester such that the connection of the resistor allows a function test to operate normally if the DC tester is left connected to the function tester, thus allowing the DC test to be interrupted into the execution of the function test to enable a concurrent execution of the function test and the DC test. As a result, the time required to change switches in the DC tester, for example, can be executed during the function test, thus preventing the time interval required to change the switches from increasing the time interval required for the test, thereby reducing the testing time interval.

Abstract: A system and method for locating a circuit defect, such as a short or an incipient open, in an electric circuit in a workpiece, such a Printed Circuit Board (PCB) or MultiChip Module (MCM). The circuit is connected to a device for sensitively measuring any resistance change. A thermal stimulus is applied to various subsets of the surface of the workpiece, the thermal stimulus being temporally modulated, and the resistance change measurement correlated with this modulation. By applying well-designed thermal stimulus subsets, resistance measurements may be logically combined which correspond to the plural thermal stimulus subsets. Further, the search region where the defect may be located may be iteratively refined. By measuring the time delay between the thermal stimulus and corresponding resistance change, the depth of a defect below the surface of the workpiece is further determined.

Abstract: A method for detecting cut data lines in an imaging array having a detector including an array of pixels for measuring radiation, and a plurality of data line contacts is provided. The method includes the steps of initializing pixels of the imaging array which includes a plurality of data lines including at least one uncut data line and at least one cut data line, wherein each cut data line is electrically connected to at least one of the plurality of data line contacts and at least one uncommitted contact. The method further includes determining a signal level for the uncut data lines, measuring a signal level of each data line in the plurality of data lines, and determining a number of cut data lines and a number of uncut data lines by using the signal levels received from each data line in the plurality of data.

Abstract: A system for testing a hardware unit containing sensitive information, while inhibiting access to that information, includes a secure program in an Automated Test Station and an interface circuit. The test station has a programmed processor, as well as generating equipment which generates pseudo test signals and measuring devices which measure the response of the unit to actual test signals. Within the processor of the test station there is a test program which does not indicate the sensitive information and a run-time program that interprets the test-program to generate encoded commands for carrying out the test. The interface circuit receives the encoded commands and the pseudo test signals from the test station, decodes the encoded commands and generates the actual test signals. These actual test signals are routed to the unit under test by the interface circuit.

Abstract: The present invention provides a method and device for reduced-pin integrated circuit I/O testing. In this regard, the present invention provides for the testing of an integrated circuit or chip in a manner which is independent of the number of test pins present on the testing device. The method and device of the present invention are realized through an integrated circuit having two test ports: a scannable I/O test port and a Forcing-Measuring test port, and a plurality of switches. The scannable I/O test port is employed for the input and output of, among other things, scannable shift-register latch data which affects the states of the plurality of switches in the integrated circuit. The Forcing-Measuring test port is employed for, among other things, forcing or measuring voltages and currents associated with the I/O circuits under test through the switches to the circuits under test.

Abstract: A method and circuitry for an undisturbed scannable state element. A scannable state element, implemented in a scan chain for testing an integrated circuit, includes both a dual-ported flop circuit and a shadow flop circuit. The dual-ported flop circuit includes both a master cell and a slave cell, while the shadow flop includes only a master cell, and utilizes the slave cell of the dual-ported flop. During scan shifting, scan data is shifted through the shadow flop and the slave cell of the dual-ported flop, bypassing the master cell. Since the data output of the dual-ported flop originates in the master cell, the state of the data in the dual-ported flop is not disturbed by the scan. Scan data may also be latched into the master cell from the scan chain or from the master cell into the scan chain through a scan data output in the slave cell.

Abstract: A method and software apparatus for implementing a dynamically modifiable test flow for integrated circuit devices that adapts to the characteristics of each processed device lot. A modified set of tests sufficient to ensure proper device function for a particular lot is performed, reducing test costs and increasing test capacity. The method and system of the invention periodically samples a predetermined sample number of devices using a full set of tests including a set of skippable tests. Depending upon the performance characteristics of the sample device group on the skippable tests, a number of skippable tests are skipped during a modified test flow. After a next set of devices is tested using the modified test flow, the full set of tests is again performed on another sample group, and the size and makeup of the modified test flow is adjusted according to the new results.

Abstract: The voltage measuring apparatus of the present invention comprises: a capacitor configured of a plurality of capacitor elements and divided at a connection point into two sections of the same capacitance; a first switching device for connecting a voltage source to be measured to both terminals of the capacitor; a differential amplifier; a second switching device for connecting both terminals of the capacitor to inputs of the differential amplifier; and a third switch for connecting the connection point in the capacitor to signal reference potential of the differential amplifier in time synchronization with the second switching device.

Abstract: Dummy cell test circuit for measuring delay times in embedded, said embedded circuits being connected to access circuits equipped with input access pads and output access pads, between which is comprised an electrical main path, said test circuit comprising a test input pad and a test output pad, between which is comprised an electrical dummy test path. According to the present invention the test input pad correspond to the access input pad (IN1′ IN1″) of the embedded circuit (2).

Abstract: An arbitrary waveform generator (AWG) generates an output signal that linearly ramps between discrete levels to approximate a smoothly varying waveform. The AWG includes a digital-to-analog converter (DAC) formed by a set of N ramp generators, with each ramp generator producing output currents that ramp at adjustable rates between discrete levels in response to a change in state of an input waveform data bit. The output currents of all N ramp generators of the DAC, which have separately weighted magnitude levels, are summed and converted to a proportional voltage to produce the AWG's output signal.

Abstract: To remove ringing from pulse. A buffer amplifier (30) is inserted in series into a path through which a signal is transmitted. Ringing caused in the output of the buffer amplifier (30) is detected by an L side comparator (31) and an H side comparator (32). When ringing is detected, a current is supplied into the input of the buffer amplifier (30) through an L side current supply circuit (33) or an H side current supply circuit (34). By supplying a current from the L side and H side current supply circuits (33, 34), the overshooting portion due to ringing can be suppressed.

Abstract: A disk drive test device for performing a test (e.g., power only self test, tests which use a serial interface) on at least one disk drive at a time. The test device includes an electrical connector which is configured so as to be able to provide the necessary electrical interconnections for executing a test on disk drives having different types of drive interface connectors (i.e., the same electrical connector may be used with at least 2 different types of drive interface connectors). There is no need to use an in-line adapter to electrically interconnect a disk drive having a first drive interface connector or to electrically interconnect a disk drive having a second drive interface connector. There is also is no need to change out the electrical connector when performing a test on disk drives which use this different types of drive interface connectors.

Abstract: A system and method for locating a circuit defect, such as a short or an incipient open, in an electric circuit in a workpiece, such a Printed Circuit Board (PCB) or MultiChip Module (MCM). The circuit is connected to a device for sensitively measuring any resistance change. A thermal stimulus is applied to various subsets of the surface of the workpiece, the thermal stimulus being temporally modulated, and the resistance change measurement correlated with this modulation. By applying well-designed thermal stimulus subsets, resistance measurements may be logically combined which correspond to the plural thermal stimulus subsets. Further, the search region where the defect may be located may be iteratively refined. By measuring the time delay between the thermal stimulus and corresponding resistance change, the depth of a defect below the surface of the workpiece is further determined.

Abstract: A method of manufacturing items in parallel. Selected samples of items to be manufactured are subjected to additional steps in a manufacturing process. If such sample items meet the requisite quality control standard, remaining items are subjected to further manufacturing steps. If the sample items which have been further processed do not meet the requisite quality control standard, the lot from which the samples do not undergo the additional manufacturing step. Invention provides an improved method of manufacturing in that it prevents unnecessary manufacturing steps.

Abstract: A method for testing node interconnection on a circuit board. The method utilizes an automated test system having at least one test channel, wherein each test channel has a digital driver with a first input and a first output, and a digital receiver with a second output and a second input. The second input of the receiver is coupled to the first output of the driver and to a test probe. The test probe is configured to couple the driver and receiver to one of a plurality of nodes on a circuit board. During a node interconnection test, the driver of a first test channel applies a test signal to a selected node of the plurality of nodes. A predetermined amount of time after application of the test signal, the receiver of the first test channel reads a node voltage of the selected node. The node voltage is then compared to a predetermined threshold voltage of the receiver of the first test channel, and the result of the comparison is an indication as to whether the selected node is coupled to ground.

Abstract: Noise is introduced into test inputs and voltage supplies provided to logic devices while under going testing by modulating a test voltage output with a noise signal to produce the test input. In particular, a noise signal and a test voltage output are generated. The test voltage output is modulated with the noise signal to provide a test input to the logic device. A more accurate approximation of an actual operating environment is thereby provided.

Abstract: During the development of process parameters for fabricating an integrated circuit, a test circuit is provided on the wafer that provides rapid identification of process problems (i.e., before failure analysis), detects defects down to a part-per-million (PPM) level, and identifies the precise location of any defects, thereby facilitating rapid failure analysis during the development and refinement of IC fabrication processes used to fabricate an integrated circuit (IC). In a first embodiment, the test circuit includes parallel conductive paths that are selectively connected to a signal source by pass transistors. Open circuits are identified by sequentially connecting one end of the conductive paths to the signal source and measuring the current at the other end. In a second embodiment, the test circuit includes perpendicular sets of overlapping conductors. Short conductive segments extend in parallel with a first set of conductors that are electrically connected to a second set of conductors.

Abstract: A trigger delay compensation arrangement for use in a digital storage oscilloscope, includes a trigger circuit for receiving a TRIGGER OUT signal generated from a logic analyzer in response to a logic analyzer trigger event signal, for starting a post trigger counter. It also includes a data entry circuitry for entering data input by a user, the data being representative of a delay between a reception of the logic analyzer trigger event signal and the generation of the TRIGGER OUT signal by the logic analyzer. A post trigger counter stops an acquisition of signal data upon expiration of a count of the post trigger counter. A controller, coupled to the data entry circuitry and to the post trigger counter receives the delay representative data, and adjusts the count of the post trigger counter in a direction to compensate for the delay.

Abstract: An integrated circuit (IC) tester includes a separate arbitrary waveform generator (AWG) for each input terminal of an IC to be tested. Each AWG generates a test signal input to the IC terminal that linearly ramps between discrete levels to approximate a smoothly varying waveform. Each AWG includes a digital-to-analog converter (DAC) formed by a set of N ramp generators, with each ramp generator producing output currents that ramp at adjustable rates between discrete levels in response to a change in state of an input waveform data bit. The output currents of all N ramp generators of the DAC, which have separately weighted magnitude levels, are summed and converted to a proportional voltage to produce the AWG's test signal.

Abstract: A test mode detector (12a) that places a multi-pin integrated circuit (10) in test mode. The test mode detector (12a) comprises a pulse detector (25) that receives a control signal. The control signal controls when the integrated circuit (10) is in test mode. The test mode detector (12a) further includes a latch (27) that is responsive to the pulse detector (25) so as to set the latch (27) when the pulse detector (25) detects a pulse in the control signal that exceeds a threshold level. The latch provides a signal that places the integrated circuit (10) in test mode for a period of time that is greater than the duration of the pulse of the control signal.

Abstract: A load sensing circuit detects an input load signal across a transformer based on changes in electric current conducted through a primary winding of the transformer. A triangle wave signal is provided to the primary winding of the transformer to induce a corresponding signal at a secondary winding of the transformer. The signal at the secondary winding varies as a function of the input load signal to effect corresponding changes in the electric current conducted through the primary winding. An output circuit provides an indication of the value of the load signal based on the current conducted through the primary winding.

Abstract: An automated test and evaluation sampling system includes a fast pattern memory (130) and a slow pattern memory (137) storing first and second sets of tests states, respectively. Stimulus logic (131) is connected to the fast pattern memory to read the first set of test states at a first rate and stimulate a device under test (133) according to the first set of test states. Compare logic (135) is connected to the slow pattern memory to read the second set of test states at a second rate which is slower on average than the first rate and to compare the second set of test states with a sampled output signal from the device under test.

Abstract: A system and method for locating a circuit defect, such as a short or an incipient open, in an electric circuit in a workpiece, such a Printed Circuit Board (PCB) or MultiChip Module (MCM). The circuit is connected to a device for sensitively measuring any resistance change. A thermal stimulus is applied to various subsets of the surface of the workpiece, the thermal stimulus being temporally modulated, and the resistance change measurement correlated with this modulation. By applying well-designed thermal stimulus subsets, resistance measurements may be logically combined which correspond to the plural thermal stimulus subsets. Further, the search region where the defect may be located may be iteratively refined. By measuring the time delay between the thermal stimulus and corresponding resistance change, the depth of a defect below the surface of the workpiece is further determined.

Abstract: An integrated circuit (IC) tester includes a separate arbitrary waveform generator (AWG) for each input terminal of an IC to be tested. Each AWG generates a test signal input to the IC terminal that linearly ramps between discrete levels to approximate a smoothly varying waveform. Each AWG includes a digital-to-analog converter (DAC) formed by a set of N ramp generators, with each ramp generator producing output currents that ramp at adjustable rates between discrete levels in response to a change in state of an input waveform data bit. The output currents of all N ramp generators of the DAC, which have separately weighted magnitude levels, are summed and converted to a proportional voltage to produce the AWG's test signal.

Abstract: A method for determining whether short circuits exist among networks within a circuit under test includes bringing test probes into contact with each such network and switching groups of the test probes among two sides of a test circuit so that current flows through the testing circuit only when one of the test probes connected to one side of the testing circuit is connected by means of a short circuit to one of the test probes connected to the other side of the test circuit. This first test process establishes the fact that a short circuit exists without determining which networks are connected by the short circuit. A version of this method subsequently applies tests to individual networks to make this determination, in the event that a short circuit is found to exist by the first test process. Other versions of this method additionally determine which networks are connected to which other networks by short circuits.

Abstract: Scan testing of logic circuitry is facilitated by providing register circuits, each having an input gate configured to selectively pass a data s signal applied to that register, a master stage configured to store a data signal passed by the input gate of that register, an interstage gate configured to selectively pass a data signal stored by the master stage of that register, and a slave stage configured to store a data signal passed by the interstage gate of that register. Inter-register gates are operatively arranged to selectively pass a data signal stored by the master stage of an associated respective first one of the registers to the master stage of an associated respective second one of the registers for storage by the master stage of that second one of the registers. During normal operation, circuitry is configured to alternately enable the input gates and the interstage gates, and to disable the inter-register gates.

Abstract: A method and apparatus are used to calibrate uncalibrated test equipment using reference devices. For each device, the calibrated test equipment is used to test the device to obtain a reference specification value. One of the devices is then selected, and an electrical identification from the selected device is retrieved. The electrical identification is associated with one of the reference specification values. A channel of the uncalibrated test equipment is used to test the selected device to obtain a measured specification value. The reference specification value associated with the electrical identification is compared with the measured specification value. Based on this comparison, the channel is calibrated.

Abstract: An IC testing apparatus which is able to measure the execution time of an automatic function for each DUT by a one-time test, and to grade said automatic function automatically based on the above measured execution time. A IC testing apparatus comprises a evaluation circuit of the automatic function with minimum execution time, a timer which is activated by the above evaluation circuit, and a timer counter which is activated by the above timer and stopped by the evaluation of each DUT, and automatically measures the execution time of automatic function of each DUT.

Abstract: An electronic telecommunications module has circuit components and conductors forming a telecommunications circuit having insertion points at which signals can be applied for test purposes and monitoring points from which responses can be tapped. The insertion and monitoring probes are mounted on the module and are connected to the respective points by shielded microcoaxial cables and the probes are connected by shield and microcoaxial cables on the connectors to allow interfacing between the particular module and the testing and diagnostic system.

Abstract: A tester that is capable of performing voltage measurements on electronic circuits is disclosed. The tester includes voltage measurement circuitry with an input, a plurality of gain stages, and switching circuitry coupled between the input and the gain stages. The switching circuitry includes a plurality of diodes, and a portion of the gain stages includes current-to-voltage converters. Each diode is coupled to a respective current-to-voltage converter. By applying different bias voltages to the respective current-to-voltage converters, the diodes can be made to conduct current for different ranges of voltages at the input. The output of each current-to-voltage converter is proportional to a respective voltage range.

Abstract: An electronic circuit tester (e.g., for testing integrated circuit wafers or packaged integrated circuits) is provided. The tester is preferably based on a relatively inexpensive computer system such as a personal computer and includes at least one high-precision clock circuit that is programmable with respect to frequency and number of clock pulses. The high-precision clock circuit is connectable to the circuit being tested to permit certain timing-critical tests to be performed, even though a large number of other data channels in the tester are controlled by a relatively low speed clock circuit. The tester also includes analog circuitry that can be programmed to provide various analog signals suitable for performing parametric testing on an electronic device under test.

Abstract: A method for testing node isolation on a circuit board. The method utilizes an automated test system having a plurality of test channels, wherein each test channel has a digital driver with a first input and a first output, and a digital receiver with a second output and a second input. The second input of the receiver is coupled to the first output of the driver, to a number of switches, and to a test probe. The test probe is configured to couple the driver and receiver to one of a plurality of nodes on a circuit board. The number of switches are configured to selectively couple the first output and second input to ground. During a node isolation test, each node of a test node group is coupled to one of the test channels. But for a selected node of the test node group, each node of the test node group is coupled to ground via the number of switches of the test channels coupled to the nodes.

Abstract: To remove ringing from pulse. A buffer amplifier (30) is inserted in series into a path through which a signal is transmitted. Ringing caused in the output of the buffer amplifier (30) is detected by an L side comparator (31) and an H side comparator (32). When ringing is detected a current is supplied into the input of the buffer amplifier (30) through an L side current supply circuit (33) or an H side current supply circuit (34). By supplying a current from the L side and H side current supply circuits (33, 34), the overshooting portion due to ringing can be suppressed.

Abstract: An apparatus and method are provided for testing component tolerances of a device for testing integrated circuits. The testing device is generally characterized by a plurality of test connectors disposed at a test head, wherein each test connector carries electrical signals for a test channel. Further, each test channel generally corresponds to a circuit board that includes at least one driver and one receiver. In this general type of tester, a system is provided that includes a specialized DUT board that establishes a low impedance electrical connection (i.e., short) between electrical conductors of a first and second test connector. Through this low impedance path, a first driver from a first circuit board is directly connected (i.e., shorted) to a first receiver on a second circuit board. A controller is configured to control the first driver to output an electrical signal at a predetermined time.

Abstract: Pin-driver circuitry in each of an automatic circuit tester (10)'s digital driver/sensor circuits (36) includes a current sensor (Rsense, QS1, QS2, D1, and D2) and comparison circuit (58) that indicate whether the load current supplied by the driver exceeds a level set by a threshold input (CURRENT_VALUE). The pin-driver circuitry also includes a timer (60) whose output indicates whether the comparison circuit's output has been asserted for a length of time that exceeds a limit set by a duration input (TIME_VALUE). When it has, the tester disables the driver and thereby prevents damage that could otherwise result from excessive backdrive durations that the test-generation process did not anticipate. When no backdriving is sensed during a given burst of test signals, the tester forgoes the normal cool-down delay, thereby speeding the test process.

Abstract: A systematic method for assigning tester channels on an Automated Test Equipment (ATE) to various signal pins on Device Under Test (DUT). The method involves creating a test fixture or a load board for a digital Integrated Circuit (IC) by wiring the DUT pins to as few channel groups as possible. The number of channel groups required for each vector set load are calculated before the signal pins are assigned. Then, the signal pins are assigned in a systematic manner to the fewest number of channel groups. As the number of test channel groups is reduced, the amount of vector data loaded into the tester's vector memory before each test vector is executed also is reduced, therefore reducing the time and cost required to test the signal pins on the DUT.

Abstract: A system for providing testing capability of individual submodules on an integrated circuit module. A test bus having a plurality of conductors is connected to selected internal ports of said submodules through three-way analog switches. Each three-way analog switch provides the capability to observe and control an internal port through combination of the ON/OFF status of two transmission gates. Test patterns for controlling the transmission gates may be provided by onboard D flip-flops which are externally programmed to control or observe ports of an individual submodule.