Plural, Automatically Sequential Tests Patents (Class 324/73.1)
  • Patent number: 6760873
    Abstract: A built-in self test implementation for testing the speed and timing margins of the IO pins of a source synchronous IO interface (SSIO). The implementation preferably includes built-in self test logic including a pseudo-random pattern generator which is configured to generate input sequences. Buffers are connected to the IO pins, and the buffers are configured to receive the input sequences. The buffers are connected to multiple input signature registers, and the multiple input signature registers are configured to receive the input sequences from the pseudo-random pattern generator and generate signatures. Comparators are provided to compare the signatures to expected vector values and generate a pass/fail output signal. Preferably, at least one programmable delay cell is disposed between each buffer and the multiple input signature registers. The programmable delay cells provide that propagation delays can be set to perform timing margin tests.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: July 6, 2004
    Assignee: LSI Logic Corporation
    Inventors: Hong Hao, Keven B Hui, Qingwen Deng, Chung-Jen Yui
  • Patent number: 6753693
    Abstract: A test apparatus simultaneously tests a plurality of semiconductor integrated circuits according to test data stored in a single memory set. A sub-test data generator includes a plurality of data reproduction units, each of which corresponds to one of the integrated circuits being tested. Each data reproduction unit reproduces the stored test data into a reproduced test data set, which is then processed by a driver, and sent to the corresponding integrated circuit for testing.
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: June 22, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Myung Seo, Jae-Kuk Jeon, Do-Hoon Byun
  • Patent number: 6750663
    Abstract: The present invention provides for a method (30) and system (10) for isolating the input nodes (3, 4) and/or the output nodes (5, 8) of an analog device (12) and performing continuity testing thereof without using relays. The system includes an analog device having a pair of input and output terminals and a plurality of resistors (R1-R3 and R4-R6) arranged in parallel and connected thereto. The method for testing continuity of the analog device includes providing a voltage input via at least one of the resistors to either input node, and then measuring the voltage at the same node via a resistor. If a diode drop from ground is sensed there is continuity, and if the applied voltage is sensed at the node there is not continuity. As a result, the invention advantageously isolates the nodes and removes any unwanted capacitance and impedance loading thereon during testing thereof.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: June 15, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Gunvant Patel
  • Patent number: 6751767
    Abstract: A system and method for test pattern compression includes a local CPU for dividing faults into a plurality of fault groups, assigning the fault groups to respective remote CPUs, that are connected to the local CPU in parallel with each other. Each remote CPU generates test patterns having undefined values assigned to pins of the logic circuit that do not participate in fault detection. The local CPU acquires pluralities of test patterns of the remote CPUs, generates new test patterns obtained by merging those test patterns that have identical pattern numbers among the pluralities of test patterns, and attempts to merge these newly generated test patterns.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: June 15, 2004
    Assignee: NEC Electronics Corporation
    Inventor: Tamaki Toumiya
  • Patent number: 6750671
    Abstract: An apparatus for testing wafer-level semiconductor devices, in particular memory chips in which a tunable light source radiates energy onto the semiconductor devices. The tunable light source is constructed to adjust the radiated light to a specific wavelength and to a specific intensity and to project the light for a predetermined time. When the semiconductor devices are irradiated with the light, electrons in defective ones of the semiconductor devices, in which a distance between a valence band and a conduction band has a lower value as compared with that of defect-free ones of the semiconductor devices, can be transferred into the conduction band from the valence band. These defective or “poor” semiconductor devices can thus be separated out.
    Type: Grant
    Filed: July 25, 2001
    Date of Patent: June 15, 2004
    Assignee: Infineon Technologies AG
    Inventor: Udo Hartmann
  • Patent number: 6744259
    Abstract: A safety compliance test instrument includes a display capable of displaying prompts, a menu display program, software for displaying a plurality of instrument verification menus, prompts, and messages concerning results of the verification tests, and software for enabling or preventing safety compliance tests from being performed depending on results of the verification. The safety compliance instrument includes at least two different safety compliance tests involving different connections to a device under test. The tests may be selected from the group consisting of a continuity test, a ground test, a dielectric withstand test, and an insulation resistance test, and more specifically from the group consisting of a continuity test, a ground bond test, AC and DC dielectric withstand tests, and an insulation test.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: June 1, 2004
    Assignee: Associated Research, Inc.
    Inventor: Roger A. Bald
  • Patent number: 6737852
    Abstract: A clock skew measuring apparatus for measuring a clock skew between a plurality of clock signals to be measured in a device under test, includes: a clock signal selecting element for receiving clock signals and outputting them by selecting one of the clock signals one by one; and a clock skew estimator for receiving a reference signal input to the device under test and the clock signals to be measured selected by the clock signal selecting element one by one and for obtaining the clock skew between the clock signals to be measured.
    Type: Grant
    Filed: October 25, 2001
    Date of Patent: May 18, 2004
    Assignee: Advantest Corporation
    Inventors: Mani Soma, Masahiro Ishida, Takahiro Yamaguchi
  • Patent number: 6737881
    Abstract: An apparatus for testing digital and analog signals from an integrated circuit includes an adder or subtractor 17 for being supplied with an analog signal outputted from the integrated circuit of a device under test and a signal outputted from a driver 11, an integrator 14 for being supplied with an analog signal outputted from the adder or subtractor 17, a switch 22 for selectively transmitting an analog signal outputted from the integrator 14 and a digital signal outputted from the integrated circuit to the comparator 13, and a switch 24 for selectively transmitting a signal outputted from a memory 20 and a signal outputted from a comparator 13 to the driver 11. At least one of the switches 22, 24 is operated depending on whether a signal to be tested is analog or digital.
    Type: Grant
    Filed: January 22, 2002
    Date of Patent: May 18, 2004
    Assignee: Agilent Technologies, Inc.
    Inventors: Hiroshi Sakayori, Takanori Komuro
  • Patent number: 6723942
    Abstract: An automatic breakthrough detection device for drilling electric discharge machine is provided. The automatic breakthrough detection device utilizing the facts of the variations of high frequency spectrum components of the provided discharge voltage and the variation of servo-feed-rate of the electrode as drilling discharge. The device includes a high frequency spectrum detecting analyzer to produce digital logic determining signals and a breakthrough judging logic device to judge the breakthrough by the electrode on the workpiece. Accordingly, the drilling electric discharge machine automatically adjusts the discharge parameters and the electrode withdrawals from the drilled hole and continues the next drilling hole on the workpiece. The present invention also provides a method of the same.
    Type: Grant
    Filed: March 6, 2003
    Date of Patent: April 20, 2004
    Assignee: Industrial Technology Research Institute
    Inventors: Jui-Kuan Lin, Yung-Feng Nien
  • Patent number: 6724182
    Abstract: A pair of resistors, having substantially equivalent resistance are arranged in series so that two data output lines of a differential data driver are connected to the ends of the series of resistors, the potentials of the two output signals ((D+)data output signal and (D−)data output signal) from the differential data driver are resistively divided to detect the sum of the potentials of the two signals. Based on the voltage of the combined signal, the acceptability of the differential signals of the differential data driver is determined.
    Type: Grant
    Filed: March 11, 2002
    Date of Patent: April 20, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Koji Isodono, Toyohiko Tanaka, Hitoshi Imai, Hitoshi Saitoh
  • Patent number: 6720791
    Abstract: An LCD panel testing method. The method comprises forming jump lines in a predetermined region on the substrate between the signal lines via mask design when forming TFT LCD arrays, and thus forming a plurality of signal-line groups each with two signal lines coupled by the jump lines. Thereupon, an array tester sequentially tests two pixels corresponding to the signal lines in the signal groups. If one of the feedback signals from the signal groups does not meet a predetermined standard, it is determined that one or both pixels in the signal group are defective. The defective pixel or pixels are then identified using an electronic microscope to test two pixels at the same time. In this way, the number of probe pins and tests performed is halved. The probe pin size is also thus less restrictive due to larger probe pin intervals. Consequently, yield is greatly increased.
    Type: Grant
    Filed: August 27, 2001
    Date of Patent: April 13, 2004
    Assignee: Hannstar Display Corporation
    Inventors: Jia-Shyong Cheng, Chia-Yu Wang, Shing-shiang Chang
  • Patent number: 6721913
    Abstract: An interface testing circuit and method for testing an interface between two or more separate hardware components provides interface testing capability without requiring complex and expensive synchronized mixed signal testing between the hardware components. The interface testing circuit includes two or more sub-circuits, each of which is adapted to selectively route either a test signal from a test input/output pad to a hardware component or route an output signal from another hardware component to the test pad. Multiple testing modes are used to fully test the interface.
    Type: Grant
    Filed: July 12, 2000
    Date of Patent: April 13, 2004
    Assignee: Marvell International, Ltd.
    Inventor: Saeed Azimi
  • Patent number: 6717427
    Abstract: A circuit arrangement (100) for controlling a first terminal and a second terminal of a preferably contactless integrated circuit, particularly for testing a CMOS circuit, tests a multitude of intergrated circuits simultaneously while using a low-cost structure. The circuit arrangement permits a simple write/read unit assigned to the integrated circuit, and enables the simultaneous testing of a multitude of integrated circuits using a low-cost structure.
    Type: Grant
    Filed: January 22, 2002
    Date of Patent: April 6, 2004
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Holger Thiel, Michael Liebig, Wolfgang Tobergte
  • Patent number: 6714031
    Abstract: The invention provides a semiconductor device that enables examination of a wafer in an initial stage to check whether the wafer is acceptable or defective in the case of DC examinations for circuit elements and also AC examinations for circuit delay times and the like. A semiconductor device is equipped with (a) a semiconductor wafer including a plurality of chip regions in which a required circuit is formed, and a scribe region to divide the plurality of chip regions, (b) a test circuit for wafer examination formed in the scribe region and formed of a plurality of transistors, and (c) an output pad formed in the scribe region and connected to the test circuit.
    Type: Grant
    Filed: May 21, 2002
    Date of Patent: March 30, 2004
    Assignee: Seiko Epson Corporation
    Inventor: Hiroshi Seki
  • Patent number: 6703844
    Abstract: Signal transit times on printed circuit boards which are equipped with all the passive components but without any active components can be determined using automatic standard test equipment composed of a standard test unit and a performance board with fittings attached thereto. In that first, using a standard routine of the test unit, a transit time is measured on the performance board from the CIF connector as far as the fitting, then a printed circuit board is plugged into the fitting location determined for it and then the sum transit time of the CIF connector is measured as far as the landing pad on the printed circuit board. By forming differences between the two measured values, the transit times on a printed circuit board can be measured with a high degree of precision with the automatic standard test equipment used in standard module testing technology.
    Type: Grant
    Filed: August 20, 2002
    Date of Patent: March 9, 2004
    Assignee: Infineon Technologies AG
    Inventors: Frank Adler, Thomas Huber, Manfred Moser, Martin Versen
  • Patent number: 6686750
    Abstract: A semiconductor integrated circuit device is provided with an IC chip so as to prevent its circuits from malfunction when the IC chip is cracked. To detect chip cracks, a resistor R01 is disposed at the outer periphery of the area in which one wants to detect the chip crack. If the chip is cracked and the resistance value of the resistor R01 is changed, the resistance change is detected, thereby controlling internal signals such as the power on reset signal and stopping the whole operation of the circuit device so as to prevent the circuits from malfunction. Thus, the system security can also be improved.
    Type: Grant
    Filed: June 10, 2002
    Date of Patent: February 3, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Kazuki Watanabe, Ryouzou Yoshino, Kenji Nagai, Tatsuya Nishihara
  • Patent number: 6671641
    Abstract: A method for calibrating hydraulic actuators includes installing an actuator in a test stand and performing an electrical signal sweep to obtain a series of pressure values. Based on desired pressure values, signals yielding unwanted pressure values are removed and the remaining signal values and pressure values are stored in a central database as a look-up table for the actuator. Multiple actuators are then assembled to form a module assembly. The customized look-up tables for the actuators forming the module assembly are retrieved from the database. Based on those tables, signals are applied to the actuators to determine if the pressure values fall within specified tolerance windows. If the pressure values fall within the specified tolerance windows, the customized look-up tables are stored in the memory of a vehicle electronics package. If not, the signals are adjusted so that the pressure values fall within the specified windows, and the adjusted customized look-up tables are then stored in the memory.
    Type: Grant
    Filed: November 15, 2000
    Date of Patent: December 30, 2003
    Assignee: Delphi Technologies, Inc.
    Inventors: Duane Zedric Collins, Gaspar Galindo
  • Patent number: 6665628
    Abstract: Methods are provided for virtually embedding and/or de-embedding balanced four-port networks into/from a device under test (DUT). For the methods, a set of scattering-parameters is acquired for the DUT. Additionally, a respective set of scatter-parameters is acquired for each of the balanced four-port networks to be embedded and/or de-embedded. A transfer-matrix is generating for the DUT based on its scattering parameters. Further, a respective transfer-matrix is generated for each of the networks to be embedded/de-embedded based on its respective set of scattering-parameters. The transfer-matrix for the DUT is then multiplied with the one or more transfer-matrices associated with the balanced four-port networks to be embedded and/or by an inverse of the transfer-matrices associated with the balanced four-port networks to be de-embedded. A composite transfer-matrix is thereby produced. Finally, a set of composite scattering-parameters is then generated based on the composite transfer-matrix.
    Type: Grant
    Filed: January 15, 2002
    Date of Patent: December 16, 2003
    Assignee: Anritsu Company
    Inventor: Jon S. Martens
  • Patent number: 6661718
    Abstract: A substrate includes a memory and a testing device for testing the memory. The testing device includes an interpreter element that operates and tests the memory in accordance with a test program. The test program command codes are stored in the untested memory cell array of the memory that will be tested. The advantage of the testing device consists, inter alia, in the fact that the testing device no longer needs to be adapted to changed hardware properties of the chip generation or fabrication lines because the test program, which is suitable for the respective chip type, is stored as a variable code on the respective memory which is to be tested. It is thus also possible to test various memory chip types with the same testing device.
    Type: Grant
    Filed: December 31, 2001
    Date of Patent: December 9, 2003
    Assignee: Infineon Technologies AG
    Inventors: Carsten Ohlhoff, Peter Pöchmüller
  • Patent number: 6657451
    Abstract: An integrated circuit is forced into a test mode through executing the following steps: presenting a test forcing pattern on a subset of the circuit's external pins for driving the circuit to a test mode, presenting the electronic test forcing pattern to the circuit and finally executing the test proper. In particular, the following steps are implemented: presenting the pattern on a single pin in the form of an aggregate of a clocking sequence and a transition signalling data sequence as input data for an on-circuit storage element; clocking the storage element by a delayed version of the test forcing pattern; sequentially storing successive data parts of the test forcing pattern under control of successive clock parts of the delayed test forcing pattern; matching a predetermined string of the stored data parts versus a standard pattern, and upon finding a match driving the circuit to a test condition for then executing a test procedure.
    Type: Grant
    Filed: November 29, 2000
    Date of Patent: December 2, 2003
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Louis Marcel Meli
  • Patent number: 6657455
    Abstract: A main power source supplies current through path impedance to a power terminal of an integrated circuit device under test (DUT). The DUT's demand for current at the power input terminal temporarily increases following edges of a clock signal applied to the DUT during a test as transistors within the IC switch in response to the clock signal edges. To limit variation (noise) in voltage at the power input terminal, an auxiliary power supply supplies an additional current pulse to the power input terminal to meet the increased demand during each cycle of the clock signal. The magnitude of the current pulse is a function of a predicted increase in current demand during that clock cycle, and of the magnitude of an adaption signal controlled by a feedback circuit provided to limit variation in voltage developed at the DUT's power input terminal.
    Type: Grant
    Filed: July 25, 2002
    Date of Patent: December 2, 2003
    Assignee: FormFactor, Inc.
    Inventors: Benjamin N. Eldridge, Charles A. Miller
  • Patent number: 6654667
    Abstract: In an active mode, a controller switches an operation mode from the active mode to a suspend mode when an acceptance preparation completion signal is not received from downstream or when a circuit board is discharged downstream, if a discharge preparation completion signal has not been received from upstream. The controller controls relay apparatuses and adjusts a flow of current to control units, in addition to controlling its own CPU clock frequency.
    Type: Grant
    Filed: July 27, 2001
    Date of Patent: November 25, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akiko Yamamoto, Kenji Okamoto
  • Patent number: 6654920
    Abstract: An integrated circuit (10) comprising combinational circuitry (13). The integrated circuit further comprises a plurality of scan channels (SC1 through SC4). Each of the plurality of scan channels comprises a number of scan elements (EC11 through EC45). For any of the plurality of scan channels having a number of scan elements greater than one element, the scan channel comprises a first element in the scan channel and a last element in the scan channel. For any of the plurality of scan channels having a number of scan elements equal to one element, the one element is both a first element and a last element in the scan channel. Further, selected ones of the scan elements are coupled to affect operation of the combinational circuitry. The integrated circuit further comprises circuitry (24) for coupling a predetermined pattern into the first element of each of the plurality of scan channels and circuitry (26) for detecting the predetermined pattern in the last element of each of the plurality scan channels.
    Type: Grant
    Filed: October 25, 2000
    Date of Patent: November 25, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Graham G. Hetherington, Anthony Fryars
  • Patent number: 6647526
    Abstract: A system and method is provided for testing industrial control modules. Input and output stimulus signals, communication lines, measurement device lines and relay contacts are provided at a tester interface panel. This allows for a test developer to configure the relay contacts in any way that the developer desires to provide appropriate connections of stimulus, communications and measurements for a given industrial control module. The switching of the relays between a normally closed position and a normally open position can be controlled by output modules coupled to a computer. The relays can be insertable and releasable in a socket for easy fault isolation and replacement. Furthermore, the same relays or similar relays can be employed for both low current measurements and high power stimulus.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: November 11, 2003
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Michael Holder, James Wojcik
  • Patent number: 6639397
    Abstract: An electronic circuit for automatic test equipment for testing a device under test includes two lines for connecting the circuit with a device under test. Two comparators are provided, one input of each of the comparators being connected to different ones of the two lines. A further comparator is provided, the two inputs of the further comparator being connected to different ones of the two lines. Each of the two lines is terminated. Switching elements are provided which are connected between the two lines. The switching elements enable the circuit to be used in different modes, in particular with a single-ended termination and with a differential termination.
    Type: Grant
    Filed: October 31, 2001
    Date of Patent: October 28, 2003
    Assignee: Agilent Technologies, Inc.
    Inventors: Bernhard Roth, Henriette Ossoinig
  • Patent number: 6639409
    Abstract: A battery voltage measurement device includes: a plurality of first switching sections, wherein each pair of adjacent first switching sections sequentially selects two output terminals of each of a plurality of battery blocks included in a battery pack so that each of the selected output terminals are connected to one of a pair of conductor wires; a voltage detection section for detecting a battery voltage of each of the plurality of battery blocks via the pair of conductor wires; and second switch sections each being provided on a respective one of the pair of conductor lines and being serially connected to each group of the plurality of first switch sections connected in parallel to one of the pair of conductor lines.
    Type: Grant
    Filed: November 2, 2001
    Date of Patent: October 28, 2003
    Assignees: Matsushita Electric Industrial Co., Ltd., Toyota Jidosha Kabushiki Kaisha
    Inventors: Naohisa Morimoto, Ichiro Maki, Hirofumi Yudahira
  • Patent number: 6624652
    Abstract: The CPU of a test apparatus sends, to a subject test board, a test command containing an address in an address space where circuit blocks of the subject test board are mapped and a command code specifying an operation to be performed to the address. Test program executed by the CPU of the subject test board allow the CPU to extract the address and the command code included in the test command from the test apparatus and then to perform the operation specified by the command code to the address.
    Type: Grant
    Filed: May 1, 2001
    Date of Patent: September 23, 2003
    Assignee: Pentax Corporation
    Inventors: Mikio Horie, Ryoichi Nakanishi
  • Patent number: 6621283
    Abstract: A semiconductor device mounted on a board or the like and having a test circuit, having the function of carrying out a contact test at a low cost on the terminals of the semiconductor, is disclosed. The semiconductor device comprises a terminal test circuit for testing a state of a contact of an external terminal and a test mode control circuit unit. The test mode control circuit unit outputs a signal indicating a first operation mode upon application of a power supply voltage thereto, outputs a test mode signal to the terminal test circuit in response to a control signal input to a specific terminal such as a chip select terminal, and outputs a signal indicating a second operation mode in response to the number of times in which the level of the control signal input to the specific terminal changes. Preferably, the first operation mode is a terminal test mode, and the second operation mode is a normal operation mode.
    Type: Grant
    Filed: November 10, 1999
    Date of Patent: September 16, 2003
    Assignee: Fujitsu Limited
    Inventors: Yasurou Matsuzaki, Masao Nakano, Toshiya Uchida, Atsushi Hatakeyama, Kenichi Kawasaki, Yasuhiro Fujii
  • Patent number: 6617844
    Abstract: The compare path bandwidth control for high performance automatic test systems provides a standard dual comparator mode with single ended transmission lines for low frequency applications with a capability of receiving a differential signal when using the dual comparators (40), (41) as an effective single comparator for high frequency applications.
    Type: Grant
    Filed: September 23, 2002
    Date of Patent: September 9, 2003
    Assignee: Texas Instruments Incorporated
    Inventor: Craig J. Lambert
  • Patent number: 6614254
    Abstract: There is a possibility that user brings a semiconductor dynamic random access memory device to a burn-in test after packaging, and a power transfer circuit is connected between an external pin and an internal power supply line, wherein the power transfer circuit discriminates an external high power voltage from other lower voltages so as connect the external pin to the internal power supply line, thereby allowing the user to carry out the burn-in test at a high speed.
    Type: Grant
    Filed: October 31, 2001
    Date of Patent: September 2, 2003
    Assignee: NEC Corporation
    Inventor: Satoshi Tamaki
  • Patent number: 6608496
    Abstract: An interconnect assembly for evaluating a probe measurement network includes a base, respective inner and outer probing areas in mutually coplanar relationship on the upper face of the base, a reference junction, and a high-frequency transmission structure connecting the probing areas and the reference junction so that high-frequency signals can be uniformly transferred therebetween despite, for example, variable positioning of the device-probing ends of the network on the probing areas. A preferred method for evaluating the signal channels of the network includes connecting a reference unit to the reference junction and successively positioning each device-probing end that corresponds to a signal channel of interest on the inner probing area.
    Type: Grant
    Filed: July 7, 2000
    Date of Patent: August 19, 2003
    Assignee: Cascade Microtech, Inc.
    Inventors: Eric W. Strid, Jerry B. Schappacher, Dale E. Carlton, K. Reed Gleason
  • Patent number: 6597165
    Abstract: The compare path bandwidth control for high performance automatic test systems provides a standard dual comparator mode with single ended transmission lines for low frequency applications with a capability of receiving a differential signal when using the dual comparators (40), (41) as an effective single comparator for high frequency applications.
    Type: Grant
    Filed: September 23, 2002
    Date of Patent: July 22, 2003
    Assignee: Texas Instruments Incorporated
    Inventor: Craig J. Lambert
  • Patent number: 6590408
    Abstract: Within both an electrical test apparatus for electrically testing a substrate, and a method for electrically testing the substrate while employing the electrical test apparatus, there is provided for an automatic selection of an electrical test program, absent operator intervention, once having identified a substrate. Due to the absence of operator intervention, the substrate is more accurately electrically tested.
    Type: Grant
    Filed: May 29, 2002
    Date of Patent: July 8, 2003
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Min Cheng, Chun-Sheng Wang, Ming-Hui Lin, Sheng-Guei Chang, Juei-Feng Hsu
  • Patent number: 6583628
    Abstract: A process to determine malfunctioning detectors in a danger signaling system having a control center and at least two-wire signaling line joined to multiplicity of detectors.
    Type: Grant
    Filed: December 13, 2000
    Date of Patent: June 24, 2003
    Assignee: Job Lizenz GmbH & Co. KG
    Inventor: Gerhard Röpke
  • Patent number: 6577979
    Abstract: A semiconductor integrated circuit with a IP test circuit having a IP test circuit, a IP6, a IP7, a COU 4, a SRAM 5. The IP test circuit has a IP test controller 21 including a register 21, a test sequencer 2, a selector 3, and a bus interface 11. Under the control of the IP test controller 1, a test program and test data in serial form are transferred from an external tester through a test data terminal 9 and then converted to the test program and the test data in parallel form. The converted test program and the test data are stored into the SRAM 5. The CPU 4 executes the test operation for the IP6 directly connected to a cpu bus 8. The test sequencer 7 executes the test operation for the IP7 that is not directly connected to the cpu bus 8. The test results are transferred to the external tester through the test data terminal.
    Type: Grant
    Filed: October 7, 1999
    Date of Patent: June 10, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Takenori Okitaka
  • Patent number: 6573699
    Abstract: A device for measuring an electric current of a target circuit includes a pair of contact pins, a resistor electrically connected between the contact pins, a voltage drop appearing across the resistor when the contact pins come into contact with the target circuit to direct the electric current to the resistor, and an electro-optical crystal electrically connected between the contact pins in parallel with the resistor, the electro-optical crystal having a voltage applied thereto responsive to the voltage drop appearing across the resistor, wherein the voltage applied to the electro-optical crystal changes polarization of a light beam passing therethrough, thereby allowing the electric current to be measured from the polarization.
    Type: Grant
    Filed: September 12, 2000
    Date of Patent: June 3, 2003
    Assignee: Fujitsu Limited
    Inventors: Soichi Hama, Akira Fujii, Hidenori Sekiguchi, Shinichi Wakana, Toshiaki Nagai
  • Publication number: 20030094934
    Abstract: There is provided a semiconductor integrated circuit device provided with a test clock generating circuit which enables high performance test operation and a method of designing a semiconductor integrated circuit device which enables setting of high precision timing margin or the like. The test clock generating circuit provided with a register sequential circuit and a clock output control circuit is provided between the pulse generating circuit and logic circuit. When the test operation is validated, transfer of clock pulse generated in the pulse generating circuit to the logic circuit is stopped and the clock pulse to operate the logic circuit is outputted using the pulse signal generated in the pulse generating circuit by controlling the clock transfer control circuit with the sequential circuit depending on the setting information of register. The test clock generating circuit is comprised with the logic design tool utilizing a computer in order to test the logic circuit function and timing margin.
    Type: Application
    Filed: November 12, 2002
    Publication date: May 22, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Hisakazu Date, Toyohito Ikeya, Masatoshi Kawashima
  • Patent number: 6564986
    Abstract: A method and assembly for testing multiple IC packages for solder joint fractures that occur in response to thermal cycling. A test PCB is fabricated with contact pads arranged to match a BGA IC package footprint, wherein pairs of the contact pads are linked by conductive traces (lines) to form a lower portion of a daisy chain. The BGA IC package is modified to link associated pairs of solder balls, e.g., using wire bonding to form an upper portion of the daisy chain. Mounting the BGA IC package on the test PCB completes the daisy chain. By alternating between the test PCB contact pads that are linked by conductive traces and the solder balls that are linked by wire bonding, the daisy chain provides a conductive path that passes through all solder balls of the BGA IC package.
    Type: Grant
    Filed: March 8, 2001
    Date of Patent: May 20, 2003
    Assignee: Xilinx, Inc.
    Inventor: Steven H. C. Hsieh
  • Patent number: 6556004
    Abstract: A supporting framework for a display panel or a probe block is capable of properly coping with display panels of different sizes in a testing apparatus. By moving a framework 1 with a display panel supported thereon or by moving frame members 2, 3, 4, 5 of the framework 1 with a probe block supported thereon, an opening (or space) defined by the respective frame members can be enlarged or reduced.
    Type: Grant
    Filed: September 12, 2001
    Date of Patent: April 29, 2003
    Assignees: Soshotech Co., Ltd., Adtec Engineering Co., Ltd.
    Inventors: Toshio Okuno, Gunji Mizutani, Masatomo Nagashima
  • Patent number: 6553522
    Abstract: Tester edge placement accuracy (EPA) is important for testing of semiconductor component devices. The value of that accuracy is quantified to the device manufacturer in terms of yield loss and bad parts sold as good parts (escapes in DPM). A simulation is presented that models the tester accuracy, the device edge distribution and their interaction for a example device having an operating speed of 800 Mbps. The same model can be applied for microprocessors or other parts that operate near the limits of ATE performance. In an example given, the estimated losses due to lack of appropriate tester accuracy are considerable: with the estimated yields and selling prices for the example device, the model shows a value of over $1 M for every 1 ps of enhanced tester edge placement accuracy.
    Type: Grant
    Filed: February 22, 2000
    Date of Patent: April 22, 2003
    Assignee: Schlumberger Technologies, Inc.
    Inventors: Wajih Dalal, Song Miao
  • Patent number: 6552561
    Abstract: An apparatus and method for controlling temperature in a device under test (DUT) having an integrated circuit chip die includes a temperature sensing device, such as a temperature sensitive diode, integrally formed in the chip die. A sensing circuit senses a signal from the diode indicative of temperature of the chip die. The sensing circuit can be part of a testing circuit in a system being used to test the DUT. The sensing circuit sends a control signal to a temperature control system used to control the temperature of a DUT temperature control medium. The temperature control medium can be, for example, a stream of temperature-controlled air directed onto the package of the DUT. In response to the control signal, the temperature control system controls the temperature of the air at a desired temperature to control the temperature of the DUT.
    Type: Grant
    Filed: April 20, 2001
    Date of Patent: April 22, 2003
    Assignee: Temptronic Corporation
    Inventors: Douglas S. Olsen, David Stura
  • Patent number: 6545494
    Abstract: An apparatus and method for controlling temperature in a wafer on a wafer chuck includes a temperature sensing device, such as a temperature sensitive diode, integrally formed in the wafer. A sensing circuit senses a signal from the diode indicative of temperature of the wafer. The sensing circuit can be part of a testing circuit in a wafer prober being used to test integrated circuits on the wafer. The sensing circuit sends a control signal to a temperature control system used to control the temperature of the chuck. In response to the control signal, the temperature control system controls the temperature of the chuck at a desired temperature to control the temperature of the wafer. The wafer can include multiple integrated circuit die, and each circuit can include its own temperature sensing diode. As a result, extremely accurate and individualized temperature testing can be performed on each integrated circuit on the wafer.
    Type: Grant
    Filed: July 10, 2000
    Date of Patent: April 8, 2003
    Assignee: Temptronic Corporation
    Inventors: Douglas S. Olsen, David Stura
  • Publication number: 20030062918
    Abstract: A function test circuit inside a burn-in apparatus is mounted on a burn-in board and specifies a plurality of checked devices which operate normally. An average voltage calculating circuit calculates average voltage for test voltage applied to a plurality of checked devices specified on a mounting section. A voltage correction circuit receives the average voltage and outputs a control signal to control set voltage output from a device power supply generation circuit. Therefore, this burn-in apparatus can set the test voltage applied to the checked devices readily with high accuracy.
    Type: Application
    Filed: August 22, 2002
    Publication date: April 3, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Osamu Hashimoto
  • Patent number: 6541994
    Abstract: A semiconductor device and a method for testing the semiconductor device of the present invention includes n macro blocks which process input data supplied from input terminals and output the data from output terminals, a test circuit which supplies test data for testing the macro blocks and receives the test data processed by the macro blocks in the test mode and a test path which supplies the test data from the test circuit to the input terminal of the macro block, supplies data of the output terminal of the k-th (k=1 to (n−1)) macro block to the input terminal of the macro block to the test circuit in the test mode. One macro block can be selected randomly to be tested.
    Type: Grant
    Filed: May 7, 2001
    Date of Patent: April 1, 2003
    Assignee: NEC Corporation
    Inventor: Kazuaki Masuda
  • Patent number: 6531865
    Abstract: A test circuit for and method of testing integrated circuit packages can be utilized to determine the existence of one or more short circuits between adjacent connectors. The system includes an interface configured to electrically connect the conductors of the integrated circuit package. The interface groups the conductors into a plurality of nodes. The number of nodes is no more than one-half the number of conductors. A control circuit is coupled to the interface. The control circuit determines the existence of one or more short circuits between adjacent conductors in response to signals on the nodes.
    Type: Grant
    Filed: December 19, 2000
    Date of Patent: March 11, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Zhihong Mai, Seok Hiong Tan, Seck June Foo
  • Patent number: 6529030
    Abstract: In a circuit 10 of an IC testing apparatus 1 in which a wave-form of a pattern signal 2a outputted from a pattern generator 2 is shaped and timing of the pattern signal is adjusted so that a testing signal 10a is created and a device 3 to be tested is made to carry out a predetermined processing according to the testing signal 10a and the quality of the device 3 to be tested is judged by comparing an obtained output signal 3a with an expecting processing result, the pattern signal 2a is outputted from AND gate 111 to TG/FC circuit 12 in Write Mode, and DEN control signal 101a is outputted from AND gate 113 to TG/FC circuit 12 by inverting Write/Read change-over signal 2b by an inverter 112 in Read Mode.
    Type: Grant
    Filed: May 9, 2000
    Date of Patent: March 4, 2003
    Assignee: Ando Electric Co., Ltd.
    Inventor: Shigeki Ishii
  • Patent number: 6515484
    Abstract: An electrical test instrument includes an improved operator interface capable of including the following features: (i) a pause/prompt feature enable prompts to be displayed during a pause, in order to facilitate operator reconfiguration of the instrument during testing; (ii) an autocalibration alert function to alert the operator that the instrument requires calibration; (iii) a security function that enables the operator to select from among a plurality of security level options; and (iv) a more flexible menu structure that enables set-up of additional tests performed by plug-in test instrument modules.
    Type: Grant
    Filed: October 31, 2000
    Date of Patent: February 4, 2003
    Assignee: Associated Research, Inc.
    Inventors: Roger A. Bald, Pin-Yi Chen
  • Patent number: 6507209
    Abstract: A test circuit generally comprising a tester connected to a socket for holding a device under test. The device may be configured to have (i) a first function and (ii) a final function. The tester may be configured to (i) stimulate the first function with a test signal to present a first output signal, (ii) stimulate the final function with the first output signal to present a final output signal; (iii) measure a result between the test signal and the final output signal, and (iv) allocate the result between the first function and the final function to disperse a measurement error in the result.
    Type: Grant
    Filed: May 8, 2001
    Date of Patent: January 14, 2003
    Assignee: Cypress Semiconductor Corp.
    Inventor: Christopher W. Jones
  • Patent number: 6505127
    Abstract: A foreign material interference detection apparatus for an opening/closing member that reduces the calculation load for foreign material interference determination processing. A rotating speed detection sensor detects the rotating speed of a motor and provides its detection signal SP to a computer. The computer obtains a load determination rotating cycle t1 from the detection signal SP. Based on the load determination rotating cycle t1, the computer determines foreign material interference when it determines that the rotating speed is fluctuating due to a load that is the same as that produced when a foreign material is interfering with the opening/closing member and when the determination is made consecutively a predetermined number of times.
    Type: Grant
    Filed: April 26, 2000
    Date of Patent: January 7, 2003
    Assignee: ASMO Co., Ltd.
    Inventor: Katsutaka Togami
  • Patent number: 6499126
    Abstract: A pattern generator that generates a test pattern used for testing an electric part including: a pattern memory that stores test pattern information, which defines the test pattern; a vector memory that stores a vector instruction, which indicates an order for reading out the test pattern information from the pattern memory; an address expansion unit that generates an address of the test pattern information in the pattern memory according to the vector instruction stored in the vector memory; an interruption pattern memory that stores interruption test pattern information, which defines the test pattern during a predetermined interruption process; an interruption vector memory, which is different from the vector memory, that stores an interruption vector instruction which indicates an order for reading out the interruption test pattern information from the interruption pattern memory; an interruption address expansion unit that generates an address of the interruption test pattern information according to th
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: December 24, 2002
    Assignee: Advantest Corporation
    Inventor: Masaru Tsuto