Abstract: The present invention is directed toward a hand-held “off-board” device, such as a scan tool or code reader, having a test circuit in the same housing that tests the condition of a starter charging system. Such a tester of the present invention allows a user to purchase and maintain a single device that can perform the desired diagnostic tests that are currently being performed by the separate devices.

Abstract: An interconnect assembly for evaluating a probe measurement network includes a base, respective inner and outer probing areas in mutually coplanar relationship on the upper face of the base, a reference junction, and a high-frequency transmission structure connecting the probing areas and the reference junction so that high-frequency signals can be uniformly transferred therebetween. A preferred method for evaluating the signal channels of the network includes connecting a reference unit to the reference junction and successively positioning each device-probing end that corresponds to a signal channel of interest on the inner probing area.

Abstract: Initialization of a bidirectional, self-timed parallel interface with capacitive coupling is provided. The self-timed interface includes master and slave nodes connected by a parallel bus comprising multiple AC differential wire pairs. The initialization includes automatically testing at least one wire pair of the multiple AC differential wire pairs for conductivity failure, wherein the testing is responsive to a link reset signal of a first frequency. The automatically testing includes employing a link test signal of a second frequency to test the at least one wire pair of the multiple AC differential wire pairs. The second frequency is a lower frequency than a third, operational signal frequency of the self-timed parallel interface, and the first frequency and the second frequency comprise different frequencies. An initialization testing and handshake approach between the master node and slave node is also provided.

Abstract: A memory test system for peak power reduction. The memory test system includes a plurality of memories, a plurality of memory built-in self-test circuits and a plurality of delay units. Each of the memory built-in self-test circuits comprises a built-in self-test controller for receiving a clock signal and producing a plurality of required control signals to test one of the memories. Each of the delay units is coupled between two adjacent built-in self-test controllers. The clock signal input to one of the built-in self-test controllers is received by the delay unit to produce a delayed clock signal, and the delay unit outputs the delayed clock signal to the other.

Abstract: Integrated module having a circuit and a plurality of input/output terminals, each of the input/output terminals being connected to a driver circuit for driving output signals and to a reception circuit for receiving input signals, a first delay element with a first delay time being provided in the integrated module, which delay element can be connected into a signal path of a circuit-internal signal or can be disconnected, in order to delay or to accelerate the circuit-internal signal, wherein provision is made of a first test delay element at a first input/output terminal pair which is embodied in a manner structurally identical to the first delay element, in order, in a test operation, to determine the delay time by means of the signal propagation time between the two input/output terminals of the first input/output terminal pair.

Abstract: According to the present invention, there is provided an insulator capacitance analyzer for analyzing C-V characteristics of a first MIS structure having unknown capacitance, which includes: a capacitance structure having known capacitance and configured so as to be serially connectable to the first MIS structure; and a measuring section for measuring synthesis capacitance of the serially-connected first MIS structure and capacitance structure.

Abstract: A detecting device for detecting electromagnetic waves generated by electric facilities includes a support having a peripheral surface for attaching a number of wave detectors which detect the electromagnetic waves generated by the electric facilities. The support may include a housing having a chamber for receiving the electric facilities, or having a curved outer peripheral surface for supporting the wave detectors. The wave detectors each has a number of light devices for indicating the strength of the received electromagnetic waves.

Abstract: One embodiment of a method for analysis of cache array test data comprises retrieving test results for a current period of time for a first plurality of storage elements and for a historical period of time for a second plurality of storage elements; determining a plurality of attributes for each of the first storage elements and the second storage elements based upon the test results, the attributes comprising one of a good condition, a defective condition, a repairable condition and a repaired condition; determining a plurality of attribute statistics corresponding to the attributes of the first storage elements and the second storage elements; and generating an output report indicating at least two of the attribute statistics of the first storage elements and the second storage elements.

Abstract: A tester comprising a reference clock generating section for generating a reference clock having a first frequency, a first test rate generating section for generating a first test rate clock having a frequency which is about an integral multiple of the first frequency, a second test rate generating section for generating a second test rate clock having a frequency which is about an integral multiple of the first frequency and different from the frequency of the first test rate clock, a first driver section for supplying a test pattern to an electronic device according to the first test rate clock, and a second deriver section for supplying the test pattern to the electronic device according to the second test rate clock.

Abstract: A main power source supplies current through path impedance to a power terminal of an integrated circuit device under test (DUT). The DUT's demand for current at the power input terminal temporarily increases following edges of a clock signal applied to the DUT during a test as transistors within the IC switch in response to the clock signal edges. To limit variation (noise) in voltage at the power input terminal, an auxiliary power supply supplies an additional current pulse to the power input terminal to meet the increased demand during each cycle of the clock signal. The magnitude of the current pulse is a function of a predicted increase in current demand during that clock cycle, and of the magnitude of an adaption signal controlled by a feedback circuit provided to limit variation in voltage developed at the DUT's power input terminal.

Abstract: A test system that tests first through m-th circuit devices for defects. The test system includes a controller and first through m-th control circuits. The controller is configured to generate a test signal having information for testing first through m-th circuit devices. The first through m-th control circuits are each configured to test a respective one of the first through m-th circuit devices for a defect using the test signal, and to stop testing the respective one of the first through m-th circuit devices when a defect is identified.

Abstract: In a method of testing an IC, short circuits between adjacent I/Os are tested by grounding alternate rows in one step, and alternate columns in another step, and, if necessary including a third step of testing any inadequately tested I/Os by identifying inadequately tested I/Os and then testing these. The identifying may include performing an AND operation on the two I/O configurations of the two first steps, the grounded I/Os being defined as logic 0 and the tested I/Os as logic 1. The third step involves grounding all power supply and all ground pins of the IC and testing the remaining I/Os that were inadequately tested in both of the first two steps.

Abstract: An automatic integrated circuit testing system, device and method using an integrative computer. The system includes a machine frame having at least one testing computer for holding and testing the integrated circuit. The machine frame also has at least one automatic plugging/unplugging machine for engaging the integrated circuits with the computer system and removing the integrated circuits after testing has been completed. The machine frame further includes at least one controller device electrically connected to the testing computer and the automatic plugging/unplugging machine for controlling the movements of the automatic plugging/unplugging machine and the testing computer. The testing computer and the integrated circuit together form an integrative computer system capable of executing various general application programs and special testing programs for integrative testing and analysis.

Abstract: A circuit for test pattern generation compression of circuits with a built-in self-test function has a test data coupling circuit having a test data input for receiving a test data input signal from a circuit cell connected upstream, which signal can be stored in a test data buffer store, a data input for applying a data input signal, which can be stored in a buffer store, a test data output for outputting the buffer-stored test data signal, and a data output for outputting the buffer-stored data signal to a data signal path via a data signal output of the circuit cell, the two buffer stores of the test data coupling circuit having a common feedback signal path, via which the received test data input signal can be coupled into the data signal path depending on a first control signal applied to the test data coupling circuit.

Abstract: A test apparatus and a method for testing an integrated circuit's data storage device's input/output signal pins for alternating current (AC) defects, by providing an interface that will couple each respective individual test contact, in a subset of said contacts, to a select plurality of the data storage input/output signal pins so that when a selected data string is introduced into the integrated circuit so that each input/output pin on a data storage device in the integrated circuit will be tested in sequence whereby the number of contacts required by the tester can be reduced.

Abstract: A method and apparatus for Interconnect Built-In Self-Test (IBIST) Based System Management Performance Tuning provides for measuring operating conditions of an interconnect, which is between a first device and a second device in a post-production system, at operating speed with a set of one or more test data and a first set of one or more operating parameters. Results of the measuring are stored and operating conditions of the interconnect with the set of test data and a second set of operating parameters are measured. The method and apparatus further provides for selecting either the first or second set of operating parameters based on the measuring of operating conditions to optimize operation of the post-production system.

Abstract: A disc drive slider test system includes a support structure and a slider test socket carried by the support structure that releasably electrically and mechanically receives a slider for testing. The slider test socket includes a body forming a cavity for receiving the slider and a plurality of spring beams outside a plan area of the body connected to a clamp for releasably securing the slider in the cavity. In some exemplary embodiments, a microactuator is employed to position the slider secured by the slider test socket with high resolution with respect to tracks of the disc.

Abstract: A plurality of integrated circuits are inspected for their characteristics, after applying uniform stresses to the integrated circuits from common interconnections. A circuit is formed from common interconnections which are connectable in common to like electrode pads of the integrated circuits on the circuit substrate. Uniform stresses are applied from the common interconnections to the integrated circuits while the electrode pads of the integrated circuits are being connected to the common interconnections corresponding thereto. The electrode pads are disconnected from the common interconnections after the uniform stresses have been applied to the integrated circuits. The integrated circuits which have been disconnected from the common interconnections are individually inspected to determine whether the integrated circuits are acceptable or not, using the electrode pads.

Abstract: A burn-in oven is provided with a wall that has a number of vertically stacked, laterally extending slots aligned with each of the burn-in-board supports in the oven. When a burn-in-board is placed in the oven on the supports, an edge portion of the burn-in-board extends through a slot into a connector area. Each of the slots has a shutter associated therewith that will move from an open position to permit the burn-in-board connector portion to extend through the slot, to a closed position wherein the shutter covers the slot. A cam operator moves the shutters to a closed position, except when a burn-in-board is extending through a particular slot, it will support the shutter in its open position and the shutter will not be moved by the cam. All the shutters associated with openings through which no burn-in-board connector portion extends will be closed to prevent air flow from the burn-in oven.

Abstract: A semiconductor chip test system and test method thereof are provided. The system having a plurality of data input/output pins, a tester for inputting/outputting data through the plurality of data input/output pins; a plurality of semiconductor chips to be tested by the tester; a control circuit for sequentially outputting the output data from each of the plurality of semiconductor chips to the tester during a read operation and simultaneously supplying the input data from the tester to the semiconductor chips during a write operation.

Abstract: Techniques are provided for performing full N-port calibrations in an environment in which a test set is used to connect an N-port DUT to an M-port VNA, where N>M. Techniques for incorporating port impedances as part of a calibration sequence are provided. Also provided are techniques for using sequential characterization and de-embedding to generate virtual calibrations that are then used in a renormalization process.

Abstract: A device testing system that has automated test equipment (ATE), which interfaces to a device under test (DUT). The device testing system selects a test set of data including a plurality of test pairs, indicative of DUT parameter values. The system, selects a subset of the plurality of test pairs from the test set of data tests the DUT via the ATE with a portion of the selected subset based upon the test results of at least one of the test pairs.

Abstract: A self-calibrating test probe system of the present invention does not require probing head removal and replacement. Using the system of the present invention, the test probe and/or the entire system (including a testing instrument) may be calibrated or may self-calibrate while the probing head remains connected to an electrical component under test. The self-calibrating electrical testing probe system includes calibration circuitry including at least one input resistor, at least one relay, and at least one known calibration reference signal. If the test probe is an active test probe, the calibration circuitry may also include at least one amplifier. Each relay has a first position that provides signal access to a testing signal from an electrical component under test and a second position that provides signal access to the known calibration reference signal. Using the present invention, the error of the test probe and/or system is determined and compensated.

Abstract: An apparatus for testing digital and analog signals from an integrated circuit includes an adder or subtractor 17 for being supplied with an analog signal outputted from the integrated circuit of a device under test and a signal outputted from a driver 11, an integrator 14 for being supplied with an analog signal outputted from the adder or subtractor 17, a switch 22 for selectively transmitting an analog signal outputted from the integrator 14 and a digital signal outputted from the integrated circuit to the comparator 13, and a switch 24 for selectively transmitting a signal outputted from a memory 20 and a signal outputted from a comparator 13 to the driver 11. At least one of the switches 22, 24 is operated depending on whether a signal to be tested is analog or digital.

Abstract: To measure the resistance from one end of a conductor (4) to the other or between conductors, for the purpose of testing them, by establishing an electric current in the conductor, without any mechanical contact therewith, this method includes providing opposite and proximate to the conductor (4)a plate (2) that has a plurality of conductive zones (8, 10) capable of being individually taken to any adjustable electric potentials, applying a beam of particles (7) to a first point (C) of the conductor (4) to extract electrons from it, and injecting electrons at a second point (B) of the conductor (4).

Abstract: A method for evaluating a power distribution network for a circuit has steps of creating a circuit model of the circuit in which all wires and transistors are represented as circuit elements, with the model comprising a plurality of nodes. A DC power analysis is performed on the circuit model to determine voltage drops at a plurality of the nodes.

Abstract: An apparatus and method for measuring the electrical characteristics of a semiconductor device in a packaged state, which includes an electrical characteristic measurer which is connected to an electrical element whose electrical characteristics are to be measured and to one pad of the semiconductor device. The measurer is driven in response to a control signal, and outputs a value indicative of the electrical characteristics of the electrical element to the pad. The measurer includes at least an NMOS threshold voltage measurer, an NMOS saturation current measurer, a PMOS threshold voltage measurer, a PMOS saturation current measurer, and a resistance measurer. An accurate electrical characteristic value can be obtained by measuring the characteristics of the element within a semiconductor device in a finished packaged product. In view of the accurate measurement, degradation of characteristics of the semiconductor device and malfunction thereof can be prevented.

Abstract: An instrument includes a probe providing a single signal path for conveying a signal from a circuit under test to the instrument. A receiver circuit within the instrument divides the path into an analog path and a digital path. The digital path includes a comparator for determining the logic state of the signal and producing a digital representation of the signal under test. The analog path includes a multiplexer to selectively couple one of a plurality of analog input signals to an output terminal for viewing on an oscilloscope. Preferably, the probe head includes a buffer amplifier to reduce loading on the circuit under test and to increase bandwidth of the signals conveyed along the test cable to the instrument. An electrically trimmable resistor is employed to terminate the transmission line of the test cable in its characteristic impedance in order to reduce reflections and maintain transmission bandwidth.

Abstract: An electrical system includes at least one function board and at least one voltage converter. The function board and the voltage converter are connected such that a voltage generated by the voltage converter is supplied to the function board. The electrical system includes an electrical circuit for evaluating the voltage required by the function board and for controlling the voltage converter depending on the evaluated voltage.

Abstract: A test selector that multiplexes different test structures (202) to an adjacent probe pad (206) in dependence on the probe voltage. In addition, a scribeline test circuit is disclosed that includes a test selector circuit located in a single scribeline portion between two adjacent die locations. Multiple test structures and at least one probe pad also are located in the single scribeline portion. The test selector circuit makes an electrical connection from the probe pad to a selected one of the test structures depending upon a voltage applied at the probe pad.

Abstract: A pin electronics circuit for use in automatic test equipment is disclosed. The pin electronics circuit includes a pin driver having an output adapted for coupling to a device-under-test pin, and a first input. AC input circuitry couples to a pattern generator to receive pattern test signals while DC input circuitry connects to a DC parametric controller. Selector circuitry selectively couples the AC and DC input circuitry to the pin driver first input.

Abstract: A method for classifying semiconductor components by their performance characteristics includes reading an identifier associated with a component and storing, in conjunction with the identifier, first and second performances values for that component. These performance values represent the component's achieved operating speed at each of two different temperatures. The component is then allocated to a speed category on the basis of the first and second performance values.

Abstract: A disk drive unit carrier (1) is adapted to carry a single disk drive unit (2). The carrier (1) includes a temperature control device (4) for controlling the temperature of the disk drive unit (2). The temperature control device (4) is preferably in the form of an air flow control device (5,6) for controlling the flow of air across the disk drive unit (2) appropriately according to the required temperature for the disk drive unit (2).

Abstract: A memory circuit having a memory cell array in which a plurality of memory cells are provided at intersection points of a plurality of word lines and a plurality of bit line pairs and a peripheral circuit for performing an operation of selecting an address is provided with a computing circuit for generating an address signal for test; a packet decoder for designating the kind of computation to the computing circuit; and an input circuit for supplying a test signal comprising a plurality of bits for designating a test operation to the packet decoder.

Abstract: Provided is an apparatus and method used to perform automatic high potential (hi-pot), megohmeter and continuity, circuit test which includes a power source connected to a central processing unit (cpu) having a floppy drive, a hard drive, an analog to digital (A/D) printed circuit board (pcb), and a predetermined number of digital I/O pcb's, a hi-pot device, and a power supply. A data entry device is connected to the cpu for providing input thereto. A display device is provided for displaying data. A hi-pot device is connected to the A/D pcb and to a digital I/O pcb for providing an input voltage of a predetermined magnitude. A multiplexer is connected to the power supply and to a digital I/O pcb and the hi-pot device for communicating the input voltage to a predetermined number of external circuits to provide testing of the external circuits.

Abstract: A method and an apparatus for testing a plurality of driver circuits of an AMOLED before OLEDs are implanted are provided. The method and the apparatus select one specific driver circuit to be tested and dispose a conductive board above the array glass of the OLED to form a capacitor. By using the data line, the scan line, and the power line of an AMOLED, the present invention is able to input and retrieve signals from driver circuits for analyzing each of them is normal or not.

Abstract: An interconnect assembly for evaluating a probe measurement network includes a base, respective inner and outer probing areas in mutually coplanar relationship on the upper face of the base, a reference junction, and a high-frequency transmission structure connecting the probing areas and the reference junction so that high-frequency signals can be uniformly transferred therebetween despite, for example, variable positioning of the device-probing ends of the network on the probing areas. A preferred method for evaluating the signal channels of the network includes connecting a reference unit to the reference junction and successively positioning each device-probing end that corresponds to a signal channel of interest on the inner probing area.

Abstract: A semiconductor device testing apparatus, system, and method, in particular for testing the contacting with semiconductor devices positioned one upon the other, wherein at least two semiconductor devices are provided that are connected to a device module, at least one pin of a first semiconductor device is conductively connected with a pad, and at least one pin of a second semiconductor device also is to conductively connected with the pad. A first value is written into a memory cell of the first semiconductor device, a second value differing from the first value is written into a memory cell of the second semiconductor device, and a signal corresponding to the first value at the pin of the first semiconductor device and of a signal corresponding to the second value at the pin of the second semiconductor device is simultaneously output.

Abstract: A method and apparatus are provided for testing linearity of two or more programmable delay chains in an integrated circuit. A first delay chain is successively programmed to a first sequence of delay settings and, for each delay setting in the first sequence, a second delay chain is successively programmed to a second sequence of delay settings. The second sequence sweeps a propagation delay through the second delay chain from a delay value less than a present propagation delay through the first delay chain to a delay value greater than the present propagation delay. For each delay setting of the second delay chain, a logic transition is applied to inputs of the first and second delay chains and the output of one of the first and second delay chains is latched as a function of the output of the other of the first and second delay chains to produce a sample value.

Abstract: In a testing board (300C), one end of each of a plurality of first wirings (310) and one end of each of a plurality of second wirings (320) are connected to a common point (340). The other end of each of the second wirings (320) is connected to a terminal (12a-12f) of a semiconductor device (10) under test. The second wirings (320) have almost the same length. Signals outputted from drivers of a tester pin (130) to the first wirings (310) are composed at the common point (340), and the composite wave is inputted to the terminal (12a-12f) through each of the second wirings (320). A relay (350) is provided at a midpoint of each of the second wirings (320) and is controlled such that the signals can be inputted to, for example, the terminal (12b) from the driver of the tester pin (130) through one of third wirings (330).

Abstract: In order to provide an output voltage adjustment circuit which is able to perform the screening of the semiconductor integrated circuit mounted as the bear chip status on the circuit board, and to plan reduction of the mounting area size and improvement of the electrical characteristic nature and reduction of the manufacturing cost by a simple constitution thereof, an engine control device having a control device of the integrated circuit of the arithmetic processing unit for operating the control program, is provided, and said engine control device has an output voltage adjustment circuitry to switch the rated voltage to screen the integrated circuit, and said output voltage adjustment circuitry has plural resistors between the output side power line of the rated voltage and the gland sides.

Abstract: A test circuit receives a plurality of internal test signals and delivers a group of the plurality of internal test signals onto a bus during an idle state of the bus. The bus is coupled to output pins so that the group of internal test signals can be used in debugging operations. The test circuit may include a multiplexing circuit that receives the plurality of internal test signals as inputs and that delivers a selected group of the internal test signals as outputs. The test circuit may also include a switch that couples the selected group of the internal test signals onto the bus during an idle state.

Abstract: A cable suitable for detecting the presence of corrosive liquids is disclosed. In an embodiment the cable includes two sensing wires wrapped around a core member, at least one of the sensing wires being surrounded by a non-conductive surface layer. In an alternate embodiment the cable includes two sensing wires wrapped around a core member, the sensing wires and core member being encapsulated by a non-conductive surface layer. Preferably, the cable includes insulating wires for detecting the location of a leak. When a corrosive liquid contacts the sensing wires of the cable an electrical connection is created between them.

Abstract: A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor.

Abstract: The present invention provides a method and system for generating a distinct signature of electronic components that is compared to a known signature for identification and verification of the electronic component. The component signature is displayed on an alpha-numeric display for viewing by the user, or can be used as a pointer in a look-up table for displaying a string of text corresponding to the signature. In a digital generation method, a test sequence is executed, wherein a predetermined combination of logic levels are applied to the pins of a component. The logic levels applied to each pin are then compared to their respective feed-back logic levels. The sum of all the differences between the feed-back logic levels and the applied logic levels at the end of the test sequence is used in generating a signature. In an analog generation method, values calculated as a function of the waveform response of the component are used to generate a signature for the component.

Abstract: The invention relates to an arrangement for testing an integrated circuit (1; 21). In order in this case to avoid a test vector memory and an on-board test system, a data word generator (2; 22), which supplies deterministic data words, means (3, 4, 5, 6; 22, 23, 24, 25, 26, 27) for test pattern generation, which modify the deterministic data words such that prescribed test patterns are produced which can be fed to inputs of an integrated circuit (1; 21) to be tested, and comparison means (12; 30) for comparing test output patterns of the integrated circuit (1; 21) with desired output patterns.

Abstract: A tester for testing a digital device. The tester includes a plurality of time measurement units to measure transition timing values of output data of each output pin of the digital device in each test cycle. A plurality of result operations units performs real-time arithmetic operations on the measured transition timing values to produce a pass/fail result and additional test results. A plurality of result accumulators stores the pass/fail result and a number of selected test results. And a capture/analysis engine captures and analyzes the pass/fail result and the selected results to provide comprehensive test performance of the digital device.

Abstract: The invention provides a structure that does not employ complicated and large-scale control circuits or control memory, minimizes the circuits for real time processing, and allows the use of refresh memory. The invention provides a test clock (8-1) comprising a data processing apparatus (1-1) provided for each electrode pin of the measured device (11), a memory (2-1) that carries out reading and writing of the test pattern data and the like, a first-in-first-out element (4-1) that executes queue processing of the data read out from the memory, a delay circuit (5-1) that delays the output signal of the first-in-first-out element, and a measured device driver (6-1) that inputs into the electrode pin the output signal of the delay circuit, and in which the data processing apparatus (1-1) of adjacent test blocks are connected into a loop via the input-output circuit (3-1).

Abstract: A wafer-level package includes a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit each provided with test chip terminals and non test chip terminals, at least one external connection terminal, at least one redistribution trace provided on the semiconductor wafer, at least one testing member, and an insulating material. A first end of the redistribution trace is connected to one of the test chip terminals and a second end of said redistribution trace is extended out to a position offset from the chip terminals. The testing member is provided in an outer region of the semiconductor chip circuit forming region, and the second end of the redistribution trace is connected to the testing member.

Abstract: A system and method for testing an integrated circuit (IC) by transient signal analysis includes a comparison circuit that is configured to generate a comparison signal from an IC transient signal and a reference signal. Circuitry operationally coupled to the comparison circuit manipulates the comparison signal to generate a first output waveform area indicative of an absolute area of positive and negative portions within the comparison signal. The comparison circuit and the circuitry may include seven operational-amplifiers (op-amps) or ten op-amps. As a further processing sequence, a second output waveform area that is indicative of an absolute area of positive and negative portions within a second comparison signal is generated. In one embodiment, a first value representing the first waveform area and a second value representing the second waveform area are plotted to determine if the plotted X-Y coordinate falls within a predefined standard for determining the pass/fail status of the IC.