Abstract: A driver and receiver circuit includes at least one output terminal for connecting a line connection. The circuit further includes a voltage supply arrangement connected to the at least one output terminal and a current measuring arrangement connected to the at least one output terminal. The current measuring arrangement is designed to detect a current at the at least one connecting terminal and to generate a current measurement signal dependent on said current. The driver and receiver circuit further includes a control circuit, to which the current measurement signal is fed, and at least one monitoring circuit. The monitoring circuit is designed to detect the current at the at least one connecting terminal and to output an error signal if the current lies above a predetermined threshold value for a time duration which is longer than a predetermined first time duration.

Abstract: A simulated battery test device and method that is capable of testing a battery charging circuit and logic circuit to determine proper operation. An operational amplifier is used that can both source and sink current to simulate the operation of the battery. A battery low signal can be generated using the simulated battery test device to test a battery charging circuit and logic circuit in a battery low condition. In addition, a battery open signal can be generated to test the battery charging and logic circuit in a battery open condition. Charging currents are detected to determine if currents fall within an acceptable range.

Abstract: A system and method for testing devices. The system includes a plurality of pads and a decoder coupled to a plurality of devices. The decoder is configured to receive a plurality of selection signals from the plurality of pads and select a device from the plurality of devices based on at least information associated with the plurality of selection signals. Additionally, the system includes one or more pads connected to the selected device. At least one of the one or more pads is not connected to any of the plurality of devices other than the selected device. The one or more pads are used for testing the selected device.

Abstract: An integrated circuit has an analog output circuit for outputting an analog signal and a leadless terminal for connecting an output line of the analog output circuit to a circuit board by soldering, and measures and transfers an analog output voltage of the leadless terminal in a state in which it is mounted on the circuit board. A measuring unit has a switching unit for connecting the analog output circuit to the measuring unit upon failure diagnosis, and an AD converter for measuring the analog output voltage of the leadless terminal in a failure diagnosis state obtained by the switching unit; and causes the analog output voltage of the leadless terminal to be determined whether it is a normal voltage or an abnormal voltage by transferring the voltage measured by the AD converter to a determination unit through serial transfer.

Abstract: A system and method for providing increased manufacturing yield for integrated circuits. Various aspects of the invention may comprise receiving an integrated circuit designed to operate at nominal power supply characteristics. The integrated circuit may, for example, be tested at nominal power supply characteristics to determine if the integrated circuit meets performance requirements at nominal power supply characteristics. If the integrated circuit meets performance requirements at nominal power supply characteristics, then the integrated circuit may designated as such and further processed accordingly. Such a designation may, for example be visible, electronic or procedural. Various aspects of the present invention may also comprise testing the integrated circuit at non-nominal power supply characteristics to determine if the integrated circuit meets performance requirements at non-nominal power supply characteristics.

Abstract: A method for testing the integrity of a memory with defective sections under a plurality of operating environments includes testing the memory with defective sections under a plurality of operating environments, recording results of each operating environment test, and comparing the results of the tests. If the results of are the same, the memory with defective sections is declared to have integrity. If not, the memory with defective sections is declared to not have integrity.

Abstract: A voltage/current (V/I) source includes circuitry having first, second, third and fourth nodes, a first current source electrically connected to the first node, a second current source electrically connected to the second node, where the third and fourth nodes are between the first and second nodes, and an operational amplifier (op-amp) having an output, an inverting input, and a non-inverting input. The output is electrically connected to the third node, and the non-inverting input is electrically connected to a voltage source. A feedback line is between the fourth node and the inverting input.

Abstract: A method for testing a semiconductor device incorporating a controller, which generates first and second complementary signals, and a memory, which operates in accordance with the first and second complementary signals. The method includes selectively switching the first and second complementary signals to an intermediate potential signal having an intermediate potential of the complementary signals. The method further includes conducting an operational test on the second device with the first and second complementary signals and the intermediate potential signal. This method enables detection of a defective connection between the devices.

Abstract: A system and method for testing a Link Control Card (LCC) of a storage device includes a host, a middle plane (MP), a switch, and a testing device array. The host is connected to the testing device array for sending out command sets and receiving results. The MP is connected between the LCC and the testing device array. The switch determines the LCC to output hard reset signals and the hard reset signals are transferred to the testing device array via the MP. The testing device array includes a plurality of testing devices, and each of the testing devices includes a micro-controller unit (MCU); a connector being connected to the MCU, and coupled to the MP; an address setting unit being connected to the MCU, for setting an unique address of each of the testing devices; and a first interface being connected to the MCU for outputting results.

Abstract: A method for testing a system module assembled by integrated circuits during mass production. The integrated circuits and the assembled system modules are manufactured by the same manufacturer. The method includes the steps of apply a plurality of system level tests to the system module to determine the performance of the system module. Next, verify the performance of the integrated circuits based on the results of the system level tests. Finally, perform integrated circuit level tests, wherein the integrated circuit level tests include test items unverifiable by the system level tests. The present invention also includes a testing apparatus for testing a system module.

Abstract: One embodiment of the present invention includes a method for reactively cleaning a contact mechanism. The method includes measuring contact resistance (CRES) associated with a plurality of electrical contacts of the contact mechanism. The method also includes generating at least one statistic of the measured CRES associated with the plurality of electrical contacts of the contact mechanism, and comparing the at least one statistic of the CRES associated with the plurality of electrical contacts of the contact mechanism with at least one CRES threshold parameter associated with an unacceptable level of CRES. The method further includes cleaning the plurality of electrical contacts of the contact mechanism based on the comparison of the at least one statistic of the CRES and the at least one CRES threshold parameter.

Abstract: An instrument is configured to coordinate execution of a plurality of experiments employing a plurality of source measurement units (SMU's) to characterize a plurality of devices under test (DUT's). Each experiment controller, of a plurality of experiment controllers, is configured to manage one of the plurality of experiments by, at least in part, controlling the SMU's allocated to that experiment. A main controller is configured to interoperate with a host to manage the experiment controllers. For example, the instrument may be configured to provide experiment parameters to the SMU's prior to execution of the experiments. In one aspect, the main controller is configured to receive experiment parameters from a host controller external to the instrument. At least in part based on the received experiment parameters, the main controller configure which experiment controllers are to manage which experiment.

Abstract: The present invention is a method and an apparatus for detecting dependability vulnerabilities in production IT environments. In one embodiment, a method for detecting a dependability vulnerability in a production IT environment includes injecting a synthetic disturbance into the production IT environment and observing the response of the production IT environment to the synthetic disturbance.

Abstract: Disclosed is a method of wafer/probe testing of integrated circuit devices after manufacture. The invention begins by testing an initial group of devices (e.g., integrated circuit chips) to produce an initial failing group of devices that failed the testing. The devices in the initial failing group are identified by type of failure. Then, the invention retests the devices in the initial failing group to identify a retested passing group of devices that passed the retesting. Next, the invention analyzes the devices in the retested passing group which allows the invention to produce statistics regarding the likelihood that a failing device that failed the initial testing will pass the retesting according to the type of failure. Then, the invention evaluates these statistics to determine which types of failures have retest passing rates above a predetermined threshold. From this, the invention produces a database comprising an optimized retest table listing the types of defects that are approved for retesting.

Abstract: Special test measures are required to test an asynchronous timing circuit. The asynchronous timing circuit (14) comprises a time-continuous feedback loop (22, 26) with a combinatorial logic circuit (22) with inputs for a feedback signal and a further signal, the feedback loop having positive loop gain. A test prepared circuit that contains the timing circuit is switched to a test mode. In the test mode test data through is shifted through a shift register structure (12). The further input signal of the feedback loop is controlled dependent on test data from the shift register structure (12). The time-continuous feedback loop (22, 26) is initially broken in the test mode, substituting test data from a register (31) in the shift register structure (12) for a feedback signal. Subsequently the time-continuous feedback loop is restored in the test mode after the further signal has stabilized.

Abstract: Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between an automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher clock frequency than the automated testing equipment is configured to operate. In order to do so, the testing interface includes components configured for generating addresses and test data to be provided to the integrated circuit. A variety of test data patterns can be produced and the test data can be address dependent.

Abstract: According to one embodiment of the invention, a method for early qualification of semiconductor device includes performing initial testing on a semiconductor device, receiving fail data on the semiconductor device, determining a solution model for the semiconductor device based on the fail data, storing the solution model, performing subsequent testing on the semiconductor device, and comparing a result of the subsequent testing to the solution model.

Abstract: An apparatus for automatically inserting connectors and coupling test probes to circuit boards, such as computer system boards and the like. The apparatus enables connectors to be automatically inserted into mating connectors on a circuit board device under test (DUT). Connectors may be automatically inserted along 1-4 axes. The apparatus includes replaceable probe/connector plates that are DUT-type specific, as well as DUT-type specific side access units. The apparatus may also be used for inserting memory devices and microprocessors, and further enables peripheral devices to be operatively coupled to expansion bus connectors on the DUT. In one embodiment, a single actuator is employed to actuate up to four insertion axes simultaneously.

Abstract: A programmable system for testing relays and controlling systems is provided. In one embodiment the present disclosure provides a programmable device capable of, for example, testing relays. The device includes a signal generator for generating signals to test relays. The device includes a memory location, and a first program stored in the memory location. The first program supports relay testing. The device includes a versioned program to support relay testing, and a processor in communication with the signal generator and the memory location. The device also includes a routine that is operable by the processor to install a versioned program in the memory location replacing the first program.

Abstract: An electronic device for use with a probe head in automated test equipment. The device includes a plurality of semiconductor devices arranged to provide at least one driver/receiver pair where the driver portion of the driver/receiver pair is configured to transmit a signal to at least one device under test and the receiver portion of the driver/receiver pair is configured to receive a signal from the at least one device under test. Each of the plurality of semiconductor devices is fabricated using either a silicon-on-insulator (SOI) or metal-on-insulator (MOI) technology and has a thickness less than about 300 ?m exclusive of any electrical interconnects. The at least one driver/receiver pair is adapted to mount directly to the probe head.

Abstract: The present invention discloses a system for synchronously controlling the testing of pluralities of devices, comprising a server, a switch coupled to the server, and a testing instrument coupled to the server. Pluralities of computers are coupled to the server respectively, wherein the pluralities of devices are respectively connected to the pluralities of computers and the switch under testing. The parameters of the pluralities of devices include a first type test item that is testable by the pluralities of computers, and a second type test item that is testable by the testing instrument. The switch includes a RF switch. The server is connected to the testing instrument by a GPIB cable (or other instrument control interface and the server is connected to the pluralities of computers via local area network (LAN) such as Ethernet.

Abstract: An apparatus to compensate for loss in a transmission path includes a circuit block that incorporates time constants into a signal transmitted via the transmission path. The time constants counteract at least part of inherent time constants that contribute to loss in the transmission path. The circuit block includes a resistive circuit and a capacitive circuit. The capacitive circuit and the resistive circuit together contribute to the time constants. The capacitive circuit includes plural capacitors that are each switchable via the circuit block. An amount of compensation provided by the apparatus corresponds, at least in part, to the loss in the transmission path.

Abstract: Electronic component validation testing is facilitated by a method, system and program product which allows the importation of virtual signals derived from simulation verification testing of the electronic component design into electronic test equipment employed during validation testing of the actual electronic component.

Abstract: A circuit component tester includes a portable casing and a circuit provided within the casing. A plurality of leads are provided to electrically connect the circuit to a gate and two terminals of a circuit component under test. A test switch provided on the casing initiates application of test voltage to at least one of the two terminals of the circuit component under test. A gate switch provided on the casing initiates application of gate voltage to the gate of the circuit component under test. At least one of the test switch and the gate switch are operable to verify functionality of the circuit component under test.

Abstract: A measurement apparatus for FET characteristics comprises a divider connected to a pulse generator for dividing pulses from the pulse generator into first and second pulses; a first SMU; a first switch for selecting pulses from the divider or voltage from the first SMU; a terminal resistor for applying signals from the first switch and supplying the signals to the first terminal of the device under test; a second and a third SMU; a bias-T connected to the third SMU; a second switch for selecting to connect the second terminal of the device under test to the second SMU or to connect the second terminal to signals of the bias-T obtained by multiplexing the voltage from the third SMU; and voltage measurement unit connected to the divider and the bias-T.

Abstract: A wafer-level package includes a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit each provided with test chip terminals and non test chip terminals, at least one external connection terminal, at least one redistribution trace provided on the semiconductor wafer, at least one testing member, and an insulating material. A first end of the redistribution trace is connected to one of the test chip terminals and a second end of said redistribution trace is extended out to a position offset from the chip terminals. The testing member is provided in an outer region of the semiconductor chip circuit forming region, and the second end of the redistribution trace is connected to the testing member.

Abstract: A nuclear reactor plant protection system printed circuit card comprises a first logic device having a number of basic logic circuits, and a second logic device operatively connected with the first logic device for testing the number of basic logic circuits without taking the printed circuit card out of service. A nuclear reactor plant protection system printed circuit card comprises a first logic device producing a first output signal in response to a test signal, a second logic device producing a second output signal in response to the test signal, and a comparator for comparing the first output signal and the second output signal, wherein the test signal has a pulse duration that is less than a latching period associated with the printed circuit card. A method of testing and a nuclear reactor control system incorporating the nuclear reactor plant protection system printed circuit card is also provided.

Abstract: The invention relates a method for testing a batch of electrical components like Integrated Circuits, the method involving applying a first test (6) on each electrical component from the batch; and applying a second test (12) on electrical components that have failed the first test (6). Advantageously, the second test (12) is applied directly after the first test (6). Preferably, the first test (6) includes a functional test, and the second test (12) includes a Contact-and-Short-Circuit test.

Abstract: According to an aspect of the present invention, multiple scan enable signals (controlling corresponding scan chains) are used in an integrated circuit, and the scan chains are placed in evaluation mode in non-overlapping durations between scan-in and scan-out operations. In an embodiment, a single clock signal drives the elements in both the scan chains, and the start and end of the non-overlapping durations are timed associated with the edges of the pulses of the clock signal. Multiple pulses of the clock signal may be used between the scan-in and scan-out. According to another aspect of the present invention, the scan elements are conveniently connected to different scan enable signals to take advantage of the non-overlapping durations.

Abstract: A test apparatus includes one handler connected to a tester and one test board divided into two or more sites or two or more test boards. Since only the sites on the test board (or test boards) need be duplicated, rather than the loading lanes or sorters of the handler, the test apparatus can be conveniently compact. Further, while testing semiconductor devices on one site or one test board, semiconductor devices in another site or on another test board can be sorted according to the test result. This enables the reduction or elimination of tester idle time to optimize the efficiency of the test apparatus.

Abstract: An electronic circuit having an input, an output with an input filter for delaying a change of an input signal and a control component for supplying an output signal and evaluating the input signal. The delay is a time constant. An industrial automation system is provide with the electronic circuit and a fail-safe component connected to an input and an output of the circuit. To increase the probability of detecting errors in the electronic circuit, the control component is provided for supplying a test signal for output through the output, for making a first evaluation of the input signal to be provided immediately after the output of a test signal and for making a second evaluation of the input signal after expiry of a time after output of the test signal which at least corresponds to the time constant. A method for testing an electronic circuit is also provided.

Abstract: A semiconductor testing apparatus, includes a test signal generating unit that generates a test signal corresponding to a test pattern to output the generated test signal to a device under test (DUT); a comparison signal generating unit that generates a comparison signal by combining a reference signal and the test signal; and a comparing unit that compares a response signal, which is output from the DUT in response to the input of the test signal, and the reference signal by offsetting the test signal contained in a composite signal of the test signal and the response signal and the test signal contained in the comparison signal. The DUT is determined to be defective or not based on a result of comparison by the comparing unit.

Abstract: A testing device for testing a printed circuit board includes a testing signal converting module for receiving testing signals from the printed circuit board and outputting the testing signals and a plurality of I/O control signals to a plurality of testing circuits. The testing signals include a BIOS signal, an audio signal and a floppy signal. A BIOS testing and upgrading circuit test the BIOS signal from the printed circuit board according to a first control signal and updating the BIOS according to a sixth control signal. An audio testing circuit for testing audio quality includes a line out/line in circuit for an output/input test, a hp-mic circuit for a headphone and microphone test and a speaker-cd-in circuit for a speaker/cd test. A floppy switching circuit tests a read/write function and a write-protect function of a floppy signal according to a fifth I/O control signal.

Abstract: A sequential control circuit operates according to an input signal. When the input signal is determined at a first state, the sequential control circuit asserts a plurality of control signals in a predetermined sequence. When the input signal is determined at a second state, the sequential control circuit de-asserts the plurality of control signals in a sequence reverse to the predetermined sequence.

Abstract: Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between an automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher clock frequency than the automated testing equipment is configured to operate. In order to do so, the testing interface includes components configured for generating addresses and test data to be provided to the integrated circuit. A variety of test data patterns can be produced and the test data can be address dependent.

Abstract: A system is provided for controlling the delay in an isolation buffer. Multiple such isolation buffers are used to connect a single signal channel to multiple lines and controlled to provide an equal delay. Isolation buffer delay is controlled to be uniform by varying either power supply voltage or current. A single delay control circuit forming a delay-lock loop supplies the delay control signal to each buffer to assure the uniform delay. Since controlling delay can also vary the output voltage of each isolation buffer, in one embodiment buffers are made from two series inverters: one with a variable delay, and the second without a variable delay providing a fixed output voltage swing. To reduce circuitry needed, in one embodiment an isolation buffer with a variable power supply is provided in a channel prior to a branch, while buffers having a fixed delay are provided in each branch.

Abstract: By mounting, on a semiconductor integrated circuit, a clock stability waiting circuit 4 for deciding whether a clock signal generated by a high speed clock generating circuit 2 is stable or not, a scan pass control circuit 7 capable of switching a scan pass structure based on a signal output from the clock stability waiting circuit 4 and an activation control circuit 6 capable of switching an order circuit to be activated based on the signal output from the clock stability waiting circuit 4, it is possible to carry out a parallel test in a stability waiting time having a high speed clock. Moreover, it is possible to externally monitor a signal capable of deciding a stability of a high speed clock. Therefore, it is easy to decide whether a failure is caused by a high speed clock generating portion or an internal circuit.

Abstract: A testing device that tests an electronic device includes a test pattern outputting unit operable to output a test pattern to the electronic device, a deciding unit operable to decide whether an output signal from the electronic device satisfies a predetermined condition, an instruction storing unit operable to store a plurality of instruction codes, a first instruction pipeline operable to generate a condition satisfaction instruction stream including a plurality of instructions that causes the test pattern outputting unit to output the test pattern to be supplied to the electronic device when the output signal satisfies the condition based on the plurality of instruction codes, a second instruction pipeline operable to generate a condition non-satisfaction instruction stream including a plurality of instructions that causes the test pattern outputting unit to output the test pattern to be supplied to the electronic device when the output signal does not satisfy the condition based on the plurality of instru

Abstract: A testing method of a semiconductor integrated circuit device includes a testing step of conducting a functional test by supplying test pattern data to a semiconductor integrated circuit device mounted upon a testing apparatus, and a post processing step conducted after the testing step for continuously driving the semiconductor integrated circuit device by supplying dummy test pattern to the semiconductor integrated circuit device, wherein the test pattern data is supplied with a first system clock speed while the dummy test pattern data is supplied with a second, slower system clock speed, the post processing step switching a system clock speed of the testing apparatus from the first system clock speed to the second system clock speed at the same time as finishing of the testing step.

Abstract: A system and method for testing devices. The system includes a plurality of pads and a decoder coupled to a plurality of devices. The decoder is configured to receive a plurality of selection signals from the plurality of pads and select a device from the plurality of devices based on at least information associated with the plurality of selection signals. Additionally, the system includes one or more pads connected to the selected device. At least one of the one or more pads is not connected to any of the plurality of devices other than the selected device. The one or more pads are used for testing the selected device.

Abstract: An interconnect assembly for evaluating a probe measurement network includes a base, respective inner and outer probing areas in mutually coplanar relationship on the upper face of the base, a reference junction, and a high-frequency transmission structure connecting the probing areas and the reference junction so that high-frequency signals can be uniformly transferred therebetween. A preferred method for evaluating the signal channels of the network includes connecting a reference unit to the reference junction and successively positioning each device-probing end that corresponds to a signal channel of interest on the inner probing area.

Abstract: A voltage verification unit and method for determining the absence of potentially dangerous potentials within a power supply enclosure without Mode 2 work is disclosed. With this device and method, a qualified worker, following a relatively simple protocol that involves a function test (hot, cold, hot) of the voltage verification unit before Lock Out/Tag Out and, and once the Lock Out/Tag Out is completed, testing or “trying” by simply reading a display on the voltage verification unit can be accomplished without exposure of the operator to the interior of the voltage supply enclosure. According to a preferred embodiment, the voltage verification unit includes test leads to allow diagnostics with other meters, without the necessity of accessing potentially dangerous bus bars or the like.

Abstract: The invention relates to a test apparatus for testing semi-conductor components, and to a signal testing procedure, to be used especially during the testing of semi-conductor components. A signal is applied to a connection of a semi-conductor component, a reference signal is applied at a particular voltage level to a further connection of the semi-conductor component, the signal is compared with the reference signal, the voltage level of the reference signal is changed, and the signal is compared with the reference signal.

Abstract: Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between an automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher clock frequency than the automated testing equipment is configured to operate. In order to do so, the testing interface includes components configured for generating addresses and test data to be provided to the integrated circuit. A variety of test data patterns can be produced and the test data can be address dependent.

Abstract: A measurement device includes a measurement circuit that generates a parametric measurement data signal including parametric characteristics of an input signal. In an exemplary embodiment, the parametric characteristics are measured at predetermined increments of time. A population limit analyzer is coupled to the measurement circuit and generates limit data in response to the parametric measurement data signal. A measurement limit checker is coupled to the population limit analyzer and generates a signal indicating that the characteristics of the parametric measurement data signal is within acceptable limits. With this information, the user is able to quickly grade a selected device under test (DUT). A device performance measurement method includes receiving an input signal. Next, statistical characteristics are determined from the parametric measurements of the input signal. Performance limits are extrapolated from the statistical characteristics of the parametric measurements.

Abstract: An apparatus for testing electronic devices employs a programmable device to adjust the timing of the strobes such that the strobes sample the bit stream from a device under test at or near the center of the bit position. The strobe time adjustment is performed based on pairs of strobe readings made around a number of different bit positions. The programmable device examines the pairs of strobe reading made around each of the different bit positions to determine whether or not a bit transition has occurred there. The programmable device selects the bit positions around which a bit transition has not occurred as eye candidates, and defines the center of the largest contiguous region of eye candidates as the center of the bit position.

Abstract: A handheld portable battery powered digital antenna and/or network analyzer which derives complex impedance values at a given frequency includes an internal direct digital synthesis generator and provides software-defined multiple operating modes and real time graphic scalar and polar displays of results in a multiplicity of user-selectable visual formats.

Abstract: A test and measurement instrument such as a Logic Analyzer, or the like, has at least one Reloadable Word Recognizer whose reference value can be loaded by a trigger machine with a current acquired data sample while data is being acquired. In a second embodiment useful for performing memory testing, the reloadable word recognizer is used in cooperation with two conventional word recognizers. In a third embodiment, a delay unit is employed to provide delayed input data words as reference words. In a fourth embodiment, an offset register and adder are used to modify the input data words before storing them. A fifth embodiment provides for substantially immediate use of base addresses of relocatable subroutines and stack-based variables recovered from a data stream acquired from a system under test.

Abstract: Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between an automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher clock frequency than the automated testing equipment is configured to operate. In order to do so, the testing interface includes components configured for generating addresses and test data to be provided to the integrated circuit. A variety of test data patterns can be produced and the test data can be address dependent.

Abstract: A system and method for providing increased manufacturing yield for integrated circuits. Various aspects of the invention may comprise receiving an integrated circuit designed to operate at nominal power supply characteristics. The integrated circuit may, for example, be tested at nominal power supply characteristics to determine if the integrated circuit meets performance requirements at nominal power supply characteristics, if the integrated circuit meets performance requirements at nominal power supply characteristics, then the integrated circuit may be designated as such and further processed accordingly. Such a designation may, for example be visible, electronic or procedural. Various aspects of the present invention may also comprise testing the integrated circuit at non-nominal power supply characteristics to determine if the integrated circuit meets performance requirements at non-nominal power supply characteristics.