Abstract: A system and method for providing increased manufacturing yield for integrated circuits. Various aspects of the invention may comprise receiving an integrated circuit designed to operate at nominal power supply characteristics. The integrated circuit may, for example, be tested at nominal power supply characteristics to determine if the integrated circuit meets performance requirements at nominal power supply characteristics, if the integrated circuit meets performance requirements at nominal power supply characteristics, then the integrated circuit may be designated as such and further processed accordingly. Such a designation may, for example be visible, electronic or procedural. Various aspects of the present invention may also comprise testing the integrated circuit at non-nominal power supply characteristics to determine if the integrated circuit meets performance requirements at non-nominal power supply characteristics.

Abstract: A semiconductor device tester includes a parametric measurement unit (PMU) stage for producing a DC test signal and a pin electronics (PE) stage for producing an AC test signal to test a semiconductor device. A driver circuit is capable of providing a version of the DC test signal and a version of the AC test signal to the semiconductor device.

Abstract: Disclosed is a method and system for testing integrated circuit devices after manufacture wherein, an initial group of devices is tested to produce an initial failing group of devices that failed the testing. The devices in the initial failing group are identified by type of failure. Then, the devices in the initial failing group are retested to identify a retested passing group of devices that passed the retesting. Next, the devices in the retested passing group are analyzed to produce statistics regarding the likelihood that a failing device that failed the initial testing will pass the retesting according to the type of failure. Then, these statistics are evaluated to determine which types of failures have retest passing rates above a predetermined threshold. From this, a database is produced that includes an optimized retest table listing the types of defects that are approved for retesting.

Abstract: Disclosed herein is an improved serializer/deserializer (SERDES) circuit (102) having built-in self-test capabilities that is configured to perform an in-situ jitter sensitivity characterization of the clock and data recovery (CDR) circuit (108). To that end, a delay perturbation is added to the serial data stream at the serializer (120) output, typically using a variable delay (DEL) line (116). Then, the perturbed serial data stream is looped back to the CDR circuit. A dedicated circuit in the control logic (112) coupled to the DEL line and the deserializer circuit (110) analyzes the recovered data to characterize the sensitivity of the CDR circuit to the jitter frequency. By continuously modifying the output delay of said serial data stream, i.e. the amplitude and the frequency of the perturbation, one can generate a perturbed serial data stream, very close to the real jittered data.

Abstract: A method for testing a semiconductor device incorporating a controller, which generates first and second complementary signals, and a memory, which operates in accordance with the first and second complementary signals. The method includes selectively switching the first and second complementary signals to an intermediate potential signal having an intermediate potential of the complementary signals. The method further includes conducting an operational test on the second device with the first and second complementary signals and the intermediate potential signal. This method enables detection of a defective connection between the devices.

Abstract: A passive matching network is connected to an input/output line for an automatic test equipment drive channel to compensate for capacitances associated with a receiver circuit connected to the line, and also an optional current-mode driver circuit. The matching circuit preferably comprises a T-coil circuit that can include a bridging capacitor; separate T-coil circuits can be provided to separately compensate for receiver circuit and current-mode driver circuit capacitances. The driver and receiver circuits can be implemented on a common layer of an integrated circuit, with the T-coil windings implemented in a separate layer of the same integrated circuit that is spaced from the common layer by at least one dielectric layer.

Abstract: A programmable system for testing relays and controlling systems is provided. In one embodiment the present disclosure provides a programmable device capable of, for example, testing relays. The device includes a signal generator for generating signals to test relays. The device includes a memory location, and a first program stored in the memory location. The first program supports relay testing. The device includes a versioned program to support relay testing, and a processor in communication with the signal generator and the memory location. The device also includes a routine that is operable by the processor to install a versioned program in the memory location replacing the first program.

Abstract: A semiconductor device having a plurality of circuits with the same configuration, wherein since expected values in the number corresponding to the number of circuits are not required, operation tests are effectively performed in a short time. The semiconductor device has first, second and third digital filters with the same configuration. To test these digital filters, comparison circuits comparing an output value and an expected value are individually provided per one digital filter. The digital filters and the comparison circuits are daisy-chained such that the output values of the first and second digital filters are input as the expected values of the comparison circuits corresponding to the second and third digital filters, respectively. When the same test signal is input to each digital filter from a built-in self test (BIST) controller, abnormal circuits can be detected based on comparison results of the comparison circuits.

Abstract: A system for testing electronic modules comprising at least one mapping board box, and at least one harness operably attached to the mapping board box with a harness port is disclosed. The mapping board box comprises pin receptors, wherein the receptors are in communication with a pinned circuit board to comprise a system for testing electronic modules. The mapping board box is pre-wired to receive circuit boards with a variety of pin configurations.

Abstract: A functionality test method for a technical system having at least one technical component to be regularly tested. The method including the steps of defining a test interval by setting a minimum time interval and a maximum time interval between two successive tests of the technical component, defining a test range for a decision parameter, sensing an actual value of the decision parameter, and performing a functionality test of the technical component if the minimum time interval between two successive tests of the technical component has elapsed and the sensed actual value of the decision parameter is within the predefined test range, or the maximum time interval between two successive tests of the technical component has elapsed.

Abstract: Embodiments of the invention connect a plurality of devices under test (DUTS) in a parallel manner and a high test current is selectively applied to each DUT. The apparatus to test a plurality of DUTs includes a plurality of power sources providing the test current to a plurality of DUTs; and switching devices connected to the respective DUTs and power sources and selectively providing the test current. In addition, the apparatus has at least one control unit to control the switching devices. Furthermore, a group of DUTs from the plurality of DUTs is connected between two of the plurality of power sources in a parallel manner, and the test current is selectively provided to one DUT from the group of DUTs according to the operation of the switching devices.

Abstract: A method and apparatus enabling the analog and digital triggering of a signal analysis device such as a Logic Analyzer, wherein separate analog and digital signal paths provide separate analog and digital processing of an input test signal for enabling the triggering of a signal analysis device upon analog and digital signal conditions.

Abstract: The invention is directed to an integrated circuit that includes a plurality of functional circuit blocks. Respective associated multiplexers are used to change over between a normal mode and a test mode. The input side of the multiplexers each have a test register connected thereto which is coupled to a serial bus. A control unit controls the transfer of test data to a selected function block on the basis of the state of a mode-of-operation memory cell in the respective test register. This means that there is little involvement required to put individual function blocks of a chip deliberately into a test mode and to program them as appropriate, while other function blocks are operating in normal mode. The principle described allows a high degree of flexibility with regard to the testing of integrated circuits with a multiplicity of functional assemblies.

Abstract: According to one embodiment a system is disclosed. The system includes a tester having a power supply, an integrated circuit device under test (DUT) and a transient compressor (TC) coupled between the tester and the power supply to stabilize power delivered to the DUT by injecting current into the path between the power supply and the DUT.

Abstract: A method and system for dynamic characterization observability using functional clocks for system or run-time process characterization. Silicon characterization circuitry may be read after silicon chips have been assembled in a package and installed in a system. A characterization circuit comprising one or more oscillators generates signal pulses, wherein the signal pulses represent a frequency of a circuit in the processor chip. A sampler circuit is connected to the characterization circuit, wherein the sampler circuit counts the number of the signal pulses from the characterization circuit within a predetermined time period. A control unit is connected to the sampler circuit, wherein the control unit comprises macros for collecting count data from the one or more oscillators to determine the silicon characterization. Based on the silicon characterization, the optimal operating frequency of the processor chip may be identified, as well as possible lifetime degradation of circuits on the chip.

Abstract: A disk drive unit mounting device is adapted to carry one or plural disk drive units. The mounting device includes a temperature control module and a carrier module secured together y a releasable fastener device so that the temperature control module controls the temperature of the disk drive unit. The temperature control module has an air flow control device for controlling the flow of air across the disk drive unit appropriately according to the required temperature for the disk drive unit. The mounting device may be used in testing disk drive units.

Abstract: An interconnect assembly for evaluating a probe measurement network includes a base, respective inner and outer probing areas in mutually coplanar relationship on the upper face of the base, a reference junction, and a high-frequency transmission structure connecting the probing areas and the reference junction so that high-frequency signals can be uniformly transferred therebetween. A preferred method for evaluating the signal channels of the network includes connecting a reference unit to the reference junction and successively positioning each device-probing end that corresponds to a signal channel of interest on the inner probing area.

Abstract: A precision measurement unit (PMU) includes a force amplifier selectively providing either a forcing voltage or a forcing current to a device under test via an output force terminal. A low limit voltage clamp and a high limit voltage clamp are operatively coupled to the output force terminal. The low and high limit voltage clamps are each responsive to user programming to define respective low and high voltage limits at the output force terminal. Upon detection of a reversal of said user programming, the operation of the low and high limit voltage clamps is disabled. More particularly, a comparator is adapted to compare the low and high voltage limits and provide a corresponding disabling signal if the high voltage limit is lower than the low voltage limit.

Abstract: A system is provided for controlling the delay in an isolation buffer. Multiple such isolation buffers are used to connect a single signal channel to multiple lines and controlled to provide an equal delay. Isolation buffer delay is controlled to be uniform by varying either power supply voltage or current. A single delay control circuit forming a delay-lock loop supplies the delay control signal to each buffer to assure the uniform delay. Since controlling delay can also vary the output voltage of each isolation buffer, in one embodiment buffers are made from two series inverters: one with a variable delay, and the second without a variable delay providing a fixed output voltage swing. To reduce circuitry needed, in one embodiment an isolation buffer with a variable power supply is provided in a channel prior to a branch, while buffers having a fixed delay are provided in each branch.

Abstract: A method and an apparatus for testing transmitter and receiver have been disclosed. One embodiment of the apparatus includes a plurality of multiplexers to select one of a positive and a negative transmitter pins, and a first comparator to compare a voltage of the selected pin with a first reference voltage to determine whether there is leakage at the selected pin. Other embodiments are described and claimed.

Abstract: A system (5) for testing and failure analysis of an integrated circuit (10) is provided using failure analysis tools (40, 50, 60). An analysis module (30) having a number of submodule test structures is incorporated into the integrated circuit design. The test structures are chosen in dependence upon the failure analysis tools (40, 50, 60) to be used. The rest of the integrated circuit contains function modules (20) arranged to provide normal operating functions. By analysing the submodule test structures of the analysis module (30) using the failure analysis tools (40, 50, 60), physical parameters of the integrated circuit (10) are obtained and used in subsequent testing of the function modules (20) by the failure analysis tools (40, 50, 60), thus simplifying the testing of the integrated circuit (10) and reducing the time taken to perform a failure analysis procedure.

Abstract: A dual channel source measurement unit for reliability testing of electrical devices provides a voltage stress stimulus to a device under test and monitors degradation to the device under test caused by the stress simulator. The dual channel source measurement unit decouples the stress and monitor portions of the unit so that the requirements of each can be optimized. Deglitching and current clamp switches can be incorporated in the dual channel source measurement unit to prevent glitches in the switching circuitry and to limit or clamp current flow to or from the monitor and stress sources.

Abstract: A measurement method and system in which a plurality of sensors are scattered about the system. One or more universal data concentrators are deployed in the areas where the sensors are concentrated. Each data concentrator is connected to one or more computers. Unique configuration data is provided to each data concentrator for its unique sensor type complement. Each data concentrator configures itself based on its configuration data. This allows the use of a universal data concentrator and, thus, one part number.

Abstract: There is provided a test apparatus that tests an electronic device. The test apparatus includes: a plurality of test modules operable to supply test patterns used for a test of the electronic device to the electronic device; a reference clock generation unit operable to generate a reference clock; a generation circuit operable to generate timing signals that cause the plurality of test modules to operate based on the reference clock; a plurality of timing sources being provided in response to the plurality of test modules and operable to supply the timing signals to the corresponding test modules; and a control unit operable to control phases of the timing signals supplied to each of the test modules by the plurality of timing sources so that timings at which each of the test modules outputs the test patterns according to the timing signals are made to be equal.

Abstract: A method of and system for producing signals to test semiconductor devices includes a pin electronic (PE) stage for providing a parametric measurement unit (PMU) current test signal to a semiconductor device under test. The PE stage also senses a response from the semiconductor device under test.

Abstract: It is intended to provide a semiconductor integrated circuit device permitting reading of information specific to chips within the mounted chips while restraining the increase in the total number of terminals of the package and enabling the area of circuits required for reading information specific to chips to be made smaller than that according to the prior art, and a control method therefor. The same terminal is used as the external terminal to which the pulse signals are inputted and the external terminal from which the chip-specific information is outputted. Also, the external terminal for inputting/outputting required power supply in the normal operation mode and the external terminal for reading chip-specific information in the information reading mode are used in common. The increase in the number of external terminals can be thereby restrained. Moreover, the counter unit is shared between functional circuits and the comparative decision unit. This can serve to restrain the increase in chip area.

Abstract: A method, apparatus, system, computer program and medium, for inspecting a wide variety of circuit boards. A controller generates test data and reference data according to characteristic information of a circuit board. Using the test data, the circuit board generates processed data. A comparator compares the processed data with the reference data on a bit-by-bit basis. Based on the comparison result, the comparator determines acceptability of the circuit board. In addition, the comparator is capable of specifying a specific portion of the circuit board causing a defect.

Abstract: An electrical test circuit includes a bridge configuration having two paths between two nodes, a buffer, and a capacitor. An output of the buffer is coupled to one of the paths, the buffer is adapted to either provide a defined potential or a high impedance, the capacitor is connected to the output of the buffer, and a signal of a device under test is adapted to be coupled to another one of the paths. One of the nodes of the bridge configuration can be supplied with a first current, and the other one of the nodes of the bridge configuration can be supplied with a second current.

Abstract: A device characteristic testing system for testing a first DUT (device under test), a second DUT, a third DUT and a fourth DUT on a wafer, each of the DUTs includes a first end and a second end, the device characteristic testing system includes: a device characteristic testing circuit formed on the wafer includes a first conducting line connected to the second end of the first and the fourth DUT, a second conducting line connected to the second end of the second and third DUTs, a third conducting line connected to the first end of the first and second DUTs, a fourth conducting line connected to the first end of the third and fourth DUT, and a plurality of testing pads respectively coupled to the first, second, third, and fourth conducting line for receiving at least one testing signal to detect device characteristics of the DUTs.

Abstract: A testing apparatus having testing module slots onto which different types of testing modules are selectively mounted includes controlling modules for supplying control signals to the testing modules mounted on the testing module slots. The control signals are used for controlling the testing module. The apparatus also includes a setting information supplying unit for supplying hardware setting information to a specific testing module, an enable signal controlling unit for instructing the specific testing module to generate and supply an enable signal to the controlling module corresponding to the specific testing module, and a setting unit for setting the controlling module received said enable signal from the specific testing module so as to supply the control signal corresponding to the specific testing module based on the hardware setting information.

Abstract: Generating test signals for a device under test (DUT) involves generating a master reference signal, using a vernier technique to generate test pattern signals based on the master reference signal, generating a test clock signal that is phase-matched with and frequency similar to the test pattern signals by providing the master reference signal as input to a phase-locked loop (PLL) and controlling one or more programmable dividers in the PLL to adjust the test clock signal to be a multiple or sub-multiple of a frequency of the test pattern signals, applying the test clock signal to the clock input pin of the DUT, and applying the test pattern signals to data pins of the DUT. When the frequency of the test pattern signals is changed, the test clock signal frequency may be adjusted to calibrate to the changed frequency of the test pattern signals by re-programming the programmable dividers.

Abstract: A physical layer device including a first port and a second port comprises a cable tester that communicates with the first and second ports and that determines a cable status, which includes an open status, a short status, and a normal status. Opposite ends of a cable selectively communicate with the first and second ports. The cable tester includes a test module that transmits a test pulse on the cable, measures reflection amplitude, calculates a cable length, and determines the cable status based on the measured amplitude and the calculated cable length. A frequency synthesizer communicates with the cable and that selectively outputs a plurality of signals at a plurality of frequencies on the first port. An insertion loss calculator receives the signals on the second port and that estimates insertion loss.

Abstract: An asynchronous system for testing disk drives includes a test platform that includes a plurality of slots for receiving and for providing communication with drives. The slots are segregated into a plurality of groups configured to satisfy predetermined environmental, communication bandwidth and test schedule requirements of the drives to be loaded therein. An automated loader/unloader is configured to selectively load drives into and out of the platform and to move drives between the plurality of groups. A module controller is assigned to each group of slots, each module controller being coupled to the slots of its assigned group and configured to administer at least one test to drives loaded in its assigned group while insuring that the predetermined environmental, communication bandwidth and test schedule requirements of its assigned group remain satisfied.

Abstract: A wafer-level package includes a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit each provided with test chip terminals and non test chip terminals, at least one external connection terminal, at least one redistribution trace provided on the semiconductor wafer, at least one testing member, and an insulating material. A first end of the redistribution trace is connected to one of the test chip terminals and a second end of said redistribution trace is extended out to a position offset from the chip terminals. The testing member is provided in an outer region of the semiconductor chip circuit forming region, and the second end of the redistribution trace is connected to the testing member.

Abstract: A connection apparatus includes a switch; a control signal connector that transmits a switching signal, sent from a controller, to the switching means; a first plurality of connectors that are connected to the switch and that are to be connected to a plurality of measurement connectors included in first measuring apparatus for measuring a first electrical characteristic of the device under test; and a second plurality of connectors that are connected to the switch and that are to be connected to a plurality of measurement connectors included in second measuring apparatus for measuring a second electrical characteristic of the device under test. In accordance with the switching signal sent from the controller via the control-signal connector, the switch performs switching so that either the first plurality of connectors or the second plurality of connectors are electrically connected to the device under test.

Abstract: A system for testing a relay is provided. The system includes a plurality of signal generators to generate signals to test relays. The system includes a controller to provide at least some inputs for use by at least one of the signal generators to generate the signals. The system also includes a hand-held controller in communication with the controller. The hand-held controller is operable to receive and display relay test information for a user. The hand-held controller is operable to transmit one or more control inputs for testing the relay.

Abstract: An integrated circuit (IC) tester includes a set of power modules mounted in a test head, each contacting a device interface board (DIB). The DIB provides power paths for delivering an output current generate by each power module to a power input terminals of one or more IC devices under test (DUTs). Power modules that supply current to the same set of DUTs communicate with one another though conductive paths provided by the DIB to ensure that all power modules begin supplying load current to that set of DUTs at the same time and to ensure that all power modules supply substantially the same amount of load current to those DUTs.

Abstract: A signal interface to connect a semiconductor tester to a device under test. The Interface includes a generic component and customized component. The generic component includes multiple copies of electronic elements that can be connected in signal paths between the tester and the device under test. The customized component is constructed for a specific device under test and provides connections between generic contact points on the generic component and test points on the device under test. In addition, the customized component has conductive members that can be used to interconnect the electronic elements on the generic component. The connections configure the electronic elements into signal conditioning circuitry, thereby providing signal paths through the interface that are compatible with the I/O characteristics of specific test points on a device under test. The generic and the customized components may be fabricated on semiconductor wafers.

Abstract: A design for test focused tester has a single printed circuit board tester architecture. By focusing on design for test testing and eliminating functional testing, the design for test focused tester reduces or eliminates requirements for high speed, precision signal formatting and timing circuitry that require a multiple board architecture interconnected via a high speed backplane. The single board architecture places a vector sequencer and vector memory close to the device under test, which provides short, consistent signal paths to the device and eliminates the need for dead cycles and synchronization between tester boards.

Abstract: Each chip includes, in addition to a core logic, a register such as a BSR. A TAPC for controlling the register is provided only on a chip of the first stage, and an test commands/data output and input signal lines for the boundary scan test are connected to each other via wire to form a loop. Other signal lines used in the test are distributed from an output signal line of the chip of the first stage. As a result, the test needs to be carried out only once with a smaller number of pins and the number of steps and area can be reduced in chips not provided with TAPC. With this arrangement, in a stacked device in which a plurality of chips are integrally sealed, the boundary scan test only needs to be carried out once with a smaller number of pins.

Abstract: A power meter is provided in which calibration is carried out as an automated procedure controlled by the meter.

Abstract: According to one embodiment, a method of testing an integrated circuit is provided. The quiescent current measuring of an integrated circuit is measured at two voltages. The functional relationship between the current measurements is determined and compared against a predetermined functional relationship to determine whether a defect exists in the integrated circuit.

Abstract: A pin electronics circuit for use in automatic test equipment is disclosed. The pin electronics circuit includes a pin driver having an output adapted for coupling to a device-under-test pin, and a first input. AC input circuitry couples to a pattern generator to receive pattern test signals while DC input circuitry connects to a DC parametric controller. Selector circuitry selectively couples the AC and DC input circuitry to the pin driver first input.

Abstract: A test system formatter may include a programmable drive circuit configurable to operate in any of a plurality of drive modes, each mode corresponding to a different combination of drive signals or drive timing markers or both, and a programmable response circuit configurable to operate in any of a plurality of strobe modes, each strobe mode corresponding to a different combination of strobe signals. The formatter may also include multiple drive channels and/or multiple response channels, each channel being formed, e.g., of an event logic interface and a corresponding linear delay element. The drive channels provide signals to the drive circuit to be used to generate drive signals or drive timing markers or both. The response channels receive from one or more pin-electronics comparators response signals used to generate fail outputs. The programmable drive and response circuits are configurable to route signals through multiple channels in parallel.

Abstract: A testing device for testing a printed circuit board comprises a testing signal converting module which comprises a connector for receiving testing signals from the printed circuit board and a converting circuit for converting the testing signals to compatible signals, the converting circuit is coupled to the connector. A testing circuit receives compatible signals from the testing signal converting module.

Abstract: Noise reduction for application of structural test patterns to a Device Under Test (DUT) is accomplished with a capacitor “booster” bypass network on the probe card in which the capacitors are charged to a much higher voltage Vboost than the DUT power supply voltage VDD. Charging the capacitors to a voltage N×VDD allows the buster network to store N times the charge of a conventionally configured capacitance network, and effectively provides N times the capacitance of the original network in the same physical space.

Abstract: A method and apparatus for testing the electrical power system of an aircraft uses existing unmodified test equipment not otherwise capable of reliably testing and certifying the aircraft for weapon store launching operations for a particular store type.

Abstract: A method and an apparatus for testing transmitter and receiver have been disclosed. One embodiment of the apparatus includes a plurality of multiplexers to select one of a positive transmitter pin and a negative transmitter pin, and a first comparator to compare a voltage of the selected pin with a first reference voltage to determine whether leakage exists at the selected pin. Other embodiments are described and claimed.

Abstract: A circuit and a method for monitoring defects in an integrated circuit chip. The circuit including a defect monitor portion and a sense element portion, the defect monitor portion either coupled to inputs of sense elements arranged in a chain or coupled between sense elements and forming portions of the chain.

Abstract: A physical layer device including a first port, a second port, and a cable that has one end that communicates with the first port and an opposite end that communicates with the second port. A cable tester tests the cable to determine a cable status, which includes an open status, a short status, and a normal status. A pretest module senses activity on the cable and selectively enables testing depending upon the sensed activity. A test module transmits a test pulse on the cable, measures a reflection amplitude, calculates a cable length, and determines the cable status based on the measured amplitude and the calculated cable length. A frequency synthesizer communicates with the cable and that selectively outputs a plurality of signals at a plurality of frequencies on the first port. An insertion loss calculator receives the signals on the second port and that estimates insertion loss.