Abstract: An apparatus and method are provided for testing component tolerances of a device for testing integrated circuits. The testing device is generally characterized by a plurality of test connectors disposed at a test head, wherein each test connector carries electrical signals for a test channel. Further, each test channel generally corresponds to a circuit board that includes at least one driver and one receiver. In this general type of tester, a system is provided that includes a specialized DUT board that establishes a low impedance electrical connection (i.e., short) between electrical conductors of a first and second test connector. Through this low impedance path, a first driver from a first circuit board is directly connected (i.e., shorted) to a first receiver on a second circuit board. A controller is configured to control the first driver to output an electrical signal at a predetermined time.

Abstract: To remove ringing from pulse. A buffer amplifier (30) is inserted in series into a path through which a signal is transmitted. Ringing caused in the output of the buffer amplifier (30) is detected by an L side comparator (31) and an H side comparator (32). When ringing is detected a current is supplied into the input of the buffer amplifier (30) through an L side current supply circuit (33) or an H side current supply circuit (34). By supplying a current from the L side and H side current supply circuits (33, 34), the overshooting portion due to ringing can be suppressed.

Abstract: Pin-driver circuitry in each of an automatic circuit tester (10)'s digital driver/sensor circuits (36) includes a current sensor (Rsense, QS1, QS2, D1, and D2) and comparison circuit (58) that indicate whether the load current supplied by the driver exceeds a level set by a threshold input (CURRENT_VALUE). The pin-driver circuitry also includes a timer (60) whose output indicates whether the comparison circuit's output has been asserted for a length of time that exceeds a limit set by a duration input (TIME_VALUE). When it has, the tester disables the driver and thereby prevents damage that could otherwise result from excessive backdrive durations that the test-generation process did not anticipate. When no backdriving is sensed during a given burst of test signals, the tester forgoes the normal cool-down delay, thereby speeding the test process.

Abstract: A systematic method for assigning tester channels on an Automated Test Equipment (ATE) to various signal pins on Device Under Test (DUT). The method involves creating a test fixture or a load board for a digital Integrated Circuit (IC) by wiring the DUT pins to as few channel groups as possible. The number of channel groups required for each vector set load are calculated before the signal pins are assigned. Then, the signal pins are assigned in a systematic manner to the fewest number of channel groups. As the number of test channel groups is reduced, the amount of vector data loaded into the tester's vector memory before each test vector is executed also is reduced, therefore reducing the time and cost required to test the signal pins on the DUT.