Abstract: An analysis tool which extracts all the available parameter identifications (i.e. PIDS) from a vehicle's power train control module for diagnostic decisions. This is done by checking these PIDS and other information (e.g., calculated PIDS, Break Points, charts and algorithms) in three states; key on engine off, key on engine cranking, key on engine running. In all three modes the tool is comparing the live data from PIDS and voltage to the other information (e.g, Break Points). If any of this data are outside the programmed values a flag is assigned to the failure or control problem. The relationship between a particular PID and its associated preprogrammed value(s) may be indicated by a light. The depth of the problem (if any) is conveyed by the color of the light. Also included are tests/charts for fuel trim, engine volumetric efficiency, simulated injector, power, catalyst efficiency, and engine coolant range.

Abstract: A test apparatus for testing a device under test includes a test signal generating section that generates a test signal to be supplied to the device under test, a main driving section that outputs an output voltage determined in accordance with the test signal, to an input/output pin connected to a signal input/output terminal of the device under test, a replica driving section that outputs a comparison voltage determined in accordance with the test signal, a resistance voltage dividing section that generates a divided voltage by resistance-dividing the comparison voltage, a comparing section that compares a voltage of the input/output pin with the divided voltage, a judging section that judges acceptability of the device under test based on a result of the comparison by the comparing section, and an adjusting section that adjusts a voltage dividing ratio of the resistance voltage dividing section so that the divided voltage becomes equal to a voltage obtained by adding together a predetermined threshold volt

Abstract: A self test adapter (STA) for automatic test equipment (ATE) is provided. The STA includes an enclosure. A backplane is housed by the enclosure. A dual data bus is integrated into the backplane. At least one STA card module is inserted into the backplane. The at least one STA card module has a port for interconnection with an ATE station receiver. The at least one STA card module includes a generic region adapted for interfacing with an additional STA card module over the dual data bus, and a resource specific region adapted for self test of at least one ATE station resource.

Abstract: A storage device testing system that includes at least one rack, test slots housed by each rack, and at least one air mover in pneumatic communication with the test slots. Each test slot includes a test slot housing having an entrance and an exit, with the entrance configured to receive a storage device. The at least one air mover is configured to move air exterior to the racks into the entrance of each test slot housing, over the received storage device, and out of the exit of each test slot housing.

Abstract: Electronic component validation testing is facilitated by a method, system and program product which allows the importation of virtual signals derived from simulation verification testing of the electronic component design into electronic test equipment employed during validation testing of the actual electronic component.

Abstract: A power consumption analyzing apparatus has a clock gating cell detector configured to detect a clock gating cell which is not present in RTL data but present in a gate-level netlist, a test bench description generation unit configured to add a description concerning the clock gating cell, a monitor signal generation unit configured to specify a monitor signal used for power consumption analysis from the RTL data, an RTL simulation unit configured to execute operational simulation of the target circuit, a monitor unit configured to detect a logic of the monitor signal during the execution of the operational simulation, and a power consumption analysis unit configured to analyze power consumption.

Abstract: A circuit testing apparatus for testing a device under test is disclosed. The device under test comprises a first output end and second output end for generating a first output signal and a second output signal, respectively. The circuit testing apparatus determines a test result for the device under test according to the first output signal and the second output signal.

Abstract: A mechanism uses in-situ bidirectional cable wrapping for determining different cable lengths. A calibration mechanism calibrates the high speed transmitter/receiver pair characteristics, and, thus, optimizes the transmission performance between subsystems. The calibration mechanism mitigates the need for frequent error correction and does not incur the performance degradation associated with error correction techniques.

Abstract: In one embodiment, a power supply controller is configured to operate in a test mode that facilitates measuring the value of an output signal of an error amplifier of the power supply controller.

Abstract: A cathodic protection monitor to be electrically connected to a cathodic protection rectifier that is adapted to prevent rust, corrosion and possible leakage in an underground pipe or storage tank above which the rectifier is supported. The cathodic protection monitor includes a CPU that reads, digitizes and stores analog current and voltage signals which are supplied from the DC output of the rectifier and are indicative of the effectiveness thereof. The monitor includes an ISM band transceiver and antenna by which the CPU is polled and from which packets of stored data are transmitted to a data collector at an overhead airplane or nearby motor vehicle for retransmission and analysis by the pipe owner or maintenance crew.

Abstract: Provided is a method and system for testing a DUT. The system includes a plurality of testing devices for interacting with the DUT and conducting a plurality of different tests on the DUT, and a computer-readable memory for storing computer-executable instructions defining the plurality of tests to be conducted by the testing device on the DUT. A scheduler component designates at least a first test and a second test from the plurality of tests to be conducted on the DUT in parallel, wherein said designating is based at least in part on content of the computer-executable instructions defining the first test and the second test. And a controller initiates the first test and the second test to be conducted in parallel and initiating at least a third test sequentially relative to at least one of the first and second tests.

Abstract: Embodiments may include a method and an apparatus for inducing degradation through temperature cycling of a solder joint or a component on a surface mount printed wiring board (SMPWB) coupon. The coupon may include alternating layers of dielectric material and conductive material stacked one upon another and a heating trace mounted on a surface of the SMPWB or between layers of dielectric material. A first value indicative of a temperature of the heating trace may be determined based on a measured electrical resistance of the heating trace. A difference between the first value and a second value indicative of a desired temperature of the heating trace may be determined. A particular current and a particular voltage may be applied to the heating trace based on the determined difference between the first value and the second value.

Abstract: A structure has a printed board carried by a metal chassis. A printed board carrying chassis analyzing system, a printed board carrying chassis analyzing method, a printed board carrying chassis structure, and a printed board carrying chassis analyzing program are provided to achieve a screw-fastened arrangement for predicting unnecessary radiation frequencies and for reducing unnecessary radiation. An equivalent circuit model including a printed board power and ground plane pair, a pair of confronting surfaces of a printed board and a chassis, and screw-fastened grounding posts is generated and analyzed to predict unnecessary radiation frequencies and unnecessary radiation reductions and to select a screw-fastened arrangement for reducing unnecessary radiation.

Abstract: A method includes defining a hierarchy of test routines in a test program for testing integrated circuit devices. A first device is tested at a first screening level in the hierarchy. The first device is tested at a second detailed level in the hierarchy responsive to the first device failing the testing at the first screening level.

Abstract: A system and method for reducing timing errors in automated test equipment (ATE) offering increased data rates for the testing of higher-speed integrated circuits. Embodiments provide an effective mechanism for increasing the data rate of an ATE system by delegating processing tasks to multiple test components, where the resulting data rate of the system may approach the sum of the data rates of the individual components. Each component is able to perform data-dependent timing error correction on data processed by the component, where the timing error may result from data processed by another component in the system. Embodiments enable timing error correction by making the component performing the correction aware of the data (e.g., processed by another component) causing the error. The data may be shared between components using existing timing interfaces, thereby saving the cost associated with the design, verification and manufacturing of new and/or additional hardware.

Abstract: A test circuit for, and method of, determining electrical properties of an underlying interconnect layer and an overlying interconnect layer of an integrated circuit (IC) and an IC incorporating the test circuit or the method. In one embodiment, the test circuit includes a gate chain having a ring path and a stage. In one embodiment, the stage includes: (1) a underlying test segment in the underlying interconnect layer, (2) a overlying test segment in the overlying interconnect layer and (3) logic circuitry activatible after formation of the underlying interconnect layer and before formation of the overlying interconnect layer to place the underlying test segment in the ring path and further activatible after the formation of the overlying interconnect layer to substitute the overlying test segment for the underlying test segment in the ring path.

Abstract: To provide a control method and a control program of a prober that are capable of enhancing throughput. Chips are tested in step S2. In step S3, when the counted number Y of conforming chips has reached a predetermined number of conforming chips X which constitutes conditions for testing, the process advances to step S10. In step S10, testing of wafers taking place at that time is interrupted, and this wafer is stored in an output cassette OC1. In a subsequent step S11, the subsequent wafer is tested, and stored in the output cassette OC2 (step S12). When all wafers have been tested, the process advances to step S14, and testing of the lot is completed. As a result, wafers that remain untested and wafers that have been tested stored separately in the input cassette and the output cassettes.

Abstract: There is provided a test apparatus for testing a device under test. The test apparatus includes a plurality of drivers that respectively output a plurality of test signals to a same terminal of the device under test so as to supply, to the same terminal of the device under test, a multiple-valued signal that is generated by combining together the plurality of test signals, and a plurality of probe pins that are provided in a one-to-one correspondence with the plurality of drivers. Here, each of the plurality of probe pins has a top end portion to be electrically connected to the same terminal of the device under test so as to supply a signal output from a corresponding one of the plurality of drivers to the same terminal of the device under test while the test apparatus is testing the device under test, and the top end portion of each probe pin is kept electrically open while the test apparatus is not testing the device under test.

Abstract: Disclosed herein is a measurement apparatus for improving performances of standard cells in a standard cell library when verifying performance of the standard cell library through a ring oscillator among various test element groups (TEGs). A built-in circuit is used to measure and verify performance of the standard cell library through a TEG. Therefore, it is possible to effectively improve performances of the standard cells in the standard cell library. Particularly, it is possible to not only remove human errors or internal errors of equipment, but also perform the measurement more readily, rapidly and accurately. Further, it is possible to curtail the use of high-performance equipment or manpower and time required in a measurement process.

Abstract: A semiconductor test device of the present invention for conducting a test on a device under test, includes: a plurality of comparison units which compare a signal obtained from the device under test with a predetermined reference voltage and output a comparison result; a plurality of measuring units which are provided in correspondence with the plurality of comparison units, and measure a time from when a measurement start signal is input thereto to when the comparison result from a corresponding comparison unit is input thereto, and output a measuring result; a start signal output unit which outputs the measurement start signal at a same timing to each of the plurality of measuring units; and a computation unit which computes time differences between a plurality of signals obtained from the device under test based on the measuring results of the plurality of measuring units.

Abstract: A power supply controller (20) is configured to operate in a test mode that facilitates measuring the value of an output signal of an error amplifier (36) of the power supply controller (20).

Abstract: An apparatus and associated method for analyzing a communications link between two components on a common PCB. The communications link has a pair of through-board conductors connected by a first conductive etching on one side of the PCB. The communications link further has second etchings on an opposite side of the PCB respectively connecting each of the through-board conductors to one of the components. The first conductive etching can operably be open-circuited and connectors of an analyzer can be fitted to the through-board conductors to test the communications link between the components.

Abstract: A data processing device includes a first memory for use during normal operation of the device and a second memory for use during testing. The second memory stores a set of test patterns for testing of a functional module. When the data processing device is in a normal (i.e. non-test) mode of operation, data is retrieved from a first memory based on a received memory address. The retrieved data is applied to the functional module of the data processing device to perform a designated function. When the data processing device is in a test mode of operation, received memory addresses are provided to the second memory for retrieval of a test pattern associated with the address. The test pattern is applied to the functional module to generate an output pattern. The result of a test is determined by comparing the output pattern to an expected pattern.

Abstract: A method for automatically testing an electronic circuit with a capacitive sensor having two capacitors is provided, wherein the common electrode of the capacitors moves relative to each fixed electrode. The electronic circuit includes a sensor interface that includes a charge transfer amplifier unit, an integrator unit connected to the amplifier unit to provide measurement output voltage, and an excitation unit. The excitation unit inversely polarizes each fixed electrode at high or low voltage or discharges the capacitors. The method includes several successive measurement cycles each divided into a first phase discharging capacitors by output voltage and a second phase for polarizing the fixed electrode of the first capacitor at high voltage and inversely polarizing the fixed electrode of the second capacitor at low voltage. In the measuring cycles, a test phase replaces a second polarizing phase in at least one cycle in every two successive measurement cycles.

Abstract: A method includes collecting trace data associated with a plurality of device testers. Tester health metrics are generated for each of the device testers. The tester health metrics are analyzed to identify a selected tester health metric that diverges from the plurality of tester health metrics. A corrective action is initiated for the tester associated with the selected tester health metric. A method includes collecting trace data associated with a plurality of device testers. The trace data for each of the device testers is compared to a reference trace data set to generate tester health metrics for each of the device testers based on the difference therebetween. The tester health metrics are analyzed to identify a selected tester health metric that diverges from the plurality of tester health metrics. A corrective action is initiated for the tester associated with the selected tester health metric.

Abstract: A semiconductor integrated circuit includes power supply pads of two or more kinds, switches each of which is connected between adjacent two of the power supply pads to allow short-circuiting them, and at least one control line connected to control terminals of the switches according to the kinds of the power supply pads connected to the switches.

Abstract: A motherboard testing apparatus for automatically turning on or off a motherboard includes a pulse signal generating circuit for outputting a pulse signal, a first control circuit for outputting a first control signal to an I/O controller on the motherboard according to the pulse signal, and a second control circuit. The first control circuit outputs a low level first control signal when it receives a low level pulse signal, the I/O controller turns the motherboard on when it receives the low level first control signal. The second control circuit outputs a second control signal to the first control circuit which controls the motherboard to turn on again when the first control circuit receives the low level pulse signal a next time.

Abstract: A program circuit activates a pass signal when a first program unit is programmed. The first program unit is programmed when a test of an internal circuit is passed. A mode setting circuit switches an operation mode to a normal operation mode or a test mode by external control. A state machine allows a partial circuit of the internal circuit to perform an unusual operation different from a normal operation when the pass signal is inactivated during the normal operation mode. By recognizing the unusual operation during the normal operation mode, it can be easily recognized that a semiconductor integrated circuit is bad. Since a failure can be recognized without shifting to the test mode, for example, a user who purchases the semiconductor integrated circuit can also easily recognize the failure.

Abstract: There is provided a test apparatus including a driver that outputs a test signal to a device under test, a first switch that switches whether to connect the driver to the device under test, a comparator that receives an output signal from the device under test via the first switch, and compares a voltage of the output signal with a predetermined reference voltage, a reference voltage input section that inputs the reference voltage into the comparator, a second switch that is provided between the reference voltage input section and the comparator, and a dummy resistance that is connected at one end thereof to a connection point between the comparator and the second switch and at the other end thereof to a predetermined potential. Here, a resistance ratio between an output resistance of the driver and an on-resistance of the first switch is substantially equal to a resistance ratio between the dummy resistance and an on-resistance of the second switch.

Abstract: A semiconductor chip test apparatus includes a plurality of power supply units, each supplying power to a semiconductor chip having a power input terminal, and a tester configured to measure an output current of at least one of the plurality of power supply units, and to generate a switching control signal when the measured output current is greater than a predetermined current. The semiconductor chip test apparatus also includes a plurality of relays each arranged between a common ground of the tester and a different ground of the semiconductor chip. Further, the semiconductor chip test apparatus includes a relay controller, such as a control bit generator, configured to selectively close one or more of the plurality of relays in response to the switching control signal from the tester.

Abstract: A sequential semiconductor device tester, and in particular to a sequential semiconductor device tester is disclosed. In accordance with the sequential semiconductor device tester, a function of generating a test pattern data for a test of a semiconductor device and a function of carrying out the test are separated to sequentially test the semiconductor device, to maintain a signal integrity and to improve an efficiency of the test by carrying out a test under an application environment or an ATE test according to the test selection command.

Abstract: A physical layer device includes a cable test module that transmits a test pulse on a cable, measures a reflection amplitude, calculates a cable length, and determines a cable status based on the measured amplitude and the calculated cable length. A frequency synthesizer selectively outputs a plurality of signals at a plurality of frequencies on one end of the cable. An insertion loss calculator receives the signals from an opposite end of the cable and estimates insertion loss based on the received signals.

Abstract: In an embodiment, an integrated circuit or chip is supplied to its intended application and a measurement quantity representing the state of one or a plurality of electrical connections in the chip is determined within the application environment of the chip and, if the measurement quantity determined does not correspond to predefined criteria, a corresponding signal is output.

Abstract: A driver for supplying a test signal to a device under test is shared by a plurality of terminals. In this way, the cost and time required for the test of the device under test can be reduced. A testing apparatus 10 relating to the present invention includes a test signal generating section 130 that generates a test signal to be supplied to a device under test 20, a driver 140 that outputs the test signal, a switch 150 that is disposed on a wire between the driver 140 and a first terminal of the device under test 20, a switch 160 that is disposed on a wire between the driver 140 and a second terminal of the device under test 20, and a connection control section 100 that (i) turns on the switch 150 and turns off the switch 160 when the test signal is supplied to the first terminal of the device under test 20, and (ii) turns off the switch 150 and turns on the switch 160 when the test signal is supplied to the second terminal of the device under test 20.

Abstract: A test instrument network for testing a plurality of DUTs includes a plurality of communicating script processors, the script processors being adapted to execute computer code; and a plurality of measurement resources controllable by the script processors in response to executed computer code, the measurement resources being adapted to test the DUTs. Each script processor and measurement resource may be arbitrarily assigned by the controller to one of at least two groups, only one script processor being assigned to be a master script processor, any other script processor being a slave script processor and any group not including the master script processor being a remote group. The master script processor is exclusively authorized to initiate code execution on any script processor in a remote group. Any slave script processor is only able to initiate operation of measurement resources in it own group.

Abstract: A sequential semiconductor device tester, and in particular to a sequential semiconductor device tester is disclosed. In accordance with the sequential semiconductor device tester, a function of generating a test pattern data for a test of a semiconductor device and a function of carrying out the test are separated to sequentially test the semiconductor device, to maintain a signal integrity and to improve an efficiency of the test by carrying out a test under an application environment or an ATE test according to the test pattern data.

Abstract: A wafer-level package includes a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit each provided with test chip terminals and non test chip terminals, at least one external connection terminal, at least one redistribution trace provided on the semiconductor wafer, at least one testing member, and an insulating material. A first end of the redistribution trace is connected to one of the test chip terminals and a second end of said redistribution trace is extended out to a position offset from the chip terminals. The testing member is provided in an outer region of the semiconductor chip circuit forming region, and the second end of the redistribution trace is connected to the testing member.

Abstract: There is provided a power supply stabilizing circuit provided in a chip of an electronic device. The power supply stabilizing circuit stabilizes a power supply voltage supplied to an operational circuit of the electronic device, and includes a current bypass section that supplies a bypass current from an auxiliary power supply interconnection to a main power supply interconnection, where the main power supply interconnection supplies the power supply voltage to the operational circuit, and the auxiliary power supply interconnection is different from the main power supply interconnection, and a current control section that varies an amount of the bypass current supplied by the current bypass section to the main power supply interconnection in accordance with a predetermined current variation pattern, under an external control, during an operation of the operational circuit.

Abstract: A system is disclosed that can be inserted between cable runs of electrical equipment so as to provide access to signal/data lines associated with the electrical equipment. The system includes a microprocessor and a matrix switch and preferably display equipment and measurement instrumentation. The microprocessor controls the matrix switch so as to route signals to a high impedance probe array that then feeds data to measurement instrumentation. The system provides pattern analyzers, which are resident in the microprocessor routine software. The measurement instrument provides measurement quantities, timing, and patterns that may be compared to known good data to ascertain the state of the health of the electrical equipment. The system is also capable of blocking signal paths and providing known good signals to the associated electrical equipment. Test data is stored in memory for later retrieval and the display equipment provides a pass, fail or intermittent indication.

Abstract: Data characterizing a read/write head of a hard disk drive is produced in a burn-in process. The method includes measuring the flying height of the head at a first temperature in a burn-in chamber, measuring the flying height of the head at a second temperature in the burn-in chamber, postulating a linear relationship between the flying height and the temperature of ambient air using values of the flying height measured at the first and second temperatures, and estimating the flying height of the head at a third temperature using the linear relationship. The elevation of the read/write head is then controlled based on data representing the values of the flying height as measured at the first and second temperatures and as estimated for the temperature. In particular, the amount of electric power supplied to an FOD heater of the head is controlled based on the data generated during the burn-in process.

Abstract: A method and system for multi-point (e.g., double-point) GOI test that can efficiently judge failure modes by testing only two points. We can measure leakage currents at only two voltages, which are the cut points of mode A-B and B-C, instead of the whole ramped voltages to save time and cost with the same test effectiveness according to a specific embodiment. By correlating leakage current at extrinsic field to the breakdown voltage, we can also evaluate the intrinsic reliability even if the samples are not subjected to actual breakdown according to a specific embodiment.

Abstract: An enhanced loadboard and method for enhanced automated test equipment (ATE) signaling. More specifically, embodiments provide an effective mechanism for reducing signal degradation and error interjection by replacing one or more relays with signal splitters for directing signals between one or more pins of a coupled ATE instrument, where the signal splitters reduce loadboard size and operating cost.

Abstract: A high-definition multimedia interface circuit uses a high-definition multimedia interface encoder to produce a plurality of channels of data. An output circuit, connected to the high-definition multimedia interface encoder, produces a plurality of channels of high frequency data from the data produced by the high-definition multimedia interface encoder. A multiplexer selects a channel for sampling, and a capacitive coupler capacitively couples the multiplexer to a sampling circuit. The sampling circuit produces sampled data corresponding to the high frequency data having a clock rate less than a clock rate of the high frequency data. A test circuit compares the sampled data with the data produced by the high-definition multimedia interface encoder.

Abstract: A testing system for measuring an electronic device includes a main controller for generating a control signal, a signal generator for outputting a predetermined test input signal according to the control signal, an instrument unit having a plurality of instruments, and a testing port having a plurality of probes. The plurality of probes connects corresponding testing points of the electronic device to the signal generator and the instruments. The predetermined test input signal is transmitted to the electronic device via the testing port. The instrument unit processes a test result signal outputted by the electronic device and outputs a result data. The main controller receives the result data and computes whether the result data is within a predetermined range. A related testing method is also provided.

Abstract: A test apparatus includes one handler connected to a tester and one test board divided into two or more sites or two or more test boards. Since only the sites on the test board (or test boards) need be duplicated, rather than the loading lanes or sorters of the handler, the test apparatus can be conveniently compact. Further, while testing semiconductor devices on one site or one test board, semiconductor devices in another site or on another test board can be sorted according to the test result. This enables the reduction or elimination of tester idle time to optimize the efficiency of the test apparatus.

Abstract: Disclosed is a method and system for wafer/probe testing of integrated circuit devices after manufacture. The invention begins by testing an initial group of devices (e.g., integrated circuit chips) to produce an initial failing group of devices that failed the testing. The devices in the initial failing group are identified by type of failure. Then, the invention retests the devices in the initial failing group to identify a retested passing group of devices that passed the retesting. Next, the invention analyzes the devices in the retested passing group which allows the invention to produce statistics regarding the likelihood that a failing device that failed the initial testing will pass the retesting according to the type of failure. Then, the invention evaluates these statistics to determine which types of failures have retest passing rates above a predetermined threshold.

Abstract: A method for testing a semiconductor wafer using an in-line process control, e.g., within one or more manufacturing processes in a wafer fabrication facility and/or test/sort operation. The method includes transferring a semiconductor wafer to a test station. The method includes applying an operating voltage on a gate of a test pattern on a semiconductor wafer using one or more probing devices. The method includes measuring a first leakage current associated with the operating voltage. If the measured first current is higher than a first predetermined amount, the device is an initial failure. If the measured first current is below the first predetermined amount, the device is subjected to a second voltage. The method includes applying the second voltage on the gate of the test pattern on the semiconductor wafer and measuring a second leakage current associated with the second voltage. If the second measured leakage current is higher than a second predetermined amount, the device is an extrinsic failure.

Abstract: A semiconductor device includes: a command control circuit for decoding a command signal to output a test signal and a normal control signal; a normal circuit for performing a predetermined operation in response to the normal control signal; and a test circuit for testing electrical characteristics of unit elements provided in the normal circuit in response to the test signal.

Abstract: A test apparatus that tests a device under test is provided. The test apparatus includes a test module that provides a test signal to the device under test. The test apparatus includes: a test module that provides a test signal to the device under test; a measuring instrument that measures a reference parameter including at least one of a reference voltage, a reference resistance and a reference current included in the test module; and a control device that controls the test module and the measuring instrument.

Abstract: A boundary-scan circuit method and apparatus for asserting an internal reset signal connected to core logic circuits of an electronic device in order to assure that testing will begin and end in a safe, known logic state. A safe end state is assured even if the system reset signal on an input pin of the electronic device is logically disconnected from the internal reset connection to the core logic, as often occurs in boundary-scan and related testing.