Abstract: Exemplary systems, methods and computer-accessible mediums can encrypting a circuit by determining at least one location to insert at least one gate in the circuit using a fault analysis, and inserting the at least one gate in at least one section of the at least one location. The determination can include an iterative procedure that can be a greedy iterative procedure. The determination can be based on an effect of the particular location on a maximum number of outputs of the circuit.

Abstract: A method for operating a brushless electric motor, the windings being energized by an inverter with the aid of six switches. A detection unit for detecting defective switches, a unit for measuring voltage at the outputs of the inverter, and a microcontroller for controlling the switch and for generating a pulse width modulated voltage supply for the windings are provided. A short-circuited switch causes a torque in the electric motor opposite the actuating direction of the electric motor. The method proposes that after detecting a short-circuited switch, the windings (U. V. W) are energized to generate a motor torque that is, on the whole, positive. An actuating period of the electric motor is divided into a plurality of sectors, wherein, in accordance with the defective switch, individual sectors are deactivated for the actuation of the windings (U, V, W), while other sectors are used to actuate the windings (V, W).

Abstract: Testing a digital-to-analog converter (DAC), where the test is carried out iteratively for a plurality of digital test signal values, includes: providing the digital test signal to a DAC under test and to a servo; providing, by the DAC under test to a summer, an analog test signal, including converting the digital test signal to the analog test signal; providing, by the summer to an observation latch, a summed signal, including summing the analog test signal and an analog offset signal, the analog offset signal received from a second DAC; providing, by the observation latch to the servo, a sample of the summed signal; providing, by the servo to the second DAC in dependence upon the sample and the digital test signal, a digital offset signal, where the second DAC converts the digital offset signal to the analog offset signal; and storing, as a digital observation, the digital offset signal.

Abstract: A device for performing timing analysis used in a programmable logic array system is provided. The device comprises first and second basic I/O terminals, a channel multiplexer, high-speed I/O terminals, a sampling module and a timing analysis module. The first basic I/O terminals receive under-test signals from an under-test unit. The channel multiplexer receives the under-test signals from the first basic I/O terminals to select at least a group of the under-test signals to be outputted to the second basic I/O terminals. The high-speed I/O terminals has a logic level analyzing speed higher than that of the first and second basic I/O terminals. The sampling module receives the group of under-test signals from the high-speed I/O terminals and samples the group of under-test signals to generate a sample result. The timing analysis module performs timing analysis and measurement according to the sample result.

Abstract: Disclosed is a signal transmission circuit device (200) including a feedback signal transmission unit (210) that feeds back a control output signal (Sout) as a feedback signal (Sf) to an input side circuit (200A). A logical comparison circuit (212) detects “mismatch” between input and output by performing logical comparison between a control input signal (Sin) and the feedback signal (Sf). When a state of “mismatch” between input and output occurs, a first pulse generating circuit (202) or a second pulse generating circuit (204) outputs a first correction signal (Sa1) or a second correction signal (Sa2) corresponding to a potential (high level or low level) of the control input signal (Sin), and corrects the control output signal (Sout) to the same potential (high level or low level) as the control input signal (Sin). With such configuration, the mismatch between input and output can be automatically corrected.

Abstract: Each register in each built-in self-test (BIST) controller contains a BIST controller-specific start count value that is different from at least one other BIST controller-specific start count. A test controller provides a start command simultaneously to all the BIST controllers. This causes each of the BIST controllers to simultaneously begin a countdown of the BIST controller-specific start count values, using a counter. Each of the BIST controllers starts a test procedure in a corresponding BIST domain when the countdown completes (in the corresponding BIST controller). Thus, the test procedure starts at different times in at least two of the BIST domains based on the difference of the BIST controller-specific start count values in the different registers. Further, during the test procedure, each stagger controller can stagger the start of each BIST engine within the corresponding BIST domain to which the stagger controller is connected.

Abstract: A method provides an improved checking of repeatability and reproducibility of a measuring chain, in particular for quality control by semiconductor device testing. The method includes testing steps provided for multiple and different devices to be subjected to measurement or control through a measuring system that includes at least one chain of measuring units between a testing apparatus (ATE) and each device to be subjected to measurement or control. Advantageously, the method comprises checking repeatability and reproducibility of each type of unit that forms part of the measuring chain and, after the checking, making a correlation between the various measuring chains as a whole to check repeatability and reproducibility, using a corresponding device subjected to measurement or control.

Abstract: A pattern generator generates a pattern signal which represents a test signal to be supplied to a DUT. A driver generates a test signal having a level that corresponds to the pattern signal, and outputs the test signal thus generated to the DUT. A voltage modulator changes, in a predetermined voltage range, the voltage level of the test signal output from the driver DR.

Abstract: Selective blocking is applied to discrete segments of scan chains in the integrated circuit device. In some implementations, locking components associated with the scan segments are selectively activated according to blocking data incorporated in test pattern data. In other implementations, selective blocking is applied to the scan cells identified as causing the highest power consumption. Selective incorporation of blocking components in an integrated circuit device is based on statistical estimation of scan cell transition rates. When the blocking components are enabled, pre-selected signal values are presented to the functional logic of the integrated circuit device. At the same time, propagation of output value transitions that may take place in the scan cells is prevented.

Abstract: Provided is a test apparatus that tests a device under test having a plurality of output terminals. The test apparatus comprises an executing section that executes a test command sequence for testing the device under test; a storage section that stores a plurality of pieces of setting data designating one or more output terminals among the plurality of output terminals; a detecting section that detects whether a value of an output signal from an output terminal designated by one of the pieces of setting data matches an expected value; and a selecting section that selects different pieces of setting data in the storage section when at least two detection commands, which change execution sequencing of the test command sequence according to the detection results of the detecting section, are executed, and supplies the selected pieces of setting data to the detecting section.

Abstract: Methods and systems to measure a signal on an integrated circuit die. An on-die measurement circuit may measure an on-die signal relative to an off-die generated reference signal, which may include a series of increasing voltage steps. The on-die measurement circuit may continuously compare voltages of the on-die signal and the off-die generated reference signal, and may generate an indication when the off-die reference signal exceeds the on-die signal. The measurement circuit may generate the indication from a voltage source other than the on-die signal to be measured, and/or may generate the indication with a relatively large voltage swing. The indication may be output off-die for evaluation, such as for testing, debugging, characterization, and/or operational monitoring. A unity gain analog buffer may be provided to tap the on-die signal proximate to a node of interest, which may be implemented within the on-die measurement circuit.

Abstract: A re-configurable test circuit for use in an automated test equipment includes a test circuit, a test processor and a programmable logic device. The pin electronics circuit is configured to interface the re-configurable test circuit with a DUT. The test processor includes a timing circuit configured to provide one or more adjustable-timing signals having adjustable timing. The programmable logic device is configured to implement a state machine, a state sequence of which depends on one or more input signals received from the pin electronics circuit, to provide an output signal, which depends on a current or previous state of the state machine, to the pin electronics circuit in response to the signal(s) received from the pin electronics circuit. The test processor is coupled to the programmable logic device to provide at least one of the adjustable-timing signal(s) to the programmable logic device to define timing of the programmable logic device.

Abstract: A 3D-IC detector for each layer of a stacked device comprises a pulse generator to receive an initial signal and generate a pulse-in signal to a next stage detector. A latch is coupled to the pulse generator to receive an output signal from the pulse generator and generate a layer identifying signal. A counter is coupled to previous stage detector and the initial signal to perform a counting operation; and an adder coupled to the counter to add a number to a counting output from the counter and input added signal to the pulse generator.

Abstract: The present invention discloses a method of testing a partially assembled multi-die device (1) by providing a carrier (300) comprising a device-level test data input (12) and a device-level test data output (18); placing a first die on the carrier, the first die having a test access port (100c) comprising a primary test data input (142), a secondary test data input (144) and a test data output (152), the test access port being controlled by a test access port controller (110); communicatively coupling the secondary test data input (144) of the first die to the device-level test data input (12), and the test data output (152) of the first die to the device-level test data output (18); providing the first die with configuration information to bring the first die in a state in which the first die accepts test instructions from its secondary test data input (144); testing the first die, said testing including providing the secondary test data input (144) of the first die with test instructions through the device-

Abstract: A feed device for the automatic shifting of objects is provided. The feed device includes a storage area or a holding element and a driven feed unit by means of which an object arranged on the storage area or at the holding element of the feed device can be shifted when the feed unit engages at the object, and wherein the feed device includes at least one electronic component which electronically detects a movement of the feed unit. The electronic component is configured such that the covering of a distance by the feed unit during movement of the feed unit is directly detected as an electric pulse and that the covering of respectively predefined distances of the feed unit generates a pulse sequence characteristic for the distances covered by the electronic component having different contact device at which in each case a pulse is generated which is characteristic for the respective contact device when the feed unit has covered a predefined distance.

Abstract: A system and method for electrostatic discharge (ESD) testing devices under test (DUTs) uses an ESD gun attached to a robotic arm to execute ESD tests. The system and method also uses cameras positioned around a DUT placed on a testing table to define at least one test point on a surface of the DUT. Using the defined test point, as well as settings on the ESD gun and a testing process scenario that includes actions to be executed by the system, the testing process is performed by the system.

Abstract: An electronic probe housing having two speed pick up devices automatically sends electric signals to an electronic governor which causes the RPM of the steam turbine to increase, decrease or remain constant, in conjunction with one or more additional speed pick up devices in the same probe housing which uses a logical array of electro-hydraulic solenoid valves to control an automatic shut off system which cuts off the steam supply to the steam turbine.

Abstract: A system and method for checking a ground via of control chips of a printed circuit board (PCB) provides a graphical user interface (GUI) displaying a layout of the PCB. The control chip has a plurality of ground pins. The computer searches for signal path routing of each ground pin and ground vias along each signal path routing of each ground pin. If there are any ground vias having the same absolute coordinates, the computer determines that the ground vias are shared by more than one ground pin.

Abstract: A signal processing section included in a semiconductor testing circuit supplies a test signal inputted from a tester via a signal line to a plurality of DUTs and generates a test result by synthesizing response signals transmitted from the plurality of DUTs on the basis of the test signal. A test result output section included in the semiconductor testing circuit makes a voltage level of the test result differ from a voltage level of the test signal inputted and outputs the test result to the tester via the signal line.

Abstract: A novel method for manufacturing embedded a capacitive stack and a novel capacitive stack apparatus are provided having a capacitive core that serves as a structural substrate on which alternating thin conductive foils and nanopowder-loaded dielectric layers may be added and tested for reliability. This layering and testing allows early fault detection of the thin dielectric layers of the capacitive stack. The capacitive stack may be configured to supply multiple isolated capacitive elements that provide segregated, device-specific decoupling capacitance to one or more electrical components. The capacitive stack may serve as a core substrate on which a plurality of additional signaling layers of a multilayer circuit board may be coupled.

Abstract: A performance testing framework enables multiple components working together to test a deployed application automatically in an unattended manner and to analyze the test results easily. At very high level, the performance testing framework can run performance tests on a tested system with one or more variations without user intervention and save the test results and configuration metadata to a database for later analysis. Each of the variations is composed of a set of logical dimensions and values associated with each of those dimensions to be tested.

Abstract: Embodiments of the invention include an electronic load having variable reactive load capability and techniques for controlling and/or modeling a reactive component in a load. The electronic load can include a user interface through which a latency value is received from a user. A delay is created based on the latency value between the time that a variable of the input signal is sensed and the time that a variable of the input signal is driven to a new value, thereby simulating a reactive component in the electronic load based on the created delay. In one example embodiment, the driven variable can be stepped after the created delay to produce an approximation of a capacitive or inductive element. In another example embodiment, the driven variable can be slewed during the delay period using an arbitrary waveform generator, thereby more accurately simulating the reactive component.

Abstract: The apparatus is provided with an abnormality determination means for determining abnormality of the apparatus where two different combinations of two electrodes are selected from the three electrodes, an alternating-current voltage is applied to an electrode in one combination by the voltage-applying portion to measure a value of a current flowing to the other electrode via the dielectric body by electrostatic coupling, an alternating-current voltage is applied to an electrode in another combination out of the at least two different combinations by the voltage-applying portion to measure a value of a current flowing to the other electrode via the dielectric body by electrostatic coupling, and an abnormality of the apparatus is determined from the current values measured.

Abstract: An input power measuring device includes a board with an edge connector, a first dual inline memory modules (DIMM) socket, a resistor, a differential amplifier circuit, a voltage dividing circuit, a display screen, and a controller. When the edge connector is inserted into a second DIMM socket of a motherboard and the motherboard is powered on, the resistor samples first current, and converts the first current into a first voltage. The differential amplifier circuit amplifiers the first current to a second current. The voltage dividing circuit divides the first voltage, and outputs a second voltage. The controller converts the second current into a third current, converts the second voltage into a third voltage, and calculates a power according to the third current and the third voltage.

Abstract: A method for determining an offset of a periodic signal is provided, wherein an offset value caused by a level change of the periodic signal is suppressed. The periodic signal is fed to first and second integrators and to a periodicity recognition unit, wherein the first integrator is integrated over a full period. The second integrator is integrated over a full period offset by a half period. Starting times of integrations are controlled by the periodicity recognition unit. Output signals of the integrators are stored in two memories, wherein the output signals are summed and a sum signal represents the offset of the periodic signal. The output signals are fed to a comparator circuit. The sum signal is stored in a further memory as an output signal, wherein the comparator circuit triggers the further memory to continue outputting a value of the output signal stored in the further memory.

Abstract: A signal switching device connected between at least one electronic device and a testing device includes a switching module and a control unit connected to the switching module. Each electronic device is capable of outputting a first signal and a second signal. The switching module is connected to each electronic device. When the switching device is in a first state, the switching module receives the first signal, and the control unit controls the switching module to transmit the first signal to the testing device. When the switching module is in a second state, the switching module receives the second signal, and the control unit controls the switching module to transmit the second signal to the testing device.

Abstract: A method, and corresponding apparatus, for testing an aircraft control system is disclosed. The method includes simultaneously coupling a test device to a plurality of separate test points in an aircraft control system, selecting each test point individually such that the test device is enabled for electrical connection with the selected test point, conducting a test on the control system at each selected test point using the test device, detecting a signal or voltage at the selected test point, and indicating a result of the test at the selected test point to an operator.

Abstract: A 3D-IC detector for each layer of a stacked device with N layer, includes a dividing-two circuit coupled to a (N?1) signal; a first comparator is coupled to the dividing-two circuit, wherein an input A is coupled to an initial layer number signal, an input B of the first comparator is coupled to an output of the dividing-two circuit; a second comparator is coupled to the initial layer number by an input A of the second comparator, and a num is coupled to an input B of the second comparator; a first Add/sub circuit is coupled to the num via an input A of the first Add/sub circuit, and coupled to the first comparator via an input B of the first Add/sub circuit, to the second comparator via an input +/? signal of the first Add/sub circuit; and a second Add/sub circuit coupled to the first comparator via an input A of the second Add/sub circuit, to the num via an input B of the second Add/sub circuit.

Abstract: A test system that provides an output signal for analysis without requiring the test hardware to be idle during a settling interval. The test system includes a preprocessor that identifies the near-DC drift that occurs in the output signal and then adjusts the output signal to remove the near-DC drift. A set of values representing the near-DC drift at each of multiple times during the acquisition of a signal for analysis may be computed and used to model a settling profile of the signal by fitting a curve to the set of values. The model of the settling profile may then be subtracted from samples representing the output signal to provide an adjusted signal for further analysis.

Abstract: A digital signal generator includes an input unit configured to receive signal information of a target data signal, a controller configured to calculate at least two delay values and at least two data values, the at least two delay values and the at least two data values being used to generate a data signal corresponding to the signal information input through the input unit, a multi-phase clock generator configured to delay a reference clock signal based on the at least two delay values to generate at least two clock signals having different phases, a signal generator configured to generate at least two data signals by assigning the at least two data values to the at least two clock signals, and a logic gate unit configured to generate the data signal corresponding to the signal information input through the input unit based on the at least two data signals.

Abstract: A system for testing a DC power supply performance includes a load module electrically coupled to the DC power supply, a switch module electrically coupled to the DC power supply, a control module electrically coupled to the load module and the switch module respectively, and an indication module electrically coupled to the control module. The control module includes a judge module and a comparison module. The judge module is configured for receiving DC voltage signals from the DC power supply; wherein the judge module is capable of turning on when the DC power supply is normal. The comparison module is configured for comparing the DC voltage signals with a reference voltage; wherein the comparison module is capable of outputting a control signal when the DC voltage signals are greater than the reference voltage. The indication module is configured for receiving the control signal and indicating status of the DC power supply.

Abstract: Provided is a test apparatus that tests a device under test, comprising a plurality of test modules that test the device under test; a synchronization module that is connected to each of the plurality of test modules, and that synchronizes the plurality of test modules; and a test control section that is connected to the plurality of test modules and the synchronization module, and that controls the test modules and the synchronization module. The synchronization module includes a receiving section that receives, from each of the plurality of test modules, a state signal indicating a state of the test module; an aggregating section that generates an aggregate state signal by calculating an aggregate of the state signals received by the receiving section; and a transmitting section that transmits, to the plurality of test modules, a control signal ordering an operation corresponding to the aggregate state signal.

Abstract: A method and apparatus which provide for measurement of embedded EMH, HIRF, or EMI (collectively referred to herein as EMH components), non-destructive measurement of embedded EMH components, component determination using only a simple current measurement; component determination without a priori knowledge of the range of values, the architecture of the test circuit that uses three MOSFET (or equivalent), switches, current measuring circuits, and suitable timing to accurately determine the component values, measurement of an embedded capacitor with relatively unknown parallel load resistance, and/or non-destructive measurement of R/C/TPD type components for any application.

Abstract: Multiple test pins receive, as input data, multiple data output from a DUT. Multiple multiplexers receive the multiple data input to the multiple test pins and selects one of the data thus input, and outputs the data thus selected. Multiple logical comparators are respectively provided for the multiple multiplexers and judge whether or not the data selected by the corresponding multiplexers match the expected values.

Abstract: A testing circuit for verifying the impedance of off-chip drivers includes: a plurality of off-chip drivers (OCD), each off-chip driver including a through-silicon via (TSV); an IREF test pad, for driving a current to the plurality of off-chip drivers; a plurality of pre-drivers, each respective pre-driver coupled to one of the plurality of off-chip drivers, wherein the plurality of pre-drivers are configured to turn on the off-chip drivers; a VREF test pad, for inputting a reference voltage to the testing circuit; a plurality of input buffers (IB) for outputting a plurality of comparison results, each of the plurality of input buffers configured to output the plurality of comparison results according to the reference voltage and the voltage at the TSV nodes; and a test pad, coupled to the plurality of IBs, for receiving the comparison results to determine whether the impedance of each OCD is within a desired range.

Abstract: An integrated circuit capable of monitoring analog voltages inside an analog block is presented. The integrated circuit has an analog test multiplexer (mux) whose inputs are connected to analog voltages of interest inside an analog block. The analog test multiplexer directs a selected analog voltage from an analog block to the output of the analog test mux. The integrated circuit further includes an analog monitor state machine which provides the selection bits to the analog test multiplexer, enabling random access to the analog voltages inside the analog block. The integrated circuit also includes an analog to digital converter for converting the selected analog voltage from the analog test multiplexer into a digital representation.

Abstract: An Analog/mixed signal automatic test system includes a software architecture that creates a virtual composite instruments through novel software dynamic allocation of low level resources. These virtual composite instruments provide backwards and forwards compatibility to a variety of automatic test equipment, known or available on the market. The virtual composite instruments are free from the normal constraints imposed by hardware implementations. Creation of the virtual composite instruments allows a single piece of automatic test equipment system to emulate many implementations of automatic test equipment, providing higher utilization, and therefore a lower cost test solution for device manufacturers. The test instruments are preferably object controls and are preferably instantiated and controlled by the test system server. This allows multiple users to control the tester simultaneously across, for example, the Internet.

Abstract: Provided is a test apparatus for testing a device under test, including: a plurality of test modules that exchange signals with the device under test; a bus to which the plurality of test modules are connected; and a test control section that controls the plurality of test modules via the bus, where each of the plurality of test modules includes: a test section that exchanges signals with the device under test, and a module control section that controls the test section, and the module control section of each test module exchanges signals with the module control section of another test module, via the bus.

Abstract: Provided is a test apparatus and a test method related to the test apparatus for testing a device under test, including: a plurality of test modules that exchange a signal with the device under test; a test control section that outputs a group read instruction for collectively reading data stored in two or more of the test modules; and a control interface section that reads the data from the two or more test modules according to the group read instruction, and collectively sends the read data to the test control section.

Abstract: A system and method for reducing timing errors in automated test equipment (ATE) offering increased data rates for the testing of higher-speed integrated circuits. Embodiments provide an effective mechanism for increasing the data rate of an ATE system by delegating processing tasks to multiple test components, where the resulting data rate of the system may approach the sum of the data rates of the individual components. Each component is able to perform data-dependent timing error correction on data processed by the component, where the timing error may result from data processed by another component in the system. Embodiments enable timing error correction by making the component performing the correction aware of the data (e.g., processed by another component) causing the error. The data may be shared between components using existing timing interfaces, thereby saving the cost associated with the design, verification and manufacturing of new and/or additional hardware.

Abstract: An LSI test apparatus includes a test circuit synthesizing unit that synthesizes a test circuit and inserts the test circuit in a pre-test-synthesis net list; a test pattern generating unit that, based on a post-test-synthesis net list acquired by the test circuit synthesizing unit, generates a test pattern that simultaneously activates selected gated clock buffers; a simulating unit that, using the test pattern generated by the test pattern generating unit, simulates operation of a circuit created from the post-test-synthesis net list; and a power source analyzing unit that analyzes voltage drop in terms of amount, based on operation rate information acquired by the simulating unit.

Abstract: Disclosed herein is a method of inspecting defects in a circuit pattern of a substrate. At least one laser beam radiation unit for radiating a laser beam onto an inspection target circuit pattern of a substrate in a non-contact manner is prepared. A probe beam radiation unit for radiating a probe beam onto a connection circuit pattern to be electrically connected to the inspection target circuit pattern in a non-contact manner is prepared. The laser beam is radiated onto the inspection target circuit pattern using the laser beam radiation unit. The probe beam is radiated onto the connection circuit pattern using the probe beam radiation unit, thus measuring information about whether the probe beam is diffracted, and a diffraction angle. Accordingly, the method can solve problems such as erroneous measurements caused by contact pressure and can reduce the time required for measurements.

Abstract: An intelligent switching unit to be connected with a processing unit is disclosed. The intelligent switching unit includes a switching unit to be actuated by a user, a detection module connected to the switching unit. The detection module detects a signal outputted by the switching unit and provides a detected signal representative of the signal outputted by the switching unit. The intelligent switching unit further comprises a communication module for receiving and transmitting the detected signal to the processing unit.

Abstract: Provided is a test apparatus that tests a device under test having a test function for sequentially outputting, from a single test terminal, signals that would be output from a plurality of terminals, the test apparatus comprising: a test section that supplies the device under test with a test signal and receives signals that are sequentially output from the test terminal in response to the test signal; an identifying section that identifies a correspondence between each signal sequentially received by the test section and a signal that would be output from one of the terminals of the device under test; and a counting section that counts a number of signals judged to be unacceptable from among the signals sequentially received by the test section for each terminal of the device under test, based on the correspondence identified by the identifying section.

Abstract: The present invention refers to a method for the precise measurement of dependency on amplitude and phase of a plurality of high frequency signals, preferably in the synchrotron accelerator of elementary particles. The essence of the solution according to the invention lies in that with a single measuring device and without any aliasing it is achieved a resolution of 0.2 micron and repeatability of measurements of 1 micron down to the lower frequency limit of a few MHz.

Abstract: A high-definition multimedia interface circuit uses a high-definition multimedia interface encoder to produce a plurality of channels of data. An output circuit, connected to the high-definition multimedia interface encoder, produces a plurality of channels of high frequency data from the data produced by the high-definition multimedia interface encoder. A multiplexer selects a channel for sampling, and a capacitive coupler capacitively couples the multiplexer to a sampling circuit. The sampling circuit produces sampled data corresponding to the high frequency data having a clock rate less than a clock rate of the high frequency data. A test circuit compares the sampled data with the data produced by the high-definition multimedia interface encoder.

Abstract: An arrangement to determine at least one electrical feature of an electrical device including a signal injection unit configured to inject first and second test signals into the electrical device, a signal conversion unit configured to measure electrical qualities in electrical circuits resulting from the test signals, and a processing device including at least two input channels configured to receive the measured electrical quantities and to determine the electrical feature based on the measured electrical quantities. The arrangement further may include a mixing unit configured to add the measurements of a first electrical quantity determined from the test signals and based thereon generate a first mixed signal, to add the measurements of a second electrical quantity from the test signals and based thereon generate a second mixed signal, and to supply the first and second mixed signals to first and second input channels.

Abstract: An embodiment of the invention provides an integrated circuit. The integrated circuit has an analog device-under-test (DUT), a memory receiving and storing a test program and a processor. The processor tests the analog DUT and outputs a test result in digital format by executing the test program, wherein the test result indicates whether the analog DUT workable according to a specification.

Abstract: An analysis tool which extracts all the available parameter identifications (i.e. PIDS) from a vehicle's power train control module for diagnostic decisions. This is done by checking these PIDS and other information (e.g., calculated PIDS, Break Points, charts and algorithms) in three states; key on engine off, key on engine cranking, key on engine running. In all three modes the tool is comparing the live data from PIDS and voltage to the other information (e.g., Break Points). If any of this data are outside the programmed values a flag is assigned to the failure or control problem. The relationship between a particular PID and its associated preprogrammed value(s) may be indicated by a light. The depth of the problem (if any) is conveyed by the color of the light. Also included are tests/charts for fuel trim, engine volumetric efficiency, simulated injector, power, catalyst efficiency, and engine coolant range.

Abstract: Provided is a driver circuit that outputs a transmission signal according to a reception signal received from outside, including a first driver that outputs a voltage according to an input first signal; a second driver that receives the voltage output by the first driver as a power supply voltage and outputs the transmission signal according to the power supply voltage and an input second signal; and a control section that delays both the first signal and the second signal, according to a change of the reception signal, and causes the transmission signal according to the reception signal to be output from the second driver.