By Fluid Patents (Class 324/750.08)
  • Patent number: 11307248
    Abstract: A contacting unit (30) for a test handler (100) for carrying out functional tests on semiconductor elements having a surface, in particular on ICs (200), has a contacting module (60).
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: April 19, 2022
    Inventors: Helmuth Heigl, Hubertus Heigl
  • Patent number: 11226362
    Abstract: A system-level testing apparatus and a system-level testing system are provided. The system-level testing apparatus includes an apparatus body, a chip carrying device, and a control device. A holding structure in the apparatus body is configured to hold a system circuit board. The chip carrying device includes a carrying circuit board, and a plurality of electrical connection sockets and a plurality of connection structures are disposed on the carrying circuit board. The electrical connection structures are electrically connected to the connection structures. When the electrical connection sockets carry a plurality of chips under test, the carrying circuit board is disposed on the system circuit board, and the connection structures are connected to a plurality of system connection structures of the system circuit board, the control device can transmit a test signal to perform a system-level test operation to the system circuit board and the chips under test.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: January 18, 2022
    Assignee: ONE TEST SYSTEMS
    Inventors: Chen-Lung Tsai, Gene Rosenthal
  • Patent number: 11209477
    Abstract: The present disclosure provides a testing fixture for holding a device under test (DUT). The testing fixture includes a base, a frame, a recessed portion, a plurality of sets of electrical contacts and a plurality of electrical lines. The frame extends upward along an outer perimeter of an upper surface of the base. The recessed portion is surrounded by the frame and the upper surface of the base, and the DUT is received in the recessed portion. The plurality of sets of electrical contacts are disposed on the recessed portion and arranged in a rotationally symmetrical manner, wherein a plurality of plated through holes of the DUT are in contact with one set of the electrical contacts after the DUT is assembled with the testing fixture.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: December 28, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ching-Chung Wang, Jui-Hsiu Jao
  • Patent number: 11162996
    Abstract: A probing apparatus includes a carrier having an opening, a supporter disposed on the carrier in a way that its bottom surface faces toward the carrier, its top surface for disposition of a wafer, and its light permeable portion allowing light to pass through the top and bottom surfaces corresponding in position to the opening, an air heating device having a covering plate and an air supply unit, and a probing device having a probe protruding out of the bottom surface of the air heating device. A thermal air source provides thermal air to a heating space between the bottom surface of the air heating device and the top surface of the supporter through an air supply passage of the air supply unit. The probing apparatus can test light emitting efficiency of a light emitting chip in the wafer and heat the chip at the same time.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: November 2, 2021
    Assignee: MPI CORPORATION
    Inventors: Wen Pin Chuang, Yi Ching Lo, Hao Duan
  • Patent number: 11092642
    Abstract: An electronic component handler including a first holding section and a second holding section holding an electronic component by adsorption, a suction section giving the first holding section and the second holding section an adsorption force to adsorb the electronic component, a suction flow path, a first branch flow path, a second branch flow path, a first opening/closing section opening and closing the first branch flow path, a second opening/closing section opening and closing the second branch flow path, a first pressure measurement section measuring first pressure inside the first branch flow path, a second pressure measurement section measuring second pressure inside the second branch flow path, and a control section, in which the control section opens the first branch flow path by the first opening/closing section and causes the first holding section to adsorb the electronic component, and checks whether or not the first pressure is lower than preset pressure when the second branch flow path is opene
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: August 17, 2021
    Inventor: Makoto Yanagisawa
  • Patent number: 11061067
    Abstract: An apparatus and a method provide a high temperature test and a low temperature test. The apparatus mainly includes a depressing head and a test base, wherein the depressing head includes a cooling module, a heating module, and a heat dissipation module therein, the heat dissipation module includes a finned heat sink and a heat conduction member, and the heat conduction member is thermally coupled to the heating module and the finned heat sink. When the low temperature test is performed, an electronic component is cooled by filling liquid nitrogen into the cooling module of the depressing head. When the high temperature test is performed, the electronic component is heated by the heating module. If the temperature of the electronic device is higher than a predetermined high temperature, the electronic device is cooled by the heat dissipation module.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: July 13, 2021
    Assignee: CHROMA ATE INC.
    Inventor: Xin-Yi Wu
  • Patent number: 11054810
    Abstract: A system utilized for freezing parts of electronic mobile devices comprises a freezing machine incorporating internet communication hardware and software, molds and vacuum bags and a central computer server hosting and operating a web-centric and/or mobile app software application which connects to, updates and operates the freezing machine via the Internet. The freezing machine comprises a housing, an engine with cylindrical cooling head, an adjustable cooling head ring fixture and metal plate attached to the adjustable cooling head ring fixture. The freezing machine further comprises an encapsulation chamber, a lid, a power inlet, a LCD/OLED display and a PCB with processor capable of operating the freezing machine.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: July 6, 2021
    Inventors: Georgios Christodouloy Hajipetrou, Hans Claussen, Charalampos Kalyvas
  • Patent number: 11027310
    Abstract: The present disclosure relates to a method of depositing a fluid onto a substrate. In some embodiments, the method may be performed by mounting a substrate to a micro-fluidic probe card, so that the substrate abuts a cavity within the micro-fluidic probe card that is in communication with a fluid inlet and a fluid outlet. A first fluidic chemical is selectively introduced into the cavity via the fluid inlet of the micro-fluidic probe card.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Wen Cheng, Jung-Huei Peng, Yi-Shao Liu, Fei-Lung Lai, Shang-Ying Tsai
  • Patent number: 10892237
    Abstract: Methods of fabricating a semiconductor device are provided. The method includes providing a plurality of semiconductor devices. The method further includes disposing a dielectric dry film on the plurality of semiconductor devices, wherein the dielectric dry film is patterned such that openings in the patterned dielectric dry film are aligned with conductive pads of each of the plurality of semiconductor devices.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: January 12, 2021
    Assignee: General Electric Company
    Inventors: Stephen Daley Arthur, Liangchun Yu, Nancy Cecelia Stoffel, David Richard Esler, Christopher James Kapusta
  • Patent number: 10685891
    Abstract: A semiconductor test system has a film frame including a tape portion with one or more openings through the tape portion. The opening is disposed in a center region of the tape portion of the film frame. The film frame may have conductive traces formed on or through the tape portion. A thin semiconductor wafer includes a conductive layer formed over a surface of the semiconductor wafer. The semiconductor wafer is mounted over the opening in the tape portion of the film frame. A wafer probe chuck includes a lower surface and raised surface. The film frame is mounted to the wafer probe chuck with the raised surface extending through the opening in the tape portion to contact the conductive layer of the semiconductor wafer. The semiconductor wafer is probe tested through the opening in the tape portion of the film frame.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: June 16, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Heng Chen Lee
  • Patent number: 10677737
    Abstract: A test fixture for inspecting joints of fuse assemblies may bend a fuse assembly at a target angle for inspection. The test fixture may include a base and a guide. The base may feature surfaces angled at the target angle. The guide at least partially overhangs the base to form a channel. The guide may include structures to align on the base and inspect the fuse assembly.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: June 9, 2020
    Assignee: Merit Medical Systems, Inc.
    Inventor: Frank Gazzano
  • Patent number: 10605829
    Abstract: The present invention provides a prober and a transfer unit being capable of improving throughput at each of the measurement units. The prober includes a transfer object housing that houses a plurality of transfer objects, the plurality of measurement units, the transfer unit that moves between the transfer object housing for housing the plurality of transfer objects and the plurality of measurement units to transfer the transfer objects into the transfer object housing or each of the measurement units, and a moving device. The transfer unit includes environment controller configured to control an environment in a casing, and air curtain formation means for causing the casing to be in a sealed or a substantially sealed state.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: March 31, 2020
    Assignee: Tokyo Seimitsu Co., Ltd.
    Inventors: Kentaro Sakai, Takekiyo Ichikawa
  • Patent number: 10571486
    Abstract: The present invention provides a prober and a transfer unit being capable of improving throughput at each of the measurement units. The prober includes a transfer object housing that houses a plurality of transfer objects, the plurality of measurement units, the transfer unit that moves between the transfer object housing for housing the plurality of transfer objects and the plurality of measurement units to transfer the transfer objects into the transfer object housing or each of the measurement units, and a moving device. The transfer unit includes environment controller configured to control an environment in a casing, and air curtain formation means for causing the casing to be in a sealed or a substantially sealed state.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: February 25, 2020
    Assignee: Tokyo Seimitsu Co., Ltd.
    Inventors: Kentaro Sakai, Takekiyo Ichikawa
  • Patent number: 10539593
    Abstract: The present invention provides a prober and a transfer unit being capable of improving throughput at each of the measurement units. The prober includes a transfer object housing that houses a plurality of transfer objects, the plurality of measurement units, the transfer unit that moves between the transfer object housing for housing the plurality of transfer objects and the plurality of measurement units to transfer the transfer objects into the transfer object housing or each of the measurement units, and a moving device. The transfer unit includes environment controller configured to control an environment in a casing, and air curtain formation means for causing the casing to be in a sealed or a substantially sealed state.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: January 21, 2020
    Assignee: Tokyo Seimitsu Co., Ltd.
    Inventors: Kentaro Sakai, Takekiyo Ichikawa
  • Patent number: 10520544
    Abstract: A chip package assembly testing system and method for testing a chip package assembly are provided herein. In one example, an IC test system is provide that includes a robot, an input queuing station, an output queuing station, and a test station. The test station includes a first and second test interfaces. The first test interface is configurable to receive and communicatively connect with a first chip package assembly having one arrangement of solder ball connections. The second test interface is configurable to receive and communicatively connect with a second chip package assembly having a different arrangement of solder ball connections. The test station also includes a first test processor configured to test the chip package assembly connected through the first interface utilizing a predetermined first test routine and a second test processor configured to test the chip package assembly connected through the second interface utilizing a predetermined second test routine.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: December 31, 2019
    Assignee: XILINX, INC.
    Inventor: Mohsen H. Mardi
  • Patent number: 10514389
    Abstract: The present invention provides a prober and a transfer unit being capable of improving throughput at each of the measurement units. The prober includes a transfer object housing that houses a plurality of transfer objects, the plurality of measurement units, the transfer unit that moves between the transfer object housing for housing the plurality of transfer objects and the plurality of measurement units to transfer the transfer objects into the transfer object housing or each of the measurement units, and a moving device. The transfer unit includes environment controller configured to control an environment in a casing, and air curtain formation means for causing the casing to be in a sealed or a substantially sealed state.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: December 24, 2019
    Assignee: Tokyo Seimitsu Co., Ltd.
    Inventors: Kentaro Sakai, Takekiyo Ichikawa
  • Patent number: 10481555
    Abstract: A dual bellows system and method that includes a main bellows which interacts with a thermally compensating bellows, whereby interaction of the main bellows with the thermally compensating bellows results in a transfer of force and/or displacement that is insensitive to temperature changes.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: November 19, 2019
    Assignee: PRECIFLEX SA
    Inventor: Lucien Vouillamoz
  • Patent number: 10466299
    Abstract: An electronic test apparatus is adapted for testing an electronic component which includes a circuit substrate and a plurality of contact electrodes disposed on the circuit substrate. The electronic test apparatus includes a test seat and a plurality of spring probes. The test seat includes a metallic main body that has a first side adapted to be in contact with the circuit substrate and a second side opposite to the first side, and that is formed with a plurality of spaced-apart probe holes extending through the first and second sides, and a temperature sensor disposed in the metallic main body. The spring probes are adapted to be electrically connected to the contact electrodes and each is positioned in a respective one of the probe holes.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: November 5, 2019
    Assignee: WINWAY TECHNOLOGY CO., LTD.
    Inventors: Kuan-Chung Chen, Cheng-Hui Lin, Chia-Pin Sun
  • Patent number: 10401423
    Abstract: An example test system includes: a test slot to hold a device under test (DUT); a temperature control system comprising a phase-change material, with the temperature control system for maintaining a temperature of the phase-change material in a steady-state condition, with the phase-change material changing phase during a transient condition to affect a temperature of a thermally-conductive structure, and with the steady-state condition being longer in duration than the transient condition; and an air mover to direct air over the thermally-conductive structure and towards the DUT in the test slot in order to affect a temperature of the DUT.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: September 3, 2019
    Assignee: Teradyne, Inc.
    Inventors: Larry Akers, Joseph Wrinn, Philip Campbell, David Graziose
  • Patent number: 10359448
    Abstract: Provided is a probe position inspection device that can inspect with ease and higher precision a position of a probe included in a semiconductor evaluation apparatus. The probe includes an inspection magnetic field producing part that produces a magnetic field corresponding to a contact point with a subject semiconductor apparatus. The probe position inspection device includes: a base part having a front surface that can be contacted by the probe, and including a plurality of magnetic field sensors placed in a plane parallel to the front surface, each of the magnetic field sensors sensing the magnetic field produced by the inspection magnetic field producing part; and an output part electrically connected to the magnetic field sensors, the output part outputting, based on the magnetic field, a signal corresponding to each of the magnetic field sensors.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: July 23, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Akira Okada, Takaya Noguchi, Norihiro Takesako
  • Patent number: 10338101
    Abstract: Provided is a prober capable of maintaining parallelism between a probe card and a wafer as well as performing wafer-level inspection with high accuracy. A test head is held by a test head holding part, and the test head and a probe card are sucked and fixed to a pogo frame attached to a head stage. A wafer chuck is moved toward a probe card while being fixed to a Z-axis movement-rotation unit in a detachable manner, and the wafer chuck is drawn toward the probe card by reducing pressure in an air-tight space formed between the wafer chuck and the probe card using a pressure reducing unit. Then, an electrical inspection of a wafer is performed while the test head, the pogo frame, the probe card, and the wafer chuck are integrated with respect to the head stage.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: July 2, 2019
    Assignee: Tokyo Seimitsu Co., Ltd.
    Inventor: Hiroo Tamura
  • Patent number: 10241149
    Abstract: A massively parallel wafer-level reliability system to test a reliability of wafers includes: a test platform; stations disposed on the test platform, wherein an individual test station receives a wafer and includes: a chuck disposed on the test platform; a probe including contactors that electrically contact the wafer; and a temperature controller to control a temperature of the wafer; a control platform disposed among the test stations; and a system controller to independently control the test stations and that is in electrical communication with the temperature controller, wherein the reliability of the wafers is tested in parallel by the test stations.
    Type: Grant
    Filed: September 24, 2016
    Date of Patent: March 26, 2019
    Assignee: THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY OF COMMERCE
    Inventor: Kin P. Cheung
  • Patent number: 10073442
    Abstract: A system for qualifying a process in a facility. The system includes a validation system and a portable computer device. The validation system includes a storage device, a processing device, and one or more sensor input modules each connected to one or more sensors. The portable computer device includes a storage device and a processing device. The storage device of the portable computer device includes a database comprising configuration file for configuring the validation system to perform a qualification of the asset. The processing device of the portable computer device is configured to transmit the configuration file to the validation system for storage in the storage device thereof. The processing device of the validation system is configured to load the configuration file stored in the storage device thereof and to perform the qualification of the asset based on the loaded configuration file.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: September 11, 2018
    Assignee: Amphenol Thermometrics, Inc.
    Inventors: Dennis Plante, Frank Kies, Himangshu Chowdhury, Volker Luebcke
  • Patent number: 10041894
    Abstract: Determining an in-plane thermal conductivity of anisotropic materials, such as display stacks, printed circuit boards (PCBs), and composite housings, includes heating a first region of an anisotropic sample, cooling a second region of the sample, and measuring temperature at a first location between the first region and the second region and a second location between the first region and the second region. The in-plane thermal conductivity of the sample is computed based at least in part on the temperature at the first location, the temperature at the second location, the distance from the first region to the second region, a thickness of the substantially planar anisotropic substrate, and an amount of heat applied to the first region.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: August 7, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Mohammed Aftab Alam, Bradley David Urban, Gaurav Soni, Ramez Nachman
  • Patent number: 10036591
    Abstract: A temperature controlling equipment includes a connection head of a fluid output device, an isolation hood, a drying chamber and a dry air source. The connection head of the fluid output device has an output nozzle and a first fluid output pipe. The isolation hood has a hood body and a second fluid output pipe. The hood body defines a working space. The output nozzle is communicated with the working space. The second fluid output pipe is communicated with the working space and the first fluid output pipe. The first fluid output pipe and the second fluid output pipe have a connection interface in between. The connection interface is at least partially located in the drying chamber. The dry air source is communicated with the drying chamber and is configured to provide a dry air to the drying chamber.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: July 31, 2018
    Assignee: MPI Corporation
    Inventors: Yueh-Ying Lee, Helge Jacob Krystad, Ying-Chiao Chang
  • Patent number: 9970960
    Abstract: A probe having a sliding rail is provided and includes a probe head, a probe tail, an elastic element made of an elastic material and connected between the probe head and the probe tail, and a sliding rail assembly. The sliding rail assembly includes a slide rail and a position limit protrusion. The slide rail has a fixed end and a free end. The fixed end is fixedly connected to the probe tail, and the free end extends to the probe head. The position limit protrusion is fixedly connected to the probe head, and has a sliding slot formed thereon through which the slide rail can pass. The sliding rail assembly is made of a conductive material, and a cross-section area of the slide rail is greater than a cross-section area of the elastic material of the elastic element.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: May 15, 2018
    Assignee: CHUNGHWA PRECISION TEST TECH. CO., LTD.
    Inventor: Chih-Peng Hsieh
  • Patent number: 9805147
    Abstract: An object of the present invention is to provide an EMC design technique of a device including an electronic device mounted therein for implementing noise amount analysis of a system in which individual electronic devices are combined. A housing model is acquired, component models are selected and acquire, the acquired component models are connected using a wire, the acquired component models are arranged in the acquired housing model, the arranged component models connected using the wire is driven to generate electromagnetic noise from the component models and the wire, the generated electromagnetic noise is propagated in the housing model to calculate a noise amount, and an output process of outputting data of the calculated noise amount is performed. Thus, even in the system in which a plurality of electronic devices are combined, electromagnetic noise analysis of the system can be easily performed, and a noise reduction design can be supported.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: October 31, 2017
    Assignee: Hitachi, Ltd.
    Inventors: Hiroki Funato, Takashi Suga, Yoshiyuki Tsuchie, Satoshi Nakamura
  • Patent number: 9726717
    Abstract: A testing environment may have at least one controller connected to at least first and second testing slots positioned in a housing. The first testing slot can be configured with a first thermal range capability and the second testing slot may be configured with a second thermal range capability that differs from the first thermal range capability.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: August 8, 2017
    Assignee: Seagate Technology LLC
    Inventors: Christopher Eugene Maulsby, Allen Daryl Webb
  • Patent number: 9714983
    Abstract: A test instrument for use with a sample having a plurality of electrically conducting contact pads, the instrument including: a controllable, variable force linear actuator; a probe assembly operated by the linear actuator, the probe assembly having a probe head at one end with a surface for contacting the sample; a movable contactor assembly including a plurality of contacts for electrically contacting the plurality of contact pads on the sample; a housing on which the linear actuator and contactor assembly are mounted, the housing having an identified area for holding the sample during testing; a position sensor assembly for measuring changes in the position of the probe; and a sensor for measuring a force applied to the sample by the probe head.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: July 25, 2017
    Assignee: Nucleus Scientific Inc.
    Inventors: Ian W. Hunter, Grant W. Kristofek, Dean Ljubicic
  • Patent number: 9702936
    Abstract: A system for concurrently testing multiple semiconductor components includes multiple testers, each including a processor and a memory configured to store and execute control signals for completing testing of one of the semiconductor components, a tester side docking board, and a tester communication port. A handler has multiple test sites, each of which is configured to receive one of the semiconductor components, a handler side docking board, and a handler communication port. A controller is located externally from the testers and the handler and is in communication with each of the testers and the handler through the tester and handler communication ports. Communication between each of the testers and the handler occurs through the controller, and each of the testers is connected, via the tester side docking board, to a corresponding one of the semiconductor components through the handler side docking board.
    Type: Grant
    Filed: August 17, 2014
    Date of Patent: July 11, 2017
    Assignee: NXP USA, INC.
    Inventor: Lifeng Tao
  • Patent number: 9678148
    Abstract: In an embodiment, a testing system includes a frame, a DUT (device under test) testing module. The frame has at least one aperture extending from a front side of the frame to a rear side of the frame. The DUT testing module is inserted into the at least one aperture. The DUT testing module is operable to receive and hold a DUT receptacle including an electrical interface, an air flow interface, and a DUT coupled to the electrical interface. The DUT receptacle is configured to enclose and hold inside the DUT. Further, the DUT testing module is operable to couple to and to use the electrical interface and the air flow interface to perform a test at a controlled temperature on the DUT that is inside of the DUT receptacle.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: June 13, 2017
    Assignee: ADVANTEST CORPORATION
    Inventors: Ben Rogel-Favila, James Fishman
  • Patent number: 9618570
    Abstract: In an embodiment, a testing apparatus includes an air mixing chamber, a docking unit, and a DUT (device under test) test execution unit. The air mixing chamber includes a first air inlet operable to receive a first air flow, a second air inlet operable to receive a second air flow, and an air outlet operable to output a mixed air flow. The docking unit is operable to receive and to securely hold a DUT (device under test) receptacle including an electrical interface, an air flow interface, and a DUT coupled to the electrical interface. The DUT receptacle is configured to enclose and hold inside the DUT. The docking unit is operable to couple to the electrical interface and to the air flow interface. The docking unit is operable to receive and to send the mixed air flow to the DUT receptacle. A DUT test execution unit is coupled to the docking unit. The DUT test execution unit is operable to perform a test on the DUT that is inside of the DUT receptacle.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: April 11, 2017
    Assignee: ADVANTEST CORPORATION
    Inventors: Ben Rogel-Favila, James Fishman
  • Patent number: 9557368
    Abstract: The present disclosure relates to a method for measuring thermal electric characteristics of a semiconductor device, including the steps of: providing at least one current to the LED device over a time interval; recording a voltage transient response of the LED device, wherein the voltage transient response has a plurality of time segments different in gradient; computing a voltage difference from one of the plurality of time segments in the voltage transient response; and determining whether the LED device is defective based on the voltage difference, wherein the voltage difference is thermal dependent. The present disclosure also provides a testing method for defining a plurality of time segments.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: January 31, 2017
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chien-Ping Wang, Tzung-Te Chen, Pei-Ting Chou
  • Patent number: 9482464
    Abstract: An environmental control apparatus includes a test chamber, a refrigerant cooling subsystem coupled to the test chamber, a liquid nitrogen cooling subsystem coupled to the test chamber, and control circuitry. The control circuitry is coupled to the refrigerant cooling subsystem and the liquid nitrogen cooling subsystem. The control circuitry is constructed and arranged to coordinate operation of the refrigerant cooling subsystem and the liquid nitrogen cooling subsystem to control internal temperature of the test chamber. Selective operation of the liquid nitrogen cooling subsystem and the refrigerant cooling subsystem can provide significant cost savings by alleviating the need to provide liquid nitrogen cooling in all cooling situations. Moreover, co-location of the liquid nitrogen cooling subsystem and the refrigerant cooling subsystem can provide an efficient and effective form factor for the environmental control apparatus.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: November 1, 2016
    Assignee: EMC IP Holding Company, LLC
    Inventor: Kevin Burke
  • Patent number: 9485810
    Abstract: A handler includes: a rotating section which is a holding unit mounting section which can take a mounted state in which a holding unit for holding an IC device is mounted; and a transportation mechanism which transports the IC device held by the holding unit. The rotating section includes a heat generation section which generates heat and a heating flow path through which fluid which is heated by the heat generation section and is used for heating of the IC device passes.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: November 1, 2016
    Assignee: Seiko Epson Corporation
    Inventors: Takayuki Imai, Haruhiko Miyamoto, Fuyumi Takata, Toshioki Shimojima
  • Patent number: 9442025
    Abstract: In some embodiments, a method may be provided for calibrating integrated circuit temperature sensors. The method may include sensing a first temperature using a first temperature sensor and a second temperature using a second temperature sensor. The first temperature sensor may be calibrated and is external to a package of the integrated circuit. The second temperature sensor may be included in the integrated circuit. The method may include increasing a temperature of the integrated circuit. The method may include allowing the integrated circuit and the package to thermally equilibrate over a first period of time. The method may include sensing a first slope of a temperature decay by the first temperature sensor. The method may include sensing a second slope of a temperature decay by the second temperature sensor. The method may include calibrating the second temperature sensor responsive to a difference between the first and second temperatures and the first and second slopes.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: September 13, 2016
    Assignee: Apple Inc.
    Inventors: Yizhang Yang, Jun Zhai
  • Patent number: 9434555
    Abstract: A handler includes a supply shuttle plate on which a device is placed and cooled, and a transfer robot configured to transfer the device placed on the supply shuttle plate from the supply shuttle plate. The transfer robot includes an adsorbing portion configured to adsorb the device placed on the supply shuttle plate thereon, a vertical movement arm configured to move the adsorbing portion away from the supply shuttle plate, an arm box configured to accommodate the adsorbing portion together with the device in a state of being kept away from the supply shuttle plate, and a dry air supply unit configured to supply dry gas into the arm box.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: September 6, 2016
    Assignee: Seiko Epson Corporation
    Inventors: Masami Maeda, Toshioki Shimojima
  • Patent number: 9335367
    Abstract: A method and structure are provided for implementing low temperature wafer testing of a completed wafer. A coolant gel is applied to the completed wafer, the gel coated wafer is cooled and one or more electrical test probes are applied through the gel to electrical contacts of the cooled wafer, and testing is performed.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: May 10, 2016
    Assignee: International Business Machines Corporation
    Inventors: Travis R. Hebig, Joseph Kuczynski, Steven R. Nickel
  • Patent number: 9151780
    Abstract: A wafer inspection interface 18 includes a probe card 20 having a substrate 20a and a multiple number of probes 25 that are provided at a surface of the substrate 20a facing a wafer W and arranged to correspond to electrodes of a plurality of semiconductor devices formed on the wafer W; a pogo frame 40 that is in contact with a surface of the probe card 20 opposite to a surface of the probe card 20 facing the wafer W and supports the probe card 20; and a shim 51 provided on the surface of the probe card 20 in contact with the pogo frame 40 and configured to adjust a thickness of the probe card 20. The shim 51 has a cross shape when viewed from the top.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: October 6, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Hiroshi Yamada
  • Patent number: 9146256
    Abstract: A probe assembly for inspecting power semiconductor devices, which includes a probe block having more than one probe holding hole, more than one probe, each of which is contained in one of the probe holding holes with its outer surface being in contact with the inner surface of the probe holding hole, and which has lower end protruding from the probe block and coming into contact with the power semiconductor device on inspection, and one or more cooling units which cool the probe block. According to the probe assembly and the inspection apparatus, it is possible to inspect characteristics of power semiconductor devices accurately by suppressing temperature rises of the probes as well as the power semiconductor device under test.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: September 29, 2015
    Assignee: KABUSHIKI KAISHA NIHON MICRONICS
    Inventors: Katsuo Yasuta, Hikaru Masuta, Hideki Nei, Tatsuya Ishiwatari
  • Patent number: 9140726
    Abstract: A support body for a plurality of contact terminals included in a probe card for inspecting semiconductor devices formed in a semiconductor substrate is provided. The support body includes a main body formed by stacking a plurality of plate-shaped members, a plurality of contact terminal holes formed through the main body in a thickness direction of the plate-shaped members, and one or more coolant paths provided in the main body. Further, the contact terminals respectively are inserted into the contact terminal holes.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: September 22, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Jun Mochizuki, Kunihiro Furuya
  • Patent number: 9075266
    Abstract: The present invention relates to a device for prebaking an alignment film by using a temperature-controllable pin to support a substrate and a method thereof. The device includes heater that prebakes a substrate from an underside of the substrate, a plurality of temperature-controllable pins for upward supporting the substrate, and a temperature control system. The temperature-controllable pins are coupled to the temperature control system and each of the temperature-controllable pins is independently controlled of temperature thereof by the temperature control system so as to uniformly heat a site of the substrate that is supported by the temperature-controllable pin and a periphery of the supported site. The device for prebaking alignment film by using temperature-controllable pin to support substrate and a method thereof according to the present invention alleviate non-uniform heating of a surface of glass substrate and thus alleviate pin mura.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: July 7, 2015
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventors: Meina Zhu, Jianjun Zhao, Hsiangyin Shih
  • Patent number: 9057757
    Abstract: Forward voltage drift in a probe system for the characterization of a light-emitting wafer is virtually eliminated by directing compressed air to the probe so as to ensure that the exact same temperature conditions exist during repeated measurements of the wafer. In one embodiment of the invention, an air flow at room temperature is used, either continuously or intermittently. In another embodiment, the temperature of the probe is controlled by flowing a liquid or a gas through micro-channels built into the probe. In yet another embodiment, the probe is connected to a solid-state Peltier cell that is computer-controlled to maintain the probe's temperature at a predetermined set-point. A temperature-controlled chamber or a thermal reservoir enclosing the probe could be used as well. The results obtained showed remarkable repeatability.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: June 16, 2015
    Assignee: BRUKER NANO, INC.
    Inventor: Dong Chen
  • Patent number: 9046569
    Abstract: Embodiments of an apparatus and method for providing cooling of probes for testing of integrated circuits are generally described herein. In some embodiments, an apparatus comprises a probe head assembly configured to hold one or more probes that are adapted to provide electrical contact with an integrated circuit device under test (DUT), a DUT chuck adapted to hold the DUT for contact with the probes, a seal arranged between the probe head assembly and the DUT chuck to form a chamber when the seal is in contact with the probe head assembly and the DUT chuck, and a first port and a second port arranged to provide fluid flow into and fluid flow out of the chamber.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: June 2, 2015
    Assignee: Intel Corporation
    Inventors: Ronald Kirby, James G. Maveety, Joe Walczyk
  • Patent number: 9035669
    Abstract: An apparatus for testing electronic devices, having a test head coupled to at least one immovably mounted test socket, a positioning device for positioning the electronic device in testing position and a lead-backer attached to the positioning device for supporting the electronic device and pressing it against the test socket. A supply port for supplying a temperature control medium to a temperature control system of the said lead-backer is immovably mounted beside the said test socket, the said temperature control system of the said lead-backer and the said supply port communicate with each other when the electronic device is in testing position, whereby the said temperature control medium flows from the said supply port to the said temperature control system of the said lead-backer.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: May 19, 2015
    Assignee: Multitest Elektronische Systeme GmbH
    Inventors: Franz Pichl, Michael Hertkorn, Guenther Jeserer
  • Patent number: 9024651
    Abstract: A test apparatus for testing a semiconductor device includes a circuit board having a contact pattern on one side and an opening therethrough, and a probe card supporting a probe needle array. The probe needle array is insertable into the opening of the circuit board and is configured to probe a device under test. The probe needle array is in electrical contact with the contact pattern of the circuit board, to allow signals through the probe card and circuit board to a test equipment. A holder supports the probe card and other probe cards. The holder has multiple sides, each of which is supportable of a probe card having a probe needle array. The holder is rotatable to manipulate and position the probe needle arrays of the probe cards relative to a device under test. The holder allows disconnection and replacement of the probe needle arrays from the holder.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: May 5, 2015
    Assignees: Celadon Systems, Inc., Intel Corporation
    Inventors: Bryan J. Root, William A. Funk, Michael Palumbo, John L. Dunklee
  • Patent number: 9007080
    Abstract: An integrated circuit (IC) device tester maintains a set point temperature on an IC device under test (DUT) having a die attached to a substrate. The tester includes a thermal control unit and a fluid management system configured to supply the thermal control unit with fluids for pneumatic actuation, cooling, and condensation abating. The tester can includes a box enclosing the thermal control unit thereby providing a substantially isolated dry environment during low humidity testing of the DUT. The heat exchange plate may include an inner structure for thermal conductivity enhancement.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: April 14, 2015
    Assignee: Essai, Inc.
    Inventors: Nasser Barabi, Chee Wah Ho, Joven R. Tienzo, Oksana Kryachek, Elena V. Nazarov
  • Patent number: 8981802
    Abstract: A device tester for an IC device under test (DUT), the DUT having a substrate and an attached die. The device tester includes a thermal control unit and a test socket assembly which conforms to the DUT's profile. The thermal control unit includes a pedestal assembly, a heater having a fuse coupled to a heating element, a substrate pusher, and a force distributor for distributing force between the pedestal assembly and the substrate pusher. The test socket assembly includes a socket insert that supports and also conforms to the DUT's profile.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: March 17, 2015
    Assignee: Essai, Inc.
    Inventors: Nasser Barabi, Chee Wah Ho, Joven R. Tienzo, Oksana Kryachek, Elena V. Nazarov
  • Publication number: 20150061712
    Abstract: A method and structure are provided for implementing low temperature wafer testing of a completed wafer. A coolant gel is applied to the completed wafer, the gel coated wafer is cooled and one or more electrical test probes are applied through the gel to electrical contacts of the cooled wafer, and testing is performed.
    Type: Application
    Filed: August 27, 2013
    Publication date: March 5, 2015
    Applicant: International Business Machines Corporation
    Inventors: Travis R. Hebig, Joseph Kuczynski, Steven R. Nickel
  • Patent number: 8896335
    Abstract: An apparatus controls a temperature of a device by circulating a fluid through a heat sink in thermal contact with the device. The apparatus includes an adjustable cold input, which inputs a cold portion of the fluid having a first temperature, and an adjustable hot input, which inputs a hot portion of the fluid having a second temperature higher than the first temperature. The apparatus further includes a chamber, connected to the cold input and hot input, in which the cold and hot portions of the fluid mix in a combined fluid portion that impinges on the heat sink. The combined fluid portion has a combined temperature that directly affects a temperature of the heat sink. The cold input and hot input are adjusted to dynamically control the combined temperature, enabling the heat sink temperature to compensate for changes in the device temperature, substantially maintaining a set point temperature of the device.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: November 25, 2014
    Assignee: Advantest Corporation
    Inventors: Larry Stuckey, Anastasios Golnas, Robert Edward Aldaz, David Yu