With Biasing Means Patents (Class 324/750.1)
  • Patent number: 11579178
    Abstract: An inspection apparatus used for inspecting a bare circuit board is provided, where the bare circuit board includes an antenna. The inspection apparatus includes a holding stage, a probing device, and a measurement device. The holding stage can hold the bare circuit board. The measurement device is electrically connected to the probing device and electrically connected to the antenna via the probing device. The measurement device can input a first testing signal to the antenna. The antenna can input a second testing signal to the measurement device after receiving the first testing signal. The measurement device can measure the antenna according to the second testing signal, where the first testing signal and the second testing signal both pass through no active component.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: February 14, 2023
    Assignee: Unimicron Technology Corp.
    Inventors: Hsin-Hung Lee, Chun-Hsien Chien, Yu-Chung Hsieh, Yi-Hsiu Fang, Tzyy-Jang Tseng
  • Patent number: 11558476
    Abstract: The present disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT). The present disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. The disclosure provides a method for renewing a subscription for network data collection and analysis in a wireless communication system.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: January 17, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jungshin Park, Sangsoo Jeong
  • Patent number: 10068814
    Abstract: An apparatus for evaluating a semiconductor device includes: a chuck stage for fixing a semiconductor device; an insulating substrate; a plurality of probes fixed to the insulating substrate; a temperature adjustment unit adjusting temperatures of the plurality of probes; an evaluation/control unit causing a current to flow into the semiconductor device through the plurality of probes to evaluate an electric characteristic of the semiconductor device; an inspection plate having a front surface and a rear surface opposite to each other; a thermal image measurement unit acquiring a thermal image of the inspection plate when distal end portions of the plurality of probes are pressed against the front surface; and a thermal image processing unit performing image processing to the thermal image to obtain in-plane positions and temperatures of the distal end portions of the plurality of probes.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: September 4, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Akira Okada, Norihiro Takesako, Hajime Akiyama
  • Patent number: 9152755
    Abstract: An optical semiconductor unit of the present invention has an LED device provided with an LED (Light Emitting Diode) and a socket to which the LED device is mounted, the LED device has a main body to which the LED is mounted, the main body has a first surface to which block-shaped electrode portions are connected.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: October 6, 2015
    Assignee: Japan Aviation Electronics Industry, Limited
    Inventor: Hideyuki Kanno
  • Patent number: 9000787
    Abstract: A method and a system for three-phase detection of a three-phase electric device are provided. The system includes a testing circuit and a comparison module. The testing circuit generates two reference voltages by using the three phase voltages of the three-phase electric device. The two reference voltages are the first and second phase voltages with reference to the third phase voltage, respectively. Three-phase detection is performed by comparing the two reference voltages for a determined number of times. After testing is completed, the testing circuit is switched off by the comparison module, to save power.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: April 7, 2015
    Assignee: Carrier Corporation
    Inventors: Brian Inman, Robert P. Dolan, Anthony G. Russo, Steven M. Palermo
  • Patent number: 8970237
    Abstract: A system and method for low-cost, fault tolerant, EMI robust data communications, particularly for an EV environment.
    Type: Grant
    Filed: August 12, 2012
    Date of Patent: March 3, 2015
    Assignee: Tesla Motors, Inc.
    Inventors: Nathaniel Brian Martin, Ian Casimir Dimen, Samuel Douglas Crowder
  • Patent number: 8952712
    Abstract: Methods and apparatus are disclosed to simultaneously, wirelessly test semiconductor components formed on a semiconductor wafer. The semiconductor components transmit respective outcomes of a self-contained testing operation to wireless automatic test equipment via a common communication channel. Multiple receiving antennas observe the outcomes from multiple directions in three dimensional space. The wireless automatic test equipment determines whether one or more of the semiconductor components operate as expected and, optionally, may use properties of the three dimensional space to determine a location of one or more of the semiconductor components. The wireless testing equipment may additionally determine performance of the semiconductor components by detecting infrared energy emitted, transmitted, and/or reflected by the semiconductor wafer before, during, and/or after a self-contained testing operation.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: February 10, 2015
    Assignee: Broadcom Corporation
    Inventors: Arya Reza Behzad, Ahmadreza Rofougaran, Sam Ziqun Zhao, Jesus Alfonso Castaneda, Michael Boers
  • Patent number: 8937483
    Abstract: A semiconductor package transferring apparatus is disclosed. The apparatus includes a tray that includes a front side and a rear side opposite the front side, the rear side including a plurality of package covering portions that each correspond to the shape of a semiconductor package and that are arranged to align with corresponding package loading portions on a front side of another tray. Each package covering portion has a surface configured to cover a semiconductor chip disposed below the surface. The apparatus further includes an anti-attachment portion disposed on the surface of one or more of the package covering portions. For each package covering portion on which an anti-attachment portion is disposed, the anti-attachment portion protrudes beyond the surface of the package covering portion.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: January 20, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeck-Jin Jeong, Yong-Ki Park, Yong-Jin Jung, Heul-Seog Kim
  • Patent number: 8922229
    Abstract: A method is disclosed for the measurement of a power device in a prober, which serves the examination and testing of such components. In the process, a power device is held by a chuck, and at least one electric probe is held by a probe holder, and optionally, the power device or the probe is positioned each relative to the other using a positioning device with an electrical drive, and contacts the power device. At the same time, an electrical connection remains between the probe to a signal unit with which a power signal is sent out or received, is blocked and only unblocked when it is determined that the contact between probe 26 and contact area is established.
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: December 30, 2014
    Assignee: Cascade Microtech, Inc.
    Inventors: Botho Hirschfeld, Stojan Kanev
  • Patent number: 8896335
    Abstract: An apparatus controls a temperature of a device by circulating a fluid through a heat sink in thermal contact with the device. The apparatus includes an adjustable cold input, which inputs a cold portion of the fluid having a first temperature, and an adjustable hot input, which inputs a hot portion of the fluid having a second temperature higher than the first temperature. The apparatus further includes a chamber, connected to the cold input and hot input, in which the cold and hot portions of the fluid mix in a combined fluid portion that impinges on the heat sink. The combined fluid portion has a combined temperature that directly affects a temperature of the heat sink. The cold input and hot input are adjusted to dynamically control the combined temperature, enabling the heat sink temperature to compensate for changes in the device temperature, substantially maintaining a set point temperature of the device.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: November 25, 2014
    Assignee: Advantest Corporation
    Inventors: Larry Stuckey, Anastasios Golnas, Robert Edward Aldaz, David Yu
  • Patent number: 8704543
    Abstract: A test head moving apparatus includes elevating arms that move a test head up and down, a frame that horizontally moves the test head, and an interlock mechanism that prohibits the horizontal movement of the frame on the basis of a height of the test head. The interlock mechanism has a limit switch that detects that the test head is positioned at the lowermost limit and stoppers capable of pressing the pressing units onto a floor plane.
    Type: Grant
    Filed: July 14, 2008
    Date of Patent: April 22, 2014
    Assignee: Advantest Corporation
    Inventor: Takayuki Yano
  • Patent number: 8593270
    Abstract: The present invention relates to a tester, its use and a method for testing signal lines of a flight control system for a trimmable horizontal stabilizer (THS) motor of an aircraft. The tester comprises at least one test-relay (52, 54) to be connected with a relay socket of the flight control system, when the signal lines of the flight control system are to be tested, and at least one indicator (60, 70, 80, 90) being electrically connected with the at least one test-relay (52, 54) for indicating whether a voltage being applied to the test-relay (52, 54) is equal to or larger than a predetermined voltage. The method according to the invention comprises the steps of connecting at least one test-relay (52, 54) of a tester (1), in place of the original relay, with the relay socket of the flight control system, applying a voltage to the at least one test-relay (52, 54) and determining whether a voltage being applied to the at least one test-relay (52, 54) is equal to or larger than a predetermined voltage.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: November 26, 2013
    Assignee: Airbus Operations GmbH
    Inventor: Sven Knoop
  • Patent number: 8547124
    Abstract: A DUT is connected to an I/O terminal. An AC test unit performs an AC test operation for the DUT. A DC test unit performs a DC test operation for the DUT. An optical semiconductor switch is arranged such that a first terminal thereof is connected to the AC test unit and a second terminal thereof is connected to the I/O terminal. The optical semiconductor switch 10 is configured to be capable of switching states, according to control signals input to control terminals, between a connection state in which the first terminal and the second terminal are connected to each other, and a disconnection state in which they are disconnected from each other. A first impedance circuit is arranged on a signal line for the control signal to be input to the positive-electrode control terminal. Furthermore, a second impedance circuit is arranged on a signal line for the control signal to be input to the negative-electrode control terminal.
    Type: Grant
    Filed: April 22, 2010
    Date of Patent: October 1, 2013
    Assignee: Advantest Corporation
    Inventors: Takao Kawahara, Takayuki Nakamura
  • Patent number: 8536888
    Abstract: An integrated circuit (IC), comprises a receiver on an IC substrate. The receiver is configured to receive a stressed input signal. A built in self test (BIST) circuit is provided on the IC substrate for testing the receiver. The BIST circuit comprises an encoder configured for receiving an input signal and identifying whether a first condition is present, in which two or more consecutive input data bits have the same polarity as each other. An output driver circuit provides the stressed input signal corresponding to the two or more consecutive input data bits. The stressed input signal has an amplitude that is larger when the encoder identifies that the first condition is present and smaller when the encoder identifies that two or more consecutive input data bits have different polarity from each other.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: September 17, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jinn-Yeh Chien, Hao-Jie Zhan
  • Patent number: 8228069
    Abstract: A test apparatus includes a plurality of pairs of test contacts on a semiconductor substrate; a first test structure which includes a plurality of first test interconnection layers and a first body interconnection layer that is electrically connected to the first test interconnection layers, each of the first test interconnection layers being electrically connected to at least one test contact; and a second test structure which includes a plurality of second test interconnection layers and a second body interconnection layer that is electrically connected to the second test interconnection layers, each of the second test interconnection layers being electrically connected to at least one test contact.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: July 24, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-Jung Lee, Hong-Jae Shin
  • Patent number: 8228084
    Abstract: Embodiments of the present disclosure provide a method that includes producing an integrated circuit device configured to include a system on a chip (SOC) and accessing test code within the SOC during the producing. The method further includes self-testing the integrated circuit device with the test code.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: July 24, 2012
    Assignee: Marvell International Ltd.
    Inventor: Hungchi Chen
  • Patent number: 8198907
    Abstract: A chip test fixture for assisting in examining a test chip on a printed circuit board includes a switching module, a pin cord and a magnetic unit. The switching module includes a standard chip and a switch element configured to turn on either the standard chip or the test chip. The pin cord is connected with the switch module at one end and is formed with a contacting head at the other end. The contacting head has a set of contact pins corresponding to that of the test chip. The magnetic unit is configured to draw the contacting head of the pin cord and the test chip together in such a way that the contact pins of the contacting head are in contact with that of the test chip once the contacting head approaches the test chip.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: June 12, 2012
    Assignee: Giga-Byte Technology Co., Ltd.
    Inventor: Shih-Yang Chou
  • Patent number: 8038343
    Abstract: A novel computer program product and method for thermally characterizing a device used for cooling an electronic device is disclosed. A cooling device, being operated, is thermally coupled to a heat pipe having a surface to receive a test chip. A heater is patterned on a circuitry side of the test chip. The heater is separate from operational circuitry of the test chip. A localized heat source is applied to at least one region on a test chip thermally coupled to the heat pipe to locally heat more than one region on a second surface of the test chip to test more than one hot spot. The second surface is the circuitry side of the test chip. The heater provides a bias heat to the test chip, independent of operating the test chip, while the localized heat source is selectively applied directly to the test chip. A temperature detector is used to measure a temperature distribution on the second surface of the test chip.
    Type: Grant
    Filed: March 14, 2008
    Date of Patent: October 18, 2011
    Assignee: International Business Machines Corporation
    Inventors: Hendrik F. Hamann, Madhusudan K. Iyengar, James A. Lacey, Roger R. Schmidt
  • Patent number: 7982477
    Abstract: A universal test fixture for testing and characterization of high-power flange-packaged RF and microwave transistors and diodes includes a precision-machined heat sink having a built-in center cavity with a finger catch on either side of the cavity which uses a plurality of matching modules that are installed in the center cavity and designed as transistor or diode carrier modules to provide mounting for the high-power packaged RF and microwave devices in a wide variety of flange type packages, an adjustable clamping structure connected to a movable arm, and a plurality of non-conductive high temperature pressure clamps. Each carrier module is made of a gold-plated rectangular aluminum block having a center cavity that is machined to the package outline. A non-conductive black-anodized high-temperature resistant pressure clamp machined to the package outline holds the packaged device in the carrier module.
    Type: Grant
    Filed: August 1, 2008
    Date of Patent: July 19, 2011
    Assignee: AES Technologies, Inc.
    Inventor: Michael M. Ghadaksaz