Abstract: A semiconductor process and apparatus provide a high-performance magnetic field sensor with three differential sensor configurations which require only two distinct pinning axes, where each differential sensor is formed from a Wheatstone bridge structure with four unshielded magnetic tunnel junction sensor arrays, each of which includes a magnetic field pulse generator for selectively applying a field pulse to stabilize or restore the easy axis magnetization of the sense layers to orient the magnetization in the correct configuration prior to measurements of small magnetic fields. The field pulse is sequentially applied to groups of the sense layers of the Wheatstone bridge structures, thereby allowing for a higher current pulse or larger sensor array size for maximal signal to noise ratio.

Abstract: The present invention is provided to quickly and efficiently inspect a plurality of CCD sensors. In the present invention, a plurality of openings is formed in a circuit board of a probe card. A plurality of vertical-type probe pins is connected to a lower surface of the circuit board. A guide board is installed at the lower surface of the circuit board, and respective probe pins are inserted into respective guide holes of the guide board. The guide board is made of a transparent glass board. During an inspection, inspection light emitted from a test head passes through the openings of the circuit board and the guide board, so that it is irradiated onto the plurality of CCD sensors on the substrate. Since the plurality of probe pins can be arranged at a narrow pitch without blocking the inspection light, adjacent CCD sensors on the substrate can be inspected simultaneously.

Abstract: A magnetic sensor integrated circuit includes a plurality of magnetically sensitive elements, and at least one test conductor positioned adjacent to at least one of the magnetically sensitive elements and configured to generate a differential magnetic field that is adapted to be applied to the plurality of magnetically sensitive elements during a test mode.