Adjustable Support For Device Under Test Patents (Class 324/750.19)
  • Patent number: 10890617
    Abstract: A characteristic detection apparatus includes: a characteristic detector that detects an electrical characteristic of an electronic component placed on a substrate; and a pressing member that is provided separately from the characteristic detector, and generates a pressing force to press the characteristic detector to the substrate, causing the characteristic detector to be electrically connected to the electronic component.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: January 12, 2021
    Assignee: DENSO CORPORATION
    Inventors: Keita Nakamata, Shinji Ohoka, Toshihiro Hattori, Takahiro Tsuda
  • Patent number: 10877089
    Abstract: In some embodiments, a semiconductor wafer testing system is provided. The semiconductor wafer testing system includes a semiconductor wafer prober having one or more conductive probes, where the semiconductor wafer prober is configured to position the one or more conductive probes on an integrated chip (IC) that is disposed on a semiconductor wafer. The semiconductor wafer testing system also includes a ferromagnetic wafer chuck, where the ferromagnetic wafer chuck is configured to hold the semiconductor wafer while the wafer prober positions the one or more conductive probes on the IC. An upper magnet is disposed over the ferromagnetic wafer chuck, where the upper magnet is configured to generate an external magnetic field between the upper magnet and the ferromagnetic wafer chuck, and where the ferromagnetic wafer chuck amplifies the external magnetic field such that the external magnetic field passes through the IC with an amplified magnetic field strength.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Harry-Hak-Lay Chuang, Chih-Yang Chang, Ching-Huang Wang, Tien-Wei Chiang, Meng-Chun Shih, Chia Yu Wang
  • Patent number: 10656178
    Abstract: A method for aligning an inhomogeneous receiver with an anisotropic emitter on a wafer probing system, wherein a reference semiconductor die comprising a reference pad and an anisotropic emitter is formed on a semiconductor wafer, the reference pad is located at a reference-pad-and-anisotropic-emitter relative position corresponding to the anisotropic emitter, the method comprises following steps of: measuring a receiver center position of an inhomogeneous receiver configured on a wafer probing system by a profile sensor; measuring a reference tip position of a reference tip of a reference probe on a probe card by a measuring instrument; displacing the inhomogeneous receiver in an aligning displacement according to the reference-pad-and-anisotropic-emitter relative position, the reference tip position and the receiver center position; and aligning the reference tip with the reference pad by a probe-tip-and-pad aligning machine of the wafer probing system.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: May 19, 2020
    Assignee: Win Semiconductors Corp.
    Inventor: Shu-Jeng Yeh
  • Patent number: 10605649
    Abstract: The disclosure relates to an adjustable load transmitter for adjusting an alignment between planar members separated from each other by a gap. The load transmitter comprises a set of plates to be received inside the gap, the set comprising two rotatable plates and being adapted for transmitting a load via a load transmission path between the planar members. The load transmission path comprises the rotatable plates. Each of the plates comprises two flat, non-parallel contact faces, and one of the contact faces of the first rotatable plate is in permanent surface contact with one of the contact faces of the second rotatable plate. The rotatable plates are adapted for being rotated relative to each other around one of their respective normal axes.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: March 31, 2020
    Assignee: International Business Machines Corporation
    Inventors: Martin Eckert, Siegfried Tomaschko, Roland Dieterle
  • Patent number: 10598698
    Abstract: Embodiments of the invention include a tool and method for automatically replacing defective pogo pins for use in testing a semiconductor package. Aspects of the invention include a nozzle tip and a pin management valve assembly coupled to the nozzle tip. The pin management valve assembly is actuatable to couple an open pin management valve or a partially closed pin management valve to the nozzle tip. The open pin management valve includes a first diameter and the partially closed pin management valve includes a second diameter. A vacuum reservoir is coupled to the pin management valve assembly and a vacuum management valve is positioned between the pin management valve assembly and the vacuum reservoir. The vacuum management valve is actuatable between an open and closed position.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: March 24, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Vincent Beauregard, Styve Giard, Gilles Labbe
  • Patent number: 10539607
    Abstract: An evaluation apparatus includes an insulating plate, a plurality of probes fixed to the insulating plate, an insulating portion having a connection portion connected to the insulating plate in a detachable manner and a tip portion continuous with the connection portion, the tip portion being narrower than the connection portion, an insulator formed by combining the insulating portions to surround the plurality of probes in planar view, and an evaluation unit for passing currents through the plurality of probes to evaluate electrical characteristics of an object to be measured.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: January 21, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Akira Okada, Kinya Yamashita, Masaki Ueno
  • Patent number: 10481177
    Abstract: A wafer inspection method improving inspection accuracy and operation efficiency. A method for performing electrical inspection by bringing into contact with pads in chips on a wafer. A chuck step S1 for heating the wafer to an inspection temperature; a first position recognition step S2 for recognizing all the positions of the pads; a second position recognition step S3 for re-recognizing, before performing the electrical inspection, the position of the pads recognizing the positional shifts of the pads due to thermal expansion; and a correction step S4 for correcting contact positions with respect to the probes, the contact positions being corrected on the basis of pad positions, which have been re-recognized in the second position recognition step S3 on the basis of the pad positions recognized in the first position recognition step S2, and which have been updated.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: November 19, 2019
    Assignee: Tokyo Seimitsu Co. LTD.
    Inventors: Yuichi Ozawa, Yasuhito Iguchi, Tetsuo Yoshida, Junzo Koshio
  • Patent number: 10388579
    Abstract: In some embodiments, a semiconductor wafer testing system comprises a first plate configured to couple to a probe head, the first plate including a first alignment feature, a biasing member, a stopper, and pins. The system also comprises a second plate configured to fasten to the first plate and including a second alignment feature configured to engage with the first alignment feature. The first and second alignment features are configured to align the pins with a test wafer positioned between the first and second plates. The biasing member and the stopper are configured to cooperate to regulate a pressure with which the test wafer contacts the pins when the second plate is fastened to the first plate.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: August 20, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Randal Leray Newby
  • Patent number: 10345136
    Abstract: The disclosure relates to an adjustable load transmitter for adjusting an alignment between planar members separated from each other by a gap. The load transmitter comprises a set of plates to be received inside the gap, the set comprising two rotatable plates and being adapted for transmitting a load via a load transmission path between the planar members. The load transmission path comprises the rotatable plates. Each of the plates comprises two flat, non-parallel contact faces, and one of the contact faces of the first rotatable plate is in permanent surface contact with one of the contact faces of the second rotatable plate. The rotatable plates are adapted for being rotated relative to each other around one of their respective normal axes.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Martin Eckert, Siegfried Tomaschko, Roland Dieterle
  • Patent number: 10254309
    Abstract: A latch assembly that can lock and unlock a probe core with respect to a circuit board is provided. The latch assembly can engage with the probe core to align the probe core with respect to a circuit board, and press down the probe core against the circuit board by rotating to lock the probe core with the circuit board. An installation tool is provided to grip or release the probe core to/from a latch assembly or a probe core carrier. The installation tool can align with the probe core and/or the latch assembly to lock and unlock the probe core with respect to a circuit board.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: April 9, 2019
    Assignee: CELADON SYSTEMS, INC.
    Inventors: John L. Dunklee, William A. Funk, Bryan J. Root
  • Patent number: 10168359
    Abstract: A probe card includes a wiring board, a top cover, a retractable structure and a probe. The top cover couples with the wiring board and has an air inlet. The retractable structure connects with the top cover and includes a first and a second rings. The first ring has vent holes. A top surface of the first ring and a first bottom surface of the top cover define a homogenized space communicating with the air inlet and the vent holes. The second ring couples with the first ring and has jet holes communicating with the vent holes. Outlets of the jet holes locate on a second bottom surface of the second ring. A first inner sidewall of the first ring and a second inner sidewall of the second ring define a pressure space. The probe connects with the wiring board and extends to the pressure space.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: January 1, 2019
    Assignee: MPI Corporation
    Inventors: Chin-Yi Tsai, Chien-Hung Chen
  • Patent number: 10150525
    Abstract: A testing device is disclosed for testing a connection interface coupled onto an assembly line between first and second vehicle components. The testing device includes a tool configured to couple the connection interface, at least one test adapter for testing the coupling of the connection interface, and a sensor device for acquiring a force progression which acts during and/or after the coupling in the connection interface. The testing device also includes an evaluation device to evaluate the force progression.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: December 11, 2018
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventor: Matthias Berg
  • Patent number: 9910084
    Abstract: A flexible circuit board inspecting apparatus for conducting an inspection on a flexible circuit board includes a transport path and an inspection part mechanism. The transport path is configured to successively transport the flexible circuit board having a plurality of unit circuit boards arranged thereon. The inspection part mechanism is configured to bring and distance a jig for inspecting the flexible circuit board transported on the transport path close to and from the flexible circuit board. The transport path includes a longitudinal transport portion for transporting the flexible circuit board in a downward vertical direction. The inspection part mechanism moves the jig in a direction perpendicular to the flexible circuit board transported on the longitudinal transport portion to bring and distance the jig close to and from the flexible circuit board.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: March 6, 2018
    Assignee: NIDEC-READ CORPORATION
    Inventors: Takashi Nakagawa, Toshihide Matsukawa, Osamu Hikita, Michio Kaida
  • Patent number: 9823341
    Abstract: The ultrasonic sensor includes a wave transmitting and receiving device and a cover. The wave transmitting and receiving device has a front surface including a wave transmitting and receiving surface and is configured to transmit and receive an ultrasonic wave through the wave transmitting and receiving surface. The cover covers the wave transmitting and receiving device so as to expose the wave transmitting and receiving surface. The cover is constituted by multiple portions, and the multiple portions are individually made of multiple materials different from each other.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: November 21, 2017
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Takashi Tsuji, Osamu Hirakawa
  • Patent number: 9823164
    Abstract: A device under test, such as a point machine, which is screwed to two longitudinal supports, which can be individually moved horizontally and vertically is provided. Thus, a highly flexible solution is created, because even devices under test having unknown or asymmetric dimensions can be fittingly accommodated and positioned. Linear drives enable highly accurate positioning of the supports, in particular even if the supports are have high inherent weight or are already loaded with the device under test. According to one embodiment, the mechanical system is designed to grasp and/or to lift a mounting cart by means of the supports, on which mounting cart the device under test is fastened by screwing. This provides the advantage that the device under test can be tested while mounted directly to the mounting cart without separate transferring and screwing of the device under test being required.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: November 21, 2017
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventor: Sven Gerhard Dudeck
  • Patent number: 9804197
    Abstract: A probe position inspection apparatus which incorporates a rotatable internal prism is attached to a supporting unit for supporting semiconductor device, thus making it possible to accurately inspect in-plane positions of tips of probes in a short time and also making it possible to adapt the probe position inspection apparatus to a double-sided prober.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: October 31, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Norihiro Takesako, Akira Okada, Takaya Noguchi
  • Patent number: 9772349
    Abstract: A circuit board tester and method that precisely aligns the probe plate and circuit board is disclosed. With a circuit board and probe plate mounting within a housing having a top and bottom, hinged together, at closure there may be slight misalignments of the two. By making one of the two plates floating, or laterally slideable with respect to each other, it is possible to make final alignment at closure. One of the two plates can be provided with a pin and the other with a pin receiving alignment block. With the lateral slideability, the pin and block can insure proper probe alignment. Additional systems for correcting misaligned pins or blocks are also disclosed.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: September 26, 2017
    Assignee: Circuit Check, Inc.
    Inventors: Gregory J. Michalko, Stuart K. Eickhoff, Jon A. Hample, Russell G. Carter
  • Patent number: 9678143
    Abstract: A semiconductor evaluation apparatus includes a jig for evaluation and a probe substrate. The jig for evaluation is provided such that a plurality of semiconductor devices can be placed thereon. The probe substrate is provided so as to face the jig for evaluation, and includes a contact probe. The jig for evaluation includes a plurality of housing portions divided by a frame portion such that the plurality of semiconductor devices can be separately placed on the plurality of housing portions, respectively. The semiconductor evaluation apparatus is configured such that the contact probe can be brought into contact with a plurality of elements in the state where a space is provided by bringing the frame portion and the probe substrate in proximity to each other. In this space, each of the plurality of semiconductor devices is placed between a corresponding one of the plurality of housing portions and the probe substrate.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: June 13, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Akira Okada, Takaya Noguchi, Norihiro Takesako, Kinya Yamashita, Hajime Akiyama
  • Patent number: 9658285
    Abstract: A probe apparatus includes a movable mounting table for holding a test object provided with a plurality of power devices including diodes; a probe card arranged above the mounting table with probes; a measuring unit for measuring electrical characteristics of the power devices by bringing the probes into electrical contact with the test object in a state that a conductive film electrode formed on at least a mounting surface of the mounting table is electrically connected to a conductive layer formed on a rear surface of the test object; and a conduction member for electrically interconnecting the conductive film electrode and the measuring unit when measuring the electrical characteristics. The conduction member is interposed between an outer peripheral portion of the probe card and an outer peripheral portion of the mounting table.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: May 23, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Isao Kouno, Ken Taoka, Eiichi Shinohara, Ikuo Ogasawara
  • Patent number: 9653332
    Abstract: A compact device allows individual or combined correction of wafer probe planarity and orientation misalignment. The device is made as a metallic block or as a strong plastic block and contains three sections, which are held together by a steel blade or by a steel blade and a rotation pin; the sections are split apart for “Phi”—orientation alignment or rotated against each-other for “Theta” planarity alignment. The steel blade provides secure and anti-backlash flexibility both in lateral (“Phi”) and perpendicular (“Theta”) direction. Alternatively the “Theta” alignment can use a rotation shaft or a small part of the original block left over as a bridge joining both sections. The device is inserted between the fixed probe support and the probe itself.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: May 16, 2017
    Inventor: Christos Tsironis
  • Patent number: 9599662
    Abstract: The present invention provides a device for conditioning semiconductor chips and a corresponding test method. The device comprises a chip temperature control means for receiving a semiconductor chip or a plurality of semiconductor chips and comprises a base body which can be flushed with a fluid for temperature control and which comprises a corresponding number of recesses which extend from a front face to a rear face of the base body; a corresponding number of chip bonding pedestals which are inserted, in thermal contact with the base body, into the recesses which comprise a chip receiving region on the front face and a wiring means on the inside which is constructed for supplying electrical signals from and/or to the semiconductor chip inserted in the respective chip receiving region; and a motherboard attached to the rear face in such a way that the wiring means of the chip bonding pedestals is electrically connected to a wiring means of the motherboard.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: March 21, 2017
    Assignee: ERS Electronic GmbH
    Inventor: Klemens Reitinger
  • Patent number: 9557371
    Abstract: In one aspect, a cradle system for supporting a load, the cradle system comprising a first arm with a first carriage assembly axially adjustable therealong and a second arm, opposite the first arm, with a second carriage assembly axially adjustable therealong. An actuator is associated with the first and second carriage assemblies and configured such that actuation of the actuator causes the first and second carriage assemblies to move axially in opposite directions. In another aspect, a cable support system comprising a support column and one or more tethers supported by the support column and configurable so that at least one tether is configured to move its supported cable in the same or opposite direction as the test head moves at a rate that is a constant multiplied by the test heads rate of motion where the constant may be greater than, equal to, or less than one.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: January 31, 2017
    Assignee: inTEST Corporation
    Inventors: Hermann Josef Weissacher, Benoit Jean Michel Goeuriot, Wei Guan, Christopher L. West, Charles Paul Nappen
  • Patent number: 9558979
    Abstract: A wafer chuck holds a wafer on a surface thereof such that an image of the wafer can be formed from light reflected by the surface of the wafer chuck. The surface of the wafer chuck is a planar surface that has a reflectivity equal to or greater than 40%, and/or a whiteness index value equal to or greater than 90. The wafer chuck can include a ceramic containing aluminum oxide having a purity equal to or greater than 95%. The planar surface of the wafer chuck is such that light illuminating the surface of the wafer chuck is reflected by the surface of the wafer chuck through the wafer. The wafer chuck can be used with an apparatus for cutting the wafer, and the light reflected by the surface can be used to form an image of the wafer used identifying cutting lines on the wafer.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: January 31, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hwa Seob Choi, Yu Sung Jang, Tai Young Eum, Jee Ho Lee
  • Patent number: 9557373
    Abstract: A convex testing stack useful in association with a thermal control unit (TCU) that may be used to maintain a set point temperature for testing of a convex IC device under test (DUT) is configured to preserve the convex shape of the DUT.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: January 31, 2017
    Assignee: Essai, Inc.
    Inventors: Nasser Barabi, Chee Wah Ho, Joven R. Tienzo, Oksana Kryachek, Elena V. Nazarov
  • Patent number: 9541422
    Abstract: The present invention extends to methods, systems, apparatus, and computer program products related to a cable-based measuring system. The cable-based measuring system includes a cable, comprising an inner cable member configured to move linearly within an outer cable housing. The measuring system also includes a measuring device configured to generate measurement information regarding movement of the inner cable member relative to the outer cable housing using one or more encoders. A computer system receives the measurement information from the measuring device. The measurement information indicates length as a function of time, and represents three orthogonal dimensional measurements of a three-dimensional object. Based on the measurement information, the computer system identifies a length of each dimensional measurement, including a length, a width, and a height of the three-dimensional object.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: January 10, 2017
    Assignee: Packsize LLC
    Inventor: Niklas Pettersson
  • Patent number: 9543180
    Abstract: An integrated transport device for a wafer carrier includes: an evacuatable chamber for accommodating therein a wafer carrier having a front opening with a cover; a rotatable platform for placing the wafer carrier thereon in the chamber; and an opening/closing device for opening and closing the cover of the wafer carrier placed on the platform at a first position, wherein the platform rotates to set the wafer carrier at the first position and a second position for transporting a wafer to a wafer-handling chamber.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: January 10, 2017
    Assignee: ASM IP Holding B.V.
    Inventor: Tatsuo Kamiya
  • Patent number: 9519009
    Abstract: A prober includes: a wafer chuck having a conductive support surface; a movement rotation mechanism which moves and rotates the wafer chuck; a head stage which holds a probe holding portion; a stage member which has a conductive stage surface that is formed in parallel to the support surface and electrically connected with the support surface, and can move integrally with the wafer chuck; and a contactor which is fixed to a position facing the stage member and whose tip can electrically come into contact with the stage surface, wherein the stage member is separated from the wafer chuck as a separate body, and the stage surface and the support surface are electrically connected through a wiring member; and a back-surface electrode of a chip is electrically connected with a tester through the wafer chuck, a wiring, the stage member and the contactor.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: December 13, 2016
    Assignee: Tokyo Seimitsu Co., Ltd.
    Inventors: Konosuke Murakami, Toshiro Mori, Yuji Shigesawa, Kazuhisa Aoki, Akira Yamaguchi
  • Patent number: 9513314
    Abstract: Circuit boards are provided that include a functional portion and at least one removable test point portion. The removable test point portion may include test points which are accessed to verify whether the functional portion is operating properly or whether installed electronic components are electrically coupled to the board. If multiple boards are manufactured together on a single panel (in which the individual boards are broken off), the test points can be placed on bridges (e.g., removable portions) that connect the individual boards together during manufacturing and testing. Configurable test boards are also provided that can be adjusted to accommodate circuit boards of different size and electrical testing requirements. Methods and systems for testing these circuit boards are also provided.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: December 6, 2016
    Assignee: Apple Inc.
    Inventors: Michael Rosenblatt, W. Bryson Gardner, Amir Salehi, Tony Aghazarian
  • Patent number: 9502319
    Abstract: A driver integrated circuit chip includes a plurality of monitoring bumps, a plurality of output bumps, a plurality of first inner wires electrically connected to the output bumps, a plurality of second inner wires, and a plurality of switching circuits are electrically connected to the second inner wires. Each of the second inner wires is electrically connected between an adjacent pair of monitoring bumps. Each of the switching circuits controls a connection between adjacent monitoring bumps.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: November 22, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jung-Hoon Shim
  • Patent number: 9488541
    Abstract: According to one embodiment, a pressure sensor includes: a base body; a sensor section; and a processing circuit. The sensor section includes: a transducing thin film; a first strain sensing element; and a second strain sensing element. The transducing thin film has a film surface and is flexible. The processing circuit is configured to output as an output signal at least one of a first signal obtained from the first strain sensing element upon application of external pressure to the transducing thin film and a second signal obtained from the second strain sensing element upon application of the external pressure to the transducing thin film.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: November 8, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideaki Fukuzawa, Masatoshi Sakurai, Masayuki Kii, Yoshihiko Fuji, Michiko Hara, Yoshihiro Higashi, Kenji Otsu, Akiko Yuzawa, Kazuaki Okamoto
  • Patent number: 9435858
    Abstract: Focusing optical systems and methods for testing semiconductors are disclosed herein. The methods include receiving an image of a probe through a single optical path of a microscope, substantially focusing the microscope on the probe, and determining a vertical height adjustment between the probe and a device under test based upon the focusing.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: September 6, 2016
    Assignee: CASCADE MICROTECH, INC.
    Inventors: Peter Andrews, David Hess
  • Patent number: 9423421
    Abstract: A testing head for a test equipment of electronic devices of the type includes a plurality of contact probes inserted into guide holes which are realized in at least an upper guide and a lower guide separated one another by an air zone. Each of such contact probes include at least a probe body having a substantially rectangular section and a projecting arm from the probe body which ends with a probe tip for contacting one of a plurality of contact pads of a device to be tested. The projecting arm projects outside the probe body so as to have a lug with respect to both faces of the probe body which converge in an edge in order to define a probe tip offset and external with respect to the probe body.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: August 23, 2016
    Assignee: Technoprobe S.p.A.
    Inventor: Stefano Lazzari
  • Patent number: 9417285
    Abstract: A device for testing a bottom package of an integrated fan-out (InFO) Package-on-Package (PoP) comprises a bottom fixture having a space to accommodate the bottom package during testing and a detachable top cover, configured for conducting at least one test of the bottom package, wherein one or both of the bottom fixture and the top cover have a plurality of probing contacts for testing of the bottom package and wherein the device can be opened for placement of the bottom package under testing, and the cover is attachable to the bottom fixture for conducting the testing.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: August 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Hao Chen
  • Patent number: 9366696
    Abstract: An apparatus for testing of a plurality of electronic devices on a flexible substrate is described. The apparatus includes at least two rollers configured for guiding the flexible substrate into a testing area along transport direction, at least one prober configured for electrically contacting one or more of the electronic devices, at least one probing support configured for supporting a portion of the flexible substrate during electrical contact with the at least one prober, and a test device for functional testing of one or more of the electronic devices.
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: June 14, 2016
    Assignee: Applied Materials, Inc.
    Inventor: Matthias Brunner
  • Patent number: 9368232
    Abstract: In a particular embodiment, a method includes controlling a temperature within a chamber while applying a magnetic field. A device including a memory array is located in the chamber. The method includes applying a magnetic field to the memory array and testing the memory array during application of the magnetic field to the memory array at a target temperature.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: June 14, 2016
    Assignee: Qualcomm Incorporated
    Inventors: Kangho Lee, Wah Nam Hsu, Xiao Lu, Seung H. Kang
  • Patent number: 9360502
    Abstract: Testing methods and systems are described. One method for testing an electronic device includes providing a probe in electrical contact with a device. The method also includes positioning an interface of the probe and the device in a liquid medium. The method also includes transmitting a current from the probe through the interface while the interface is in the liquid medium. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 31, 2011
    Date of Patent: June 7, 2016
    Assignee: INTEL CORPORATION
    Inventors: Warren S. Crippen, Brett Grossman, Roy E. Swart, Pooya Tadayon
  • Patent number: 9337074
    Abstract: An attaching device configured to attach a substrate and a support via an adhesive layer is provided with support holding members. Holding tools of the support holding members are configured to hold the support with oblique surface parts (contact members) of the holding tools without coming into contact with a surface of the support, which is to be attached to the substrate. The attaching device attaches, to the substrate, the support of which the surface is held not to be contacted.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: May 10, 2016
    Assignee: TOKYO OHKA KOGYO CO., LTD.
    Inventors: Yoshihiro Inao, Shigeru Kato, Shugo Tsushima, Junichi Katsuragawa, Satoshi Kobari, Akihiko Nakamura
  • Patent number: 9267985
    Abstract: An integrated circuit (IC) that includes a plurality of bond pads disposed on a surface of the IC and a plurality of probe pads disposed on the surface of the IC is provided. Each of the plurality of probe pads is in electrical communication with corresponding bond pads. The plurality of probe pads are linearly configured across the surface. In one embodiment, the probe pads are disposed along a diagonal of the surface of the die defined between opposing vertices of the die surface. In another embodiment, multiple rows of linearly disposed probe pads are provided on the surface.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: February 23, 2016
    Assignee: Altera Corporation
    Inventor: William Y. Hata
  • Patent number: 9151696
    Abstract: A gage tool (700) for inspecting tolerances of a gas turbine engine seal plate (430) includes a base plate (710) and a top plate (720). The base plate (710) includes a base opening (712) and a slot (711) with an annular shape sized to receive a seal plate (430). The top plate (720) includes a top opening (723). The base opening (712) and top opening (723) each provide access to a portion of a seal plate (430) within the gage tool (700). The gage tool (700) also includes a first gage (750) with a probe tip for measuring a variation in an outer interlacing surface (433) of a seal plate (430) and a seal slide gage (740) for measuring a force required to rotate the seal plate (430) within the gage tool.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: October 6, 2015
    Assignee: Solar Turbines Incorporated
    Inventors: James Brian Powell, Scott L. Stafford, Luvern John Weber, Terry Toshio Akiyama
  • Patent number: 9154972
    Abstract: A wireless electronic device may be provided with antenna structures. The antenna structures may be formed from an antenna ground and an array of antenna resonating elements formed along its periphery. The antenna resonating elements may be formed from metal traces on a dielectric support structure that surrounds the antenna ground. The electronic device may be tested using a test system for detecting the presence of manufacturing/assembly defects. The test system may include an RF tester and a test fixture. The device under test (DUT) may be attached to the test fixture during testing. Multiple test probes arranged along the periphery of the DUT may be used to transmit and receive RF test signals for gathering scattering parameter measurements on the device under test. The scattering parameter measurements may then be compared to predetermined threshold values to determine whether the DUT contains any defects.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: October 6, 2015
    Assignee: Apple Inc.
    Inventors: Jerzy Guterman, Joshua G. Nickel, Boon W. Shiu, Mattia Pascolini
  • Patent number: 9069008
    Abstract: An inspection apparatus is provided, which includes probes for front side electrodes, probes for back side electrodes, and a chuck stage. The probes for front side electrodes and the probes for back side electrodes are formed on the upper surface of the chuck stage, and the probe contact area electrically continues to the wafer holding area, and the probes for front side electrodes and the probes for back side electrodes are located leaving a distance in horizontal direction between them so that the probes for back side electrodes move relatively within the probe contact area when the probes for front side electrodes are moved relatively within the wafer under test by the movement of the chuck stage.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: June 30, 2015
    Assignee: KABUSHIKI KAISHA NIHON MICRONICS
    Inventors: Katsuo Yasuta, Hikaru Masuta, Hideki Nei
  • Publication number: 20150145541
    Abstract: An inspection apparatus and an inspection method capable of reducing the effect of noises are provided. An inspection apparatus according to the present invention includes a work table 26 on which an inspection panel 12 is placed, a probe unit 31 including a probe 38 that comes into contact with an electrode 12a of the inspection panel 12 placed on the work table 26, and a stage 11 that moves the work table 26 in order to bring the probe 38 into contact with the electrode 12a of the inspection panel 12 placed on the work table 26, in which the stage 11 is connected to the ground and supports the work table 26 through a resistive element.
    Type: Application
    Filed: November 13, 2014
    Publication date: May 28, 2015
    Inventors: Takayoshi KUDO, Katsuhiko KIMURA, Takahiro FUKUSHI, Kazuyoshi MIURA
  • Publication number: 20150109011
    Abstract: A method of testing an integrated circuit of a device is described. Air is allowed through a fluid line to modify a size of a volume defined between the first and second components of an actuator to move a contactor support structure relative to the apparatus and urge terminals on the contactor support structure against contacts on the device. Air is automatically released from the fluid line through a pressure relief valve when a pressure of the air in the fluid line reaches a predetermined value. The holder is moved relative to the apparatus frame to disengage the terminals from the contacts while maintaining the first and second components of the actuator in a substantially stationary relationship with one another. A connecting arrangement is provided including first and second connecting pieces with complementary interengaging formations that restricts movement of the contactor substrate relative to the distribution board substrate in a tangential direction.
    Type: Application
    Filed: December 26, 2014
    Publication date: April 23, 2015
    Applicant: AEHR TEST SYSTEMS
    Inventors: Scott E. Lindsey, Junjye Yeh, Jovan Jovanovic, Seang P. Malathong
  • Patent number: 9007081
    Abstract: A jig for use in a semiconductor test of the present invention includes; a base on which a probe pin and an insulating material are provided such that the probe pin is surrounded by the insulating material in plan view; and a stage arranged to face a surface of the base on which the probe pin and the insulating material are provided. The stage is capable of receiving a test object placed on a surface facing the base. When the test object is placed on the stage and the base and the stage move in a direction in which they get closer to each other, the probe pin comes into contact with an electrode formed on the test object, and the insulating material comes into contact with both the test object and the stage.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: April 14, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventor: Masaaki Ikegami
  • Patent number: 9000798
    Abstract: A system and method for aligning a probe, such as a wafer-level test probe, with wafer contacts is disclosed. An exemplary method includes receiving a wafer containing a plurality of alignment contacts and a probe card containing a plurality of probe points at a wafer test system. A historical offset correction is received. Based on the historical offset correct, an orientation value for the probe card relative to the wafer is determined. The probe card is aligned to the wafer using the orientation value in an attempt to bring a first probe point into contact with a first alignment contact. The connectivity of the first probe point and the first alignment contact is evaluated. An electrical test of the wafer is performed utilizing the aligned probe card, and the historical offset correction is updated based on the orientation value.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Long Chen, Chien-Chih Liao, Tseng Chin Lo, Hui-Yun Chao, Ta-Yung Lee, Jong-I Mou, Chin-Hsiang Lin
  • Patent number: 8981809
    Abstract: A compliant printed circuit semiconductor tester interface that provides a temporary interconnect between terminals on integrated circuit (IC) devices being tested. The compliant printed circuit semiconductor tester interface includes at least one dielectric layer printed with recesses corresponding to a target circuit geometry. A conductive material is deposited in at least a portion of the recesses comprising a circuit geometry and a plurality of first contact pads accessible along a first surface of the compliant printed circuit. At least one dielectric covering layer is preferably applied over the circuit geometry. A plurality of openings in the dielectric covering layer are provided to permit electrical coupling of terminals on the IC device and the first contact pads. Testing electronics that to test electrical functions of the IC device are electrically coupled to the circuit geometry.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: March 17, 2015
    Assignee: Hsio Technologies, LLC
    Inventor: James Rathburn
  • Publication number: 20150015285
    Abstract: A probe apparatus can suppress a spark from occurring near a wafer surface simply and efficiently when inspecting electrical characteristics of a semiconductor device at wafer level. A spark preventing device 50 mounted in the probe apparatus includes a surrounding member 52 which surrounds probe needles 24G and 24S between a probe card 16 and a mounting table 12; and a gas supply device 54 configured to supply a gas to a vicinity of the probe needles 24G and 24S through an inside or a vicinity of the surrounding member 52 to form an atmosphere of a preset pressure higher than an atmospheric pressure in the vicinity of the probe needles 24G and 24S when inspecting the electrical characteristics of each chip on a semiconductor wafer W. A contact plate 34 also serves as the surrounding member 52.
    Type: Application
    Filed: July 11, 2014
    Publication date: January 15, 2015
    Inventors: Eiichi Shinohara, Kenji Yamaguchi, Masataka Hatta
  • Patent number: 8872532
    Abstract: Wafer cassette systems and methods of using wafer cassette systems. A wafer cassette system can include a base and a probe card assembly. The base and the probe card assembly can each include complementary interlocking alignment elements. The alignment elements can constrain relative movement of the base and probe card assembly in directions parallel to a wafer receiving surface of the base, while permitting relative movement in a direction perpendicular to the receiving surface.
    Type: Grant
    Filed: December 27, 2010
    Date of Patent: October 28, 2014
    Assignee: FormFactor, Inc.
    Inventors: Keith J. Breinlinger, Eric D. Hobbs
  • Patent number: 8866503
    Abstract: A method for correcting inclination of a wafer chuck includes obtaining in advance a correction amount for each of the semiconductor chips which corrects the inclination of the wafer chuck in the case of applying a contact load to at least each one of the semiconductor chips and storing each of the correction amounts in a data storage unit; calculating a total correction amount for correcting the inclination of the wafer chuck by calculating the correction amount of each of the semiconductor chips bringing into contact with the probes when the semiconductor wafer comes into electrical contact with the probes and adding the calculated correction amounts; and correcting the inclination of the wafer chuck based on the total correction amount.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: October 21, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Kazunari Ishii, Toshihiko Iijima, Shuji Akiyama
  • Patent number: 8847618
    Abstract: A circuit board tester and method that precisely aligns the probe plate and circuit board is disclosed. With a circuit board and probe plate mounting within a housing having a top and bottom, hinged together, at closure there may be slight misalignments of the two. By making one of the two plates floating, or laterally slideable with respect to each other, it is possible to make final alignment at closure. One of the two plates can be provided with a pin and the other with a pin receiving alignment block. With the lateral slideability, the pin and block can insure proper probe alignment. Additional systems for correcting misaligned pins or blocks are also disclosed.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: September 30, 2014
    Assignee: Circuit Check, Inc.
    Inventors: Gregory J. Michalko, Stuart K. Eickhoff, Jon A. Hample, Russell G. Carter