Using Optical Means Patents (Class 324/750.23)
  • Patent number: 11908753
    Abstract: Herein disclosed is a test head connection method, the method comprises the following steps. First, a load board and a card holder are provided between a test head and a probing machine, the card holder is disposed in the probing machine, and the card holder is used to accommodate the load board. A vacuum function of the test head is activated, and the test head is moved to align the card holder. The test head is moved to touch the load board in the card holder. At least one clamping piece is used to fix the test head and the card holder. Wherein the load board and a wafer are connected by direct probing.
    Type: Grant
    Filed: November 6, 2021
    Date of Patent: February 20, 2024
    Assignee: Chroma ATE Inc.
    Inventors: Kao-Shan Yang, Ching-Li Lin
  • Patent number: 11714106
    Abstract: Provided is a technique capable of improving test efficiency of semiconductor devices. A test apparatus includes a probe card having a plurality of measurement sites that contact with a plurality of semiconductor devices formed on a semiconductor wafer; a control unit configured to generate map information, probe-card form information, and contact-position information, the map information including position information and peculiar information of the semiconductor devices on the semiconductor wafer, the probe-card form information including arrangement information of the measurement sites, the contact-position information indicating a contact position that is a range of the semiconductor device tested at one time by the probe card based on constrained-condition information of limiting contact with the probe card; and a position control unit configured to control a relative position between the probe card and the semiconductor wafer based on the contact-position information.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: August 1, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kazuhiro Sakaguchi
  • Patent number: 11340263
    Abstract: There is provided a probe device for inspecting a wafer. The probe device includes: an upper camera provided in a wafer alignment unit; a lower camera provided in a stage; a target member provided in any one of the wafer alignment unit and the stage; and a control circuit configured to control each operation of the upper and lower camera. The target member has an end surface on which a target mark is provided, wherein any of the upper and lower camera is configured to capture an image of the target mark. The control circuit is configured to acquire a captured image of the target mark using any of the upper camera and the lower camera; and calculate a correspondence between a specific physical parameter and a value represented in the captured image for a parameter represented in the captured image among physical parameters, based on the acquired captured image.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: May 24, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Muneaki Tamura
  • Patent number: 11315832
    Abstract: A method for monitoring and controlling a substrate singulation process is described. Device edges are imaged and identified for analysis. Discrepancies in device edges are noted and used to modify a singulation process and to monitor the operation of singulation processes for anomalous behavior.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: April 26, 2022
    Assignee: Onto Innovation Inc.
    Inventor: Wayne Fitzgerald
  • Patent number: 11280959
    Abstract: An intact semiconductor wafer (wafer) includes a plurality of die. Each die has a top layer including routings of conductive interconnect structures electrically isolated from each other by intervening dielectric material. A top surface of the top layer corresponds to a top surface of the wafer. Below the top layer, each die has a device layer including optical devices and electronic devices. Each die has a cladding layer below the device layer and on a substrate of the wafer. Each die includes a photonic test port within the device layer. For each die, a light transfer region is formed within the intact wafer to extend through the top layer to the photonic test port within the device layer. The light transfer region provides a window for transmission of light into and out of the photonic test port from and to a location on the top surface of the wafer.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: March 22, 2022
    Assignee: Ayar Labs, Inc.
    Inventors: Roy Edward Meade, Chen Sun, Shahab Ardalan, John Fini, Forrest Sedgwick
  • Patent number: 11262400
    Abstract: A probing system includes a chuck configured to support a device under test (DUT); a probe card disposed above the chuck and including a plurality of probes protruding from the probe card toward the chuck; and a platen disposed between the chuck and the probe card and configured to support the probe card, wherein the chuck includes a shielding member disposed between the platen and the chuck.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: March 1, 2022
    Assignee: TECAT TECHNOLOGIES (SUZHOU) LIMITED
    Inventor: Choon Leong Lou
  • Patent number: 11226367
    Abstract: The present invention relates to a substrate testing cartridge provided for simultaneously testing multiple substrates for which a substrate treatment process has been finished, and a method for manufacturing same. According to an embodiment of the present invention, a substrate testing cartridge comprises: a chuck member on which a substrate is placed; a probe card which contacts and tests the substrate and is positioned to face the chuck member with reference to the substrate; and coupling members which couple the substrate, the chuck member, and the probe card, wherein each coupling member comprises: a substrate coupling part which couples the substrate and the chuck member; and a chuck coupling part which couples the probe card and the chuck member.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: January 18, 2022
    Assignee: KOREA INSTITUTE OF INDUSTRIAL TECHNOLOGY
    Inventors: Kyung Tae Nam, Sang Moo Lee, Seung Joon Lee, Kwang Hee Lee, Sung Won Choo
  • Patent number: 11226390
    Abstract: An example method, such as a calibration method, includes: determining a geometry of an arrangement of cells that is perceived by a robot configured to move devices into, and out of, the cells; determining an expected location of a target cell among the cells; determining an offset from the expected location that is based on the geometry that is perceived by the robot; and calibrating the robot based on the offset.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: January 18, 2022
    Assignee: Teradyne, Inc.
    Inventor: Adnan Khalid
  • Patent number: 11148223
    Abstract: This laser processing machine, which moves a work piece, which is mounted on a table, and an optical head, which shines a laser light, relative to each other, and processes the work piece by irradiating the work piece with the laser light, is provided with: a calibration camera that is fixed to the optical head; a probe that is fixed to the optical head; and a calibration unit that has measurement reference points (Pc1, Pc2, Pc3, Pp1, Pp2, Pp3) for measuring the position of the calibration camera and the probe, and a processing portion that forms a processing mark (L1, L2) due to the laser light.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: October 19, 2021
    Assignee: MAKINO MILLING MACHINE CO., LTD.
    Inventors: Hiroshi Toyama, Muneaki Beppu
  • Patent number: 11125780
    Abstract: A test probe assembly for determining the integrity of a test pad of a semiconductor wafer. The test probe assembly includes a probe card, a plurality of test probes mounted to the probe card, a fiber optic lead mounted to each test probe and arranged to direct incident light toward individual test pads of the semiconductor wafer and a plurality of photodetectors arranged about the probe card. Individual photodetectors are configured to receive light reflected off a dielectric coating of the test pad corresponding to a first set of light rays emitted by the test pad and configured to receive light reflected off a metallic base of the test pad corresponding to a second set of light rays emitted by the test pad, and to generate first and second output signals associated with the first and second sets of light rays to create image data of the individual test pads.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: September 21, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kushagra Sinha, Pablo Nieves, Reinaldo Vega
  • Patent number: 11119148
    Abstract: A test probe assembly includes a probe card, a plurality of test probes mounted to the probe card with each of the test probes having a probe tip segment and a probe end for positioning adjacent respective individual test pads of a semiconductor wafer, and a fiber optic lead mounted to each test probe. The fiber optic leads are arranged to direct incident light toward respective individual test pads of the semiconductor wafer. A plurality of photodetectors may be arranged about the probe card with individual photodetectors configured for reception of light reflected off the respective individual test pads to emit output signals used to generate image data representative of the individual test pads on the semiconductor wafer. The image data may be utilized to align the test pads with the test probes for subsequent testing.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: September 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Pablo Nieves, Kushagra Sinha, Reinaldo Vega
  • Patent number: 10996277
    Abstract: A method includes receiving a first confidence level from a first battery sensor coupled to a first battery electrically coupled to an engine; receiving a second confidence level from a second battery sensor coupled to a second battery electrically coupled to the engine; storing the first confidence level and the second confidence level prior to the engine being powered off; receiving an updated first confidence level and an updated second confidence level after the engine is powered on; comparing (i) the first confidence level to the updated first confidence level for the first battery sensor and (ii) the second confidence level to the updated second confidence level for the second battery sensor; and enabling a stop-start functionality of the engine in response to the first confidence level and the second confidence level decreasing after the engine system is powered on relative to when the engine system was powered off.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: May 4, 2021
    Assignee: Cummins Inc.
    Inventors: Martin T. Books, Carl A. Jones
  • Patent number: 10725091
    Abstract: An example test system includes: a test rack including test slots; first and second shuttles that are configured to move contemporaneously to transport devices towards and away from trays, with at least some of the devices having been tested and at least some of the devices to be tested; first and second robots that are configured to move contemporaneously to move the devices that have been tested from test sockets in test carriers to the first and second shuttles, and to move the devices to be tested from the first and second shuttles to the test sockets in test carriers; and first and second test arms that are configured to move contemporaneously to move the test carriers between the first and second robots and the test rack.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: July 28, 2020
    Assignee: TERADYNE, INC.
    Inventors: David Paul Bowyer, Jianfa Pei, John P. Toscano, Philip Campbell, Marc LeSueur Smith
  • Patent number: 10679334
    Abstract: An electronic component handler includes a region where an electronic component placing unit on which an electronic component is placed is capable of being disposed. A transport unit includes a first hand and a second hand for holding and transporting the electronic component. A light irradiation unit is capable of emitting light toward the electronic component placing unit and is capable of adjusting an emitting direction of the light. A capturing unit is capable of capturing an image of the electronic component placing unit irradiated with the light via a space between the first hand and the second hand. A control unit performs determination processing about the presence or absence of the electronic component in the electronic component placing unit based on the image captured by the capturing unit.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: June 9, 2020
    Assignee: Seiko Epson Corporation
    Inventors: Takahito Sanekata, Hirokazu Ishida, Daisuke Ishida
  • Patent number: 10620159
    Abstract: A Kelvin probe system is provided. The invention is achieved using a rotating Kelvin probe head comprising a Kelvin probe face is provided on a side face of the Kelvin probe head.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: April 14, 2020
    Assignee: INDIKEL AS
    Inventors: Eugen Florin Turcu, Michael Rohwerder
  • Patent number: 10520392
    Abstract: An optical measurement apparatus configured to measure a photonic integrated circuit (photonic IC) is provided. The optical measurement apparatus includes a substrate, at least one optical waveguide device, a first connector, and a second connector. The at least one optical waveguide device is disposed on the substrate. The first connector and the second connector are connected with the at least one optical waveguide device. An optical signal from a first optical fiber is transmitted to the at least one optical waveguide device through the first connector, transmitted to the inside of the photonic IC though at least one first evanescent coupler of the photonic IC, transmitted to the at least one optical waveguide device through at least one second evanescent coupler of the photonic IC, and transmitted to a second optical fiber through the second connector in sequence.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: December 31, 2019
    Assignee: Industrial Technology Research Institute
    Inventor: Shang-Chun Chen
  • Patent number: 10520391
    Abstract: An optical measurement apparatus configured to measure a photonic integrated circuit (photonic IC) is provided. The optical measurement apparatus includes a substrate, at least one optical waveguide device, a first connector, and a second connector. The at least one optical waveguide device is disposed on the substrate. The first connector and the second connector are connected with the at least one optical waveguide device. An optical signal from a first optical fiber is transmitted to the at least one optical waveguide device through the first connector, transmitted to the inside of the photonic IC though at least one first evanescent coupler of the photonic IC, transmitted to the at least one optical waveguide device through at least one second evanescent coupler of the photonic IC, and transmitted to a second optical fiber through the second connector in sequence.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: December 31, 2019
    Assignee: Industrial Technology Research Institute
    Inventor: Shang-Chun Chen
  • Patent number: 10416229
    Abstract: Provided is a wafer inspection method wherein a chuck top can be properly received. When an aligner receives a chuck top after a wafer W has been inspected, the distance between the chuck top and a chuck base is adjusted by adjusting the inclination of the chuck base such that the chuck top height, which is the distance between the chuck top and the chuck base after the chuck top is held, is a height in which any of 0 to 200 ?m is added to the chuck top height before the chuck top is held.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: September 17, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Hiroshi Yamada
  • Patent number: 10416228
    Abstract: To provide a prober and a probe contact method capable of enhancing the reliability of electrical contact between electrode pads on a wafer and probes. A prober includes a wafer chuck, a probe card, a ring-shaped seal member provided on the wafer chuck, a Z-axis moving/rotating unit which lifts up and down the wafer chuck detachably fixed to a wafer chuck fixing part, a decompressor which depressurize an internal space formed by the probe card, the wafer chuck and the ring-shaped seal member, a lifting controller which controls the Z-axis moving/rotating unit to bring probes into contact with electrode pads in an overdrive condition, and a depressurization controller which controls the decompressor such that the wafer chuck is drawn to the probe card by depressurization of the internal space.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: September 17, 2019
    Assignee: Tokyo Seimitsu Co., Ltd.
    Inventor: Hideaki Nagashima
  • Patent number: 10408733
    Abstract: A method for determining the presence of crystalline silica particles in a sample comprising a plurality of particles. The method comprises: receiving first data generated based upon light scattered by at least one particle of said plurality of particles; receiving second data generated based upon intensity and polarization change of the light transmitted through at least one particle of said plurality of particles; and determining the presence of crystalline silica particles in the sample based upon the first data and second data.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: September 10, 2019
    Assignee: Trolex Limited
    Inventors: Paul Henry Kaye, William Eugene Martin
  • Patent number: 10324127
    Abstract: An electronic component handling apparatus (10) is provided which can improve the operation rate. The electronic component handling apparatus (10) includes: a contact arm (300) having a holding part (380) configured to hold a DUT (10A), the contact arm (300) being configured to press the DUT (10A) against a socket (410); an alignment device (200) including a camera (221) and a operation unit (230), the camera (221) being configured to image the DUT (10A) to acquire image information, the operation unit (230) being configured to adjust a position of the holding part (380) within a range of a maximum alignment amount (ALmax); and a control device (105) configured to control the contact arm (300) and the alignment device (200). When a predetermined condition is not satisfied, the control device (105) controls the contact arm (300) and the alignment device (200) so as to perform preliminary alignment work at least once.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: June 18, 2019
    Assignee: ADVANTEST CORPORATION
    Inventors: Yasuyuki Kato, Masataka Onozawa, Keisuke Nitta
  • Patent number: 10209273
    Abstract: A probe position inspection apparatus capable of inspecting the position of contact portions of respective probe tips easily and accurately, an apparatus for inspecting a semiconductor device, and a method of inspecting a semiconductor device are provided. The probe position inspection apparatus includes a transparent plate, a camera for taking an image of one surface of the transparent plate, and a pressure passive member covering the other surface of the transparent plate. The tip of a probe for use in evaluation of a semiconductor device is pressed against the other surface of the transparent plate, with the pressure passive member therebetween. The probe position inspection apparatus further includes an image processor for processing the image taken by the camera to detect the position of the probe in the plane of the transparent plate.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: February 19, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Norihiro Takesako, Takaya Noguchi, Akira Okada
  • Patent number: 10115620
    Abstract: Disclosed is an apparatus for handling electronic components and a method of adjusting the position of at least one handling device of an apparatus for handling electronic components.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: October 30, 2018
    Assignee: ASM TECHNOLOGY SINGAPORE PTE LTD
    Inventors: Yu Sze Cheung, Chi Wah Cheng, Chi Fung Chan
  • Patent number: 9989587
    Abstract: A die tester comprising a testing table on which a plurality of dice arranged in an array are mountable, and a first probe and a second probe that are adjustable to a fixed position with a fixed separation distance between the first probe and the second probe. The fixed position corresponds to predetermined test points on the plurality of dice, and the testing table and the first and second probes are movable relative to each other so as to position test points of a first die of the plurality of dice to the first probe and the second probe for testing the first die. The die tester further comprises movable third and fourth probes that are movable relative to each other and positionable to test points on a second die of the plurality of dice for testing the second die.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: June 5, 2018
    Assignee: ASM TECHNOLOGY SINGAPORE PTE LTD
    Inventors: Yam Mo Wong, Kui Kam Lam, Kai Siu Lam, Ka Wai Chan
  • Patent number: 9842823
    Abstract: A chip-stacking apparatus for stacking a chip on a substrate is provided. The chip-stacking apparatus includes a substrate support configured to carry the substrate and a transport device configured to dispose a chip to the substrate. The transport device includes a bond head including a bond base and an attaching element disposed on the bond base and configured to allow the chip to be attached thereon. The center area of the attaching element is higher than an edge area of the attaching element relative to the bond base.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: December 12, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Hua Yu, HsiaoYun Lo, Yi-Hsiu Chen, Wen-Chih Chiou
  • Patent number: 9804196
    Abstract: Probes with fiducial marks, probe systems including the same, and associated methods. The probes include a beam portion and a probe tip that is configured to contact a device under test (DUT), and further include a fiducial mark formed on the beam portion that is configured to facilitate alignment of the probe and the DUT. The fiducial mark is configured to be visible to an optical assembly, and is in focus to the optical assembly within a depth of field of the optical assembly that is smaller than a depth of field over which the beam portion is in focus to the optical assembly. The methods include methods of utilizing and/or manufacturing the probes.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: October 31, 2017
    Assignee: Cascade Microtech, Inc.
    Inventors: Bryan Conrad Bolt, Joseph George Frankel
  • Patent number: 9684052
    Abstract: A method of assessing functionality of a probe card includes providing a probe card analyzer without a probe card interface, removably coupling a probe card having probes to a support plate of the probe card analyzer, aligning a sensor head of the probe card analyzer with the probe card, and measuring a component of the probes with the sensor head.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: June 20, 2017
    Assignee: Rudolph Technologies, Inc.
    Inventor: Greg Olmstead
  • Patent number: 9523708
    Abstract: An electrical testing device includes a base having two parallel first rails, a platform provided on the base, a support provided between the first rails, a test arm, a rotary table provided on the test arm, a plurality of holders provided on the rotary table, and a plurality of probe sets respectively provided on the holders. The support has a second rail provided thereon, and is moveable relative to the base and the platform. The test arm is provided on the second rail and above the platform, wherein the test arm is moveable along with the support, and is also movable relative to the support. The rotary table is moveable or rotatable relative to the test arm. The holders are moveable along with the rotary table, and are also moveable or rotatable relative to the rotary table. The probe sets are moveable along with the holders.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: December 20, 2016
    Assignee: MPI Corporation
    Inventors: Wei-Cheng Ku, Shao-Wei Lu, Ya-Hung Lo, Shou-Jen Tsai
  • Patent number: 9322843
    Abstract: A “Theta” angle adjustment tool is made of a solid parallelepiped and adjusting screw, that allows the wafer probes to be fastened to the auxiliary equipment under correcting “Theta” angles. The procedure consists of loosening the probe and pressing hard on the tool to force the probe to adjust to the intended slope (“Theta”) and then fastening the probe under pressure against the tool and chuck surface. Following that the marks left when the probe tips touch the wafer are assessed and corrective action is taken regarding “Theta misalignment”.
    Type: Grant
    Filed: March 19, 2013
    Date of Patent: April 26, 2016
    Inventor: Christos Tsironis
  • Patent number: 9312752
    Abstract: An electronics apparatus having a housing, an inverting device, a first circuit board connected to the inverting device via at least one line, and a second circuit board connected via a first galvanic connection to the first circuit board and connected via a second galvanic connection to at least component, and having a first filter situated on the first circuit board and upstream from the first galvanic connection, the first filter having a first discharge connection to the housing, and having a second filter situated on the second circuit board and downstream from the first galvanic connection, the second filter having a second discharge connection to the housing, and having a third filter situated on the second circuit board and upstream from the second galvanic connection, the third filter having a third discharge connection to the housing. A method for producing an electronics apparatus is also described.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: April 12, 2016
    Assignee: ROBERT BOSCH GMBH
    Inventor: Hartmut Sparka
  • Patent number: 9310429
    Abstract: A semiconductor wafer resting on a contact element has a spatially distributed force applied to its frontside and an equal and opposing force applied to its backside. The contact element comprises a solid immersion lens (SIL), and has an area less than the area of the wafer, but no less than the larger of the area of an optical collection area and an electrical probe assembly. The equal and opposing forces cause the wafer to conform to the shape of the contact element. Measurements, including electrical testing, optical probing and wafer characterization are performed on the wafer.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: April 12, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephen Bradley Ippolito, Alan J. Weger
  • Patent number: 9110131
    Abstract: The invention generally relates to a method and device for contacting contact areas (22) with probe tips (18) in a tester. The contact areas (22), which are arranged on a substrate (6), and the probe tips (18) are positioned relative to each other and then brought in contact with each other by an advancing motion. In order to detect a secure contact for each of the probe tips (18), the contacting between the probe tips (18) and the contact areas (22) is observed from at least two observation directions (34), which include an observation angle ? in a range of 0 to 180°.
    Type: Grant
    Filed: April 13, 2010
    Date of Patent: August 18, 2015
    Assignee: Cascade Microtech, Inc.
    Inventors: Claus Dietrich, Stojan Kanev, Frank Fehrmann, Botho Hirschfeld
  • Patent number: 9093179
    Abstract: A method for improving test coverage of pads of a chip, where the chip includes a control unit, a plurality of pads, and a storage unit, and the storage unit includes a plurality of blocks, includes writing test data to a first predetermined block through a predetermined pad of the plurality of pads, controlling a first pad to read and store a predetermined datum of the test data from the first predetermined block, controlling the first pad to write the predetermined datum to a second predetermined block, reading the predetermined datum stored in the second predetermined block through the predetermined pad, and determining whether the first pad is passed.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: July 28, 2015
    Assignee: Etron Technology, Inc.
    Inventors: Shih-Hsing Wang, Ming-Cheng Liang, Kuo-Cheng Ting
  • Patent number: 9024648
    Abstract: A handler for conveying DUTs to a socket for a test that can reduce a test time includes: a test section including the socket; a heat applying section into which a tray having plural DUTs placed on its surface is conveyed and that controls the temperature of the DUTs to a predetermined test temperature and conveys the tray into the test section; and a device image capturing section that includes imaging elements arranged along a first direction the number of which is equal to DUTs arranged along the first direction and that in the heat applying section, captures images of the DUTs by moving the imaging elements relative to the surface of the tray in a second direction non-parallel with the first direction; and a position adjusting section that adjusts the positions of the DUTs relative to the socket based on their images captured by the device image capturing section.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: May 5, 2015
    Assignee: Advantest Corporation
    Inventors: Hiromitsu Horino, Masataka Onozawa
  • Publication number: 20150015286
    Abstract: A vision alignment system for an integrated circuit device testing handler includes a head guiding ring configured to be attached to a pick-and-place device, the head guiding ring having an opening in which a device-under-test having a device contact array is locatable; a socket apparatus including: a fixed mounting frame, a moveable socket guiding ring, and a plurality of actuators configured to move the moveable socket guiding ring relative to the fixed mounting frame; and a visualization device configured to provide data relating to a position of the device contact array relative to the contactor pin array. The socket apparatus is configured to adjust a position of the head guiding ring by moving the moveable socket guiding ring while the head guiding ring is located in an opening of the moveable socket guiding ring to align the device contact array to the contactor pin array.
    Type: Application
    Filed: July 11, 2014
    Publication date: January 15, 2015
    Inventors: Kexiang Ken DING, Keith EMERY, Jerry Ihor TUSTANIWSKYJ, Michael Anthony LAVER, Samer KABBANI
  • Patent number: 8907696
    Abstract: There is provided a test apparatus for testing a device under test, including a test signal generator that generates a test signal to test the device under test, an electric-photo converter that converts the test signal into an optical test signal, an optical interface that (i) transmits the optical test signal generated by the electric-photo converter to an optical receiver of the device under test and (ii) receives and outputs an optical response signal output from the device under test, a photo-electric converter that converts the optical response signal output from the optical interface into an electrical response signal and transmits the electrical response signal, and a signal receiver that receives the response signal transmitted from the photo-electric converter and a test method.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: December 9, 2014
    Assignee: Advantest Corporation
    Inventor: Shin Masuda
  • Patent number: 8901525
    Abstract: The present invention provides a panel alignment apparatus and a panel alignment method. The panel alignment apparatus comprises an image detection device and a first clamp. The method comprises the following steps: utilizing the image detection device to detect a position of a display panel, and to calculate a position adjustment value; and utilizing the first clamp to hold the standing display panel, and to rotate the display panel according to the position adjustment value for adjusting a position of the display panel. The present invention can utilize the clamps to precisely align the standing display panel.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: December 2, 2014
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventors: Jiasheng Lu, Teng-chou Wei
  • Publication number: 20140347081
    Abstract: A semiconductor device assessment apparatus that electrically assesses a semiconductor device formed on a semiconductor substrate includes a holding unit having a surface to hold the semiconductor substrate thereon, and a detection unit to detect irregularity on the surface of the holding unit. The holding unit on the surface includes a plurality of grooves formed such that when the semiconductor substrate is held on the surface, the grooves overlap a periphery of the semiconductor substrate and also have a portion located outer than the periphery of the semiconductor substrate.
    Type: Application
    Filed: February 24, 2014
    Publication date: November 27, 2014
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hajime AKIYAMA, Akira OKADA, Kinya YAMASHITA
  • Patent number: 8896333
    Abstract: A shutdown apparatus and method for use in conjunction with automatic test equipment (ATE) is provided. A unit under test (UUT) is inserted into an ATE receiver that couples the UUT to at least one electronic device during test and extracted from the ATE receiver after test. The shutdown apparatus comprises an electro-mechanical interface that inserts the UUT into the receiver prior to test and extracts the UUT from the receiver after test A shutdown module is coupled to the electronic device and to the electro-mechanical interface and connects the electronic device to the receiver after insertion of the UUT into the receiver and disconnects the electronic device from the receiver prior to extraction of the UUT from the receiver.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: November 25, 2014
    Assignee: Honeywell International Inc.
    Inventors: Kenny Nordstrom, Krishna Munirathnam, Santhoshkumar Ramasamy
  • Patent number: 8816709
    Abstract: An electronic component testing device includes a first imaging device for imaging an upper-surface electrode of an electronic component before the electronic component is held by a holding part, a second imaging device for imaging a contact terminal provided to a testing head, a third imaging device for imaging a lower-surface electrode of the electronic component held by the holding part, and a fourth imaging device for imaging a testing socket. A control device controls the position adjustment part of the testing head to adjust the position of the holding part, and thereby controlling, based on images captured by the first and second imaging devices, a holding orientation when the holding part holds the electronic component, and controlling, based on the images captured by the third and fourth imaging devices, a holding orientation of the holding part in relation to the testing socket.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: August 26, 2014
    Assignee: Seiko Epson Corporation
    Inventor: Masakuni Shiozawa
  • Publication number: 20140218061
    Abstract: Methods and structures for testing a microelectronic packaging structure/device are described. Those methods may include placing a device in a floating carrier, wherein the floating carrier is coupled to a socket housing by pin dowels disposed in four corners of the socket housing, and wherein at least two actuating motors are disposed within the socket housing, and micro adjusting the device by utilizing a capacitive coupled or a fiber optic alignment system wherein a maximum measured capacitance or maximum measured intensity between alignment structures disposed in the socket housing and alignment package balls disposed within the device indicate optimal alignment of the device. Methods further include methods for active co-planarity detection through the use of a capacitive-coupled techniques.
    Type: Application
    Filed: March 10, 2014
    Publication date: August 7, 2014
    Inventors: Abram M. Detofsky, Todd P. Albertson, David Shia
  • Patent number: 8797055
    Abstract: A prober includes a probe card provided with a support board and a probe attached to the support board, a stage on which a measurement wafer is mounted, a camera provided over the probe card to observe an electrode pad of a first semiconductor chip formed on the measurement wafer, and a stage moving unit for moving the position of the stage relative to the probe card.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: August 5, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kazuhiro Tashiro
  • Publication number: 20140203830
    Abstract: A wafer test system includes an input device configured to transmit a test signal, a wafer including an optical port, an input port configured to receive the test signal, and an output port configured to output a result signal based on the test signal, a measuring device configured to measure the result signal, and an alignment device configured to align an optical fiber port of an optical probe with an alignment port based on the result signal and then align the optical fiber port with the optical port. The alignment port is the input port or the output port. The optical probe is configured to be the input device when the input port is the alignment port and the optical probe is configured to be the measuring device when the output port is the alignment port.
    Type: Application
    Filed: January 21, 2014
    Publication date: July 24, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: DONG JAE SHIN, Yoon Dong Park, Sang Hun Choi, Kyoung Ho Ha
  • Patent number: 8786300
    Abstract: A probe tip includes a plurality of light emitters and a control circuit that is coupled to the light emitters. The control circuit is configured to control a projection of a plurality of light patterns from the light emitters for performing a phase-shift analysis using a plurality of images of the light patterns that are projected onto a component being inspected. The control circuit controls the projection of the light patterns by receiving electrical energy from a drive circuit. At least one of the light emitters is identified for receiving a power input based at least in part on the electrical energy received from the drive circuit. The power input is transmitted to the identified light emitter, based at least in part on the electrical energy received from the drive circuit, to enable the activation of the identified light emitter.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: July 22, 2014
    Assignee: General Electric Company
    Inventor: Clark Alexander Bendall
  • Patent number: 8773153
    Abstract: A method of correcting an overlay includes setting a reference map having information relating to predetermined positions of a substrate. An overlay value is measured at each of the predetermined positions to obtain a plurality of overlay measurement values. The plurality of overlay measurement values is applied to a polar coordinate function to calculate a correlation coefficient of the polar coordinate function. The polar coordinate function uses coordinate values of the predetermined positions as parameters.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: July 8, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chan Hwang
  • Publication number: 20140111235
    Abstract: There is provided an electronic component handling apparatus which can be reduced in size or can improve the throughput when the number of contact arms is increased. A handler comprises: a plurality of contact arms which are arrayed along a first direction, each of the plurality of contact arms including a holding part which holds a DUT and including an adjustment unit which moves the holding part relative to a base part of each contact arm; an imaging unit capable of imaging the DUT and the holding part; an operation unit which operates the adjustment unit; and a moving unit which moves the imaging unit and the operation unit along an X direction. The adjustment unit adjusts the relative position of the holding part according to an operation of the operation unit.
    Type: Application
    Filed: October 21, 2013
    Publication date: April 24, 2014
    Applicant: ADVANTEST CORPORATION
    Inventor: Aritomo KIKUCHI
  • Patent number: 8655350
    Abstract: A pn junction type solar cell is formed in a predetermined region on a substrate made of glass. Light emitted from a light emitting unit reaches an n-type semiconductor layer after it passed through substrate. The solar cell generates electromotive force corresponding to a quantity of the emitted light. A control circuit, a mask ROM, a transmitting circuit and an antenna are formed on an upper side of the solar cell. A surface of a semiconductor storage device is entirely covered with an insulating film to block entry of outside air. The insulating film is typically formed of physicochemically stable glass or silicon dioxide.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: February 18, 2014
    Assignees: Sharp Kabushiki Kaisha, Kyoto University, Keio University
    Inventors: Shigeki Imai, Yukihiro Nakamura, Hiroyuki Ochi, Naohisa Ohta, Sadayasu Ono
  • Patent number: 8643393
    Abstract: An embodiment of an electrical connecting apparatus enables reliable identification of a mark and enables accurate and easy determination of a coordinate position of the mark. The electrical connecting apparatus comprises a supporting body having a lower surface, a plurality of contacts arranged on the lower surface of the supporting body, a mark that is provided on a lower side of the supporting body and whose light passing feature differs from that of an area adjacent to the mark, and a light source provided to the supporting body to irradiate light to the mark from an upper side of the mark.
    Type: Grant
    Filed: February 19, 2010
    Date of Patent: February 4, 2014
    Assignee: Kabushiki Kaisha Nihon Micronics
    Inventors: Ken Hasegawa, Hisao Narita, Yutaka Funamizu
  • Patent number: 8624579
    Abstract: A Fiber-optic current sensor for sensing electric current carried in an electric conductor (18). Its optical section comprises: a light source (1); a directional coupler (2) with two ports (2A, 2B) of two arms each; a radiation polarizer (3); a polarization modulator (4); a fiber line (17) coupled to a current-sensing fiber loop (11); a mirror (10); and a photodetector (22). The first port of the coupler (2) is coupled to the light source (1) and to the photodetector (22). Its second port is coupled via the radiation polarizer (3) to the polarization modulator (4). The polarization modulator comprises a magneto-sensitive element (5), around which a solenoid (6) is wound. The fiber loop (11) comprises a magneto-sensitive optical fiber with embedded linear birefringence. An electronic section comprises a signal generator (21) which drives the solenoid (6); and a signal processing unit which receives the optical signal from the photodetector (22).
    Type: Grant
    Filed: December 28, 2010
    Date of Patent: January 7, 2014
    Assignee: Closed Joint Stock Company “Profotech” (CJSC “Profotech”)
    Inventors: Yuri Chamorovskiy, Vladimir Gubin, Sergei Morshnev, Yan Prziyalkovskiy, Maxin Ryabko, Nikolay Starostin, Alexander Sazonov, Anton Boyev
  • Patent number: 8593157
    Abstract: In one aspect, the present invention provides an imager, preferably portable, that includes a source of electromagnetic radiation capable of generating radiation with one or more frequencies in a range of about 1 GHz to about 2000 GHz. An optical system that is optically coupled to the source focuses radiation received therefrom onto an object plane, and directs at least a portion of the focused radiation propagating back from the object plane onto an image plane. The imager further includes a scan mechanism coupled to the optical system for controlling thereof so as to move the focused radiation over the object plane. A detector optically coupled to the lens at the image plane detects at least a portion of the radiation propagating back from a plurality of scanned locations in the object plane, thereby generating a detection signal. A processor that is in communication with the detector generates an image of at least a portion of the object plane based on the detection signal.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: November 26, 2013
    Assignee: Walleye Technologies, Inc.
    Inventors: Christopher P. Adams, David S. Holbrook