Liquid State Patents (Class 324/754.04)
  • Patent number: 11906569
    Abstract: A semiconductor wafer evaluation apparatus brings a contact maker (mercury liquefied at room temperature), as a Schottky electrode, into contact with a semiconductor wafer, intermittently applies a voltage from a pulse power supply, and evaluates the state (kinds, density) of point defects by an evaluation means based on the status of the electrostatic capacity of the semiconductor wafer. In this manner, the state (kinds, density) of the point defects in the plane of a large-diameter semiconductor wafer is directly evaluated using a large table.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: February 20, 2024
    Assignee: SHOWA DENKO K.K.
    Inventors: Koichi Murata, Isaho Kamata, Hidekazu Tsuchida, Akira Miyasaka
  • Patent number: 11802908
    Abstract: An alignment mechanism is disclosed which includes a mount, a beam having a first end affixed to the mount and a second end. The beam is an order of magnitude more rigid along its longitudinal axis than along an axis orthogonal to its longitudinal axis. The second end of the beam is affixed to a first device having a surface configured to contact a second device. The beam applies a normal force component to the second device through the first device and allows movement at the second end in directions orthogonal to the normal force component.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: October 31, 2023
    Assignee: DELTA DESIGN, INC.
    Inventors: Jerry Ihor Tustaniwskyj, James Wittman Babcock
  • Patent number: 11805597
    Abstract: A high-throughput method of manufacturing a liquid metal circuit may include applying a liquid metal to an alloying metal pattern on an elastic substrate to form the liquid metal circuit. The elastic substrate may have a surface area greater than 1 square inch. The liquid metal circuit may include a plurality of liquid metal circuits on the elastic substrate. Methods of using the liquid metal circuit are also described.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: October 31, 2023
    Assignee: CARNEGIE MELLON UNIVERSITY
    Inventors: O Burak Ozdoganlar, Carmel Majidi, Kadri Bugra Ozutemiz, James Wissman
  • Patent number: 9431307
    Abstract: Provided is a semiconductor wafer evaluation method of performing an evaluation of electrical characteristics of a semiconductor wafer by bringing mercury into contact with a surface of the semiconductor wafer, the method including using a probe constituted of a fixed electrode having a tip end portion and a transparent covering portion that covers a portion other than the tip end portion of the fixed electrode, the fixed electrode being made of a metal having stronger wettability with respect to the mercury than the semiconductor wafer and the covering portion, and measuring the electrical characteristics by attaching the mercury to the tip end portion of the fixed electrode and then bringing the mercury into contact with the surface of the semiconductor wafer.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: August 30, 2016
    Assignee: SHOWA DENKO K.K.
    Inventor: Taichi Okano
  • Patent number: 8970238
    Abstract: A probe module for testing an electronic device comprises at least two contacts, each contact including a first end portion extending in a first direction along a first line, a second end portion extending linearly in a second direction opposite from the first direction and along a second line, and a third curved portion extending between the first end portion and the second end portion. The first line is spaced apart from and in parallel with the second line, and the at least two contacts are spaced apart from each other in a direction perpendicular to the first line and the second line. Methods for making such a probe module are also taught.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: March 3, 2015
    Assignee: Electro Scientific Industries, Inc.
    Inventor: Douglas J. Garcia
  • Patent number: 8970242
    Abstract: Provided is a method for manufacturing a probe card which inspects electrical characteristics of a plurality of semiconductor devices in batch. The method includes: a step of forming a plurality of probes, which are to be brought into contact with external terminals of the semiconductor devices, on one side of a board which forms the base body of the probe card; a step of forming on the board, by photolithography and etching, a plurality of through-holes which reach the probes from the other side of the board; a step of forming, in the through-holes, through electrodes to be conductively connected with the probes, respectively; and a step of forming wiring, which is conductively connected with the through electrodes, on the other side of the board.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: March 3, 2015
    Assignee: Rohm Co, Ltd.
    Inventors: Goro Nakatani, Masahiro Sakuragi, Koichi Niino
  • Publication number: 20140354318
    Abstract: Embodiments of the present disclosure are directed to interconnects that include liquid metal, and associated techniques and configurations. The individual interconnects may electrically couple a contact of a printed circuit board (PCB) to a contact of a device under test (DUT). The interconnect may be disposed in or on the PCB. In various embodiments, the interconnect may include a carrier that defines a well (e.g., an opening in the carrier), and the liquid metal may be disposed in the well. In some embodiments, the contact of the DUT, or a contact of an intermediary device, may extend into the well and directly contact the liquid metal. In other embodiments, a flex circuit may be disposed over the well to seal the well. The flex circuit may include a conductive pad to electrically couple the liquid metal to the contact of the DUT. Other embodiments may be described and claimed.
    Type: Application
    Filed: May 28, 2013
    Publication date: December 4, 2014
    Inventors: Youngseok Oh, Joe F. Walczyk, Jin Yang, Pooya Tadayon, Ting Zhong
  • Publication number: 20140253161
    Abstract: Methods and apparatus for measuring minority carrier lifetimes using liquid probes are provided. In one embodiment, a method of measuring the minority carrier lifetime of a semiconductor material comprises: providing a semiconductor material having a surface; forming a rectifying junction at a first location on the surface by temporarily contacting the surface with a conductive liquid probe; electrically coupling a second junction to the semiconductor material at a second location, wherein the first location and the second location are physically separated; applying a forward bias to the rectifying junction causing minority carrier injection in the semiconductor material; measuring a total capacitance as a function of frequency between the rectifying junction and the second junction; determining an inflection frequency of the total capacitance; and determining a minority lifetime of the semiconductor material from the inflection frequency.
    Type: Application
    Filed: March 5, 2014
    Publication date: September 11, 2014
    Applicant: Alliance for Sustainable Energy, LLC
    Inventor: Jian Li
  • Patent number: 8653845
    Abstract: A test handler is provided, which comprises a test tray, at least one opening unit, and a position changing apparatus. The test tray aligns a plurality of inserts on its side. Each insert loads at least one semiconductor device thereon. The opening unit opens inserts at one part of the one side of the test tray. The position changing apparatus moves at least one opening unit in such a way that the at least one opening units can be located at another part of the one side of the test tray, such that the at least one opening units can open inserts at said another part of the one side of the test tray. The present invention can reduce the number of replaced parts according to change in the semiconductor device size, production cost, and part replacement time.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: February 18, 2014
    Assignee: TechWing Co., Ltd.
    Inventors: Jae-Gyun Shim, Yun-Sung Na, In-Gu Jeon, Tae-Hung Ku, Dong-Han Kim
  • Patent number: 8476918
    Abstract: The present disclosure provides a semiconductor test system. The semiconductor test system includes a wafer stage to hold a wafer having a plurality of light emitting devices (LEDs); a probe test card operable to test each test field of the wafer; and a light detector integrated with the probe test card to collect light from a LED of the wafer.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: July 2, 2013
    Assignee: TSMC Solid State Lighting Ltd.
    Inventor: Hsin-Chieh Huang
  • Patent number: 8451014
    Abstract: A method to test and package dies so as to increase overall yield is provided. The method includes performing a wafer test on a first die and mounting the first die on a package substrate to form a partial package, if the wafer test of the first die is successful. The method further includes performing a system test on the partial package including the first die and stacking a second die on the first die if the system test on the partial package and the first die is successful.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: May 28, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bryan Black, Joseph Siegel
  • Patent number: 8384405
    Abstract: A method of the invention for performing burn-in test includes assembling, on a fixture stand, a plurality of light source elements and a plurality of light detectors for monitoring a light output from a corresponding one of the plurality of light source elements; and electrifying the plurality of light source elements in a state where at least the plurality of light source elements and the plurality of light detectors are immersed in an insulation liquid. Thereby, it is realized to hold a stable temperature in a short period of time, to maintain a temperature that does not deviate from normal load conditions, and to perform a sorting test between defect parts and good part for light source unit chips without causing damage to the elements.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: February 26, 2013
    Assignee: TDK Corporation
    Inventors: Koji Shimazawa, Ryo Hosoi, Yasuhiro Ito, Masaaki Kaneko, Takashi Honda, Ryuji Fujii, Koji Hosaka
  • Publication number: 20130021051
    Abstract: The invention relates to an apparatus for electrically contacting a solar cell or a solar cell module, particularly for testing its performance, the solar cell or the solar cell module having an electrical contact, the apparatus comprising: a receiving volume for receiving a solar cell or a solar cell module, at least one fluid space for receiving an electrically conducting fluid, the fluid space being arranged with respect to the receiving volume such that a fluid in the fluid space at least partially covers an electrical contact of a solar cell or a solar cell module when being received by the receiving volume, and electrical transmitting means for connecting the fluid in the fluid space with a measurement device (I, U) in an electrically conducting manner.
    Type: Application
    Filed: July 18, 2012
    Publication date: January 24, 2013
    Inventor: André RICHTER
  • Patent number: 7982478
    Abstract: In some embodiments, a liquid TIM dispense and removal method and assembly is presented. In this regard, a method is introduced including loading an absorbent material of a thermal control unit with a liquid thermal interface material (TIM), pressing the absorbent material against an integrated circuit device causing the liquid TIM to be released, testing the integrated circuit device, and removing the absorbent material from against the integrated circuit device causing the liquid TIM to be reabsorbed. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: July 19, 2011
    Assignee: Intel Corporation
    Inventors: Nader Abazarnia, Ashish X Gupta, Suzana Prstic