Abstract: Methods and systems are described which use load balancing to efficiently perform queries. Embodiments identify available nodes and divide an index into shards. Embodiments distribute the index across the nodes where each node has at least two distinct shards. Based on a target upper bound number of requests per node, and based on which shards exist at each node, embodiments identify a query routing policy which also includes accounting for node failure. Embodiments route a query based on the identified query routing policy.

Abstract: The present disclosure is directed to an inspection tool having a probe head with a probe card with a plurality of probes for performing testing, each of the probes being configured with a first end attached to the probe card and a second end for engaging microbumps coupled to a semiconductor die, the plurality of probes including a first set of probes having a first cross-sectional dimension, the first set of probes being arranged in a first set of locations on the probe card, and a second set of probes having a second cross-sectional dimension, the second set of probes being arranged in a second set of locations on the probe card, and a stage for holding the semiconductor die.

Abstract: One or more embodiments provide a heterogeneous test equipment interfacing apparatus. The heterogeneous test equipment interfacing apparatus includes a plurality of data intermediate apparatuses connected to a plurality of environment test chambers; and at least one computer apparatus interoperating with the plurality of data intermediate apparatuses. Each of the plurality of data intermediate apparatuses is configured to convert an electric signal received from at least one environment test chamber interoperating with a corresponding data intermediate apparatus from among the plurality of environment test chambers into a data signal based on an SNMP protocol, output the data signal and, output a control signal for controlling the at least one environment test chamber interoperating with a corresponding data intermediate apparatus according to an operation control instruction received from the at least one computer apparatus.

Abstract: A method for aligning a device includes: loading devices sequentially on an upper surface of a base plate having vacuum holes; suctioning the loaded device with vacuum pressure that allows minute movement of the loaded device, as the vacuum pressure is applied while the device is loaded on the base plate; moving an alignment vision assembly positioned above the base plate to the upper portion of the device to be aligned and then lowering the alignment vision assembly; checking a position of the device with a vision means through a through hole and an opening in a state, in which an alignment block surrounds the device, so as to inform a controller of the coordinates of the device; and aligning the device by finely moving the base plate in X-Y-? directions according to the coordinates so that the device is guided to two surfaces of the opening.

Abstract: An optical path correction subassembly, an optical detection assembly, and an optical detection system are provided. The optical path correction subassembly can be optionally configured to be applied to a light detector. The optical path correction subassembly includes a holder structure and an optical path correction structure carried by the holder structure, and the optical path correction structure has a light beam guiding surface arranged as a reverse inclination inclined relative to a vertical line. The light beam guiding surface of the optical path correction structure can be configured to effectively or accurately guide a predetermined light beam to a light receiving surface of the light detector so as to facilitate collection of the predetermined light beam. The light beam guiding surface of the optical path correction structure can be arranged at an acute angle relative to the light receiving surface of the light detector.

Abstract: A probe unit includes: a first contact probe configured to come in contact with a signal electrode; a second contact probe configured to come in contact with a ground electrode; a probe holder including a first holder hole through which the first contact probe passes, and a second holder hole through which the second contact probe passes; and a conductive floating member including a first through hole to which the first contact probe is inserted and the signal electrode is inserted, and a second through hole to which the second contact probe is inserted and the ground electrode is inserted. The probe holder is configured such that at least an inner circumferential surface of the first holder hole has an insulating property, and the probe unit has a coaxial structure in which central axes of the first contact probe and the first through hole are aligned with each other.

Abstract: A probe station includes a frame, a platform, a testing equipment, a probe holder and at least one probe. The frame defines an accommodation space. The platform is connected with the frame. The platform has an opening. The opening is communicated with the accommodation space. The testing equipment is at least partially disposed in the accommodation space and is at least partially exposed through the opening. The probe holder is disposed on the platform. The probe is held by the probe holder. The probe holder is configured to control the probe to contact with a device under test disposed on the testing equipment through the opening.

Abstract: Cryogenic testing systems for testing electronic components such as wafers under cryogenic conditions are provided. The novel designs enable fast throughput by use of a cryogenically maintained test surface to which wafers may be rapidly introduced, cooled, and manipulated to contact testing elements while maintaining high quality cryogenic conditions. Thermal shielding is achieved by floating shields and/or flexible bellows that provide effective thermal shielding of the test environment while enabling manipulation of wafers with a wide range of motion. Also provided are novel door assemblies, chuck configurations, and vacuum plate bases that enable effective maintenance of cryogenic conditions and high throughput.

Abstract: The present disclosure provides a semiconductor wafer. The semiconductor wafer includes: a scribe line between a first row of dies and a second row of dies; and a benchmark circuit disposed adjacent to the scribe line and electrically coupled to a first conductive contact and a second conductive contact. The benchmark circuit includes a first device-under-test (DUT); a second DUT; a first switching circuit configured to selectively couple the first DUT and the second DUT to the first conductive contact; and a second switching circuit configured to selectively couple the first DUT and the second DUT to the second conductive contact.

Abstract: A contact assembly for a Kelvin testing system for testing integrated circuit devices is disclosed. The contact assembly includes at least one grouping of blades including a first force blade, a second force blade, a first sense blade, and a second sense blade; an electrical insulation layer disposed between the first force blade and the first sense blade and between the second force blade and the second sense blade; and an elongated elastomer. The elastomer is configured to be retained by the first force blade, the second force blade, the first sense blade, and the second sense blade. Each of the first force blade, the second force blade, the first sense blade, and the second sense blade includes a recess having an opening and sized to receive and retain at least a portion of the elastomer.

Abstract: Implementations of a substrate carrier may include: a top ring configured to enclose an edge of a first side of a substrate; and a bottom support configured to enclose an entire second side and an edge of the second side of the substrate.

Abstract: Provided are an inspection jig and an inspection apparatus in which a configuration for bending a plurality of contacts in the same direction can be simplified. The inspection jig includes a plurality of contacts each of which has a rod shape, a first support portion that supports the first end portion side of the plurality of contacts, and a second support portion that supports the second end portion side of the plurality of contacts. The first support portion includes a facing support plate that is disposed to face the second support portion in a manner separated from the second support portion and has a plurality of through holes through which the plurality of contacts are inserted, and a cross section of each of the through holes has an elliptical shape whose major axis extends in a predetermined specific direction along a plane direction of the facing support plate.

Abstract: An inspection apparatus includes: a probe card having a probe to be in contact with an object to be inspected; an upper module having a mounting portion on which the object to be inspected is mounted; a movement mechanism that is configured to support the upper module to be liftable and lowerable and that is able to move the upper module in a horizontal direction; and a lifting and lowering mechanism that is provided under the movement mechanism and that is able to push up the upper module toward the probe card, wherein an axis passing through a point of action of a pushing force when the lifting and lowering mechanism pushes up the upper module and an axis passing through a point of action of a load received by the probe card are arranged at positions to be common.

Abstract: A wafer carrier that exhibits a thin, low-profile includes a bottom support plate upon which a thinned semiconductor wafer may be positioned, with a holding ring disposed to surround the periphery of the wafer and engage with the bottom support plate to hold the wafer in a fixed position between the two components. The bottom support plate is formed to include a plurality of apertures for pulling a vacuum through the carrier, as well as features that engage with the holding ring and alignment fiducials for properly registering the orientation of the wafer's surface with respect to the wafer carrier and other testing equipment using the wafer carrier.

Abstract: Some embodiments of the invention are directed to electrochemical fabrication methods for forming structures or devices (e.g. microprobes for use in die level testing of semiconductor devices) from a core material and a shell or coating material that partially coats the surface of the structure. Other embodiments are directed to electrochemical fabrication methods for producing structures or devices (e.g. microprobes) from a core material and a shell or coating material that completely coats the surface of each layer from which the probe is formed including interlayer regions. Additional embodiments of the invention are directed to electrochemical fabrication methods for forming structures or devices (e.g. microprobes) from a core material and a shell or coating material wherein the coating material is located around each layer of the structure without locating the coating material in inter-layer regions.

Abstract: An integrated circuit includes a semiconductor die having conductive pads and an electronic component with a first terminal coupled to a third conductive pad and a second terminal coupled to a fourth conductive pad. A resistor has a first terminal coupled to the fourth conductive pad and a second terminal coupled to the fifth conductive pad, and a first transistor has a first terminal coupled to the first conductive pad, a second terminal coupled to the fifth conductive pad, and a control terminal. A second transistor has a first terminal coupled to the first transistor, a second terminal coupled to the third conductive pad, and a control terminal. A pulse generator has an input coupled to the second conductive pad and an output coupled to the control terminal of the second transistor.

Abstract: A process tests an operability of a circuit breaker device (18, 20, 34) to establish/sever a connection of two circuit areas (36, 38, 40, 42). The circuit breaker device includes a MOSFET (44) with a source terminal (46) connected with a circuit area, a drain terminal (48) connected with a circuit area, and a gate terminal (50) with a gate voltage applied by an associated gate driver device (52) to switch into a connection switching state connecting the two circuit areas during a connection phase. The gate voltage is monitored during the connection phase, a base voltage being applied to the source terminal or/and to the drain terminal during the connection phase is monitored. If a difference between the gate voltage and the base voltage falls below a predefined reference difference during the connection phase, it is determined that a circuit defect is present in the MOSFET.

Abstract: A probing apparatus includes a chuck supporting a DUT, and a platform with an opening above the chuck. The probing apparatus further includes first and second rails positioned at first and second sides of the platform, respectively. The probing apparatus further includes a probing device, the probing device includes a probing module slidably along the first and second rails, and a first motor system configured to automatically align a probe card with the DUT. The probing module includes a third rail with two ends slidably attached to the first and second rails, respectively, a probing stage slidably attached to the third rail, and the probe card attached to the probing stage. The first motor system includes a first motor configured to control movement of the probing stage along the third rail, and a second motor configured to control movement of the probing module along the first and second rails.

Abstract: Implementations of methods of making a semiconductor device may include: providing a partial semiconductor wafer. The method may also include providing a wafer holder including a tape portion with one or more openings through the tape portion. The method may include mounting the partial semiconductor wafer over the one or more openings in the tape portion of the wafer holder and providing an electrical connection to the partial semiconductor wafer through the one or more openings in the tape portion during probe test.

Abstract: An electrical connection assembly includes a main body and a spring. One end of the main body is configured to be in contact with a device under test. The spring is sleeved around the main body. Two ends of the spring are respectively defined as a first end and a second end. The first end is abutted against a limiting protrusion, and a concealed section of the main body is correspondingly arranged inside of the spring. The spring has a first tightly-coiled section, an elastic section, and a second tightly-coiled section in sequence from the first end to the second end. A pitch of the spring within the elastic section is greater than a pitch of the spring within the first tightly-coiled section, and the pitch of the spring within the elastic section is greater than a pitch of the spring within the second tightly-coiled section.

Abstract: An electrical connection device includes: a plurality of probes (10) in which distal end portions contact an inspection object (2) during measurement; and a space transformer (30) including a plurality of connection wirings (33), in each of which a first terminal electrically connected to any of proximal end portions of the plurality of probes (10) is arranged on a first main surface (301), and a second terminal is exposed to a second main surface (302), and having a short-circuit wiring pattern formed on the first main surface, the short-circuit wiring pattern electrically connecting, to the same connection wiring (33), proximal end portions of a plurality of same-potential probes (10) set at a same potential during measurement among the plurality of probes (10).

Abstract: There is provided an information processing apparatus including an image acquisition part that acquires an image captured by an imaging part, and a display controller that causes a virtual object to be displayed in accordance with a recognition result of a real object shown in the image. The display controller controls the virtual object on a basis of a size of the real object in a real space.

Abstract: A method for upgrading an automatic testing system includes electrically connecting at least one pogo pin attaching device to an expansion instrument and a pogo pin of a pogo pin interface of the automatic testing system wherein the pogo pin attaching device comprises at least one metal attaching member and at least one cable, each of said at least one cable having two opposite ends, a first end electrically connected to the metal attaching member and a second end electrically connected to the expansion instrument, and the metal attaching member attaches to the pogo pin. In response to operating the automatic testing system, electrically connecting the pogo pin to a subject so that a measurement path is established between the subject and the expansion instrument through the pogo pin attaching device, wherein the measurement path is configured to connect signals for upgrading the automatic testing system.

Abstract: Probe systems for optically probing a device under test (DUT) and methods of operating the probe systems. The probe systems include a probing assembly that includes an optical probe that defines a probe tip and a distance sensor. The probe systems also include a support surface configured to support a substrate, which defines a substrate surface and includes an optical device positioned below the substrate surface. The probe systems further include a positioning assembly configured to selectively regulate a relative orientation between the probing assembly and the DUT. The probe systems also include a controller programmed to control the operation of the probe systems. The methods include methods of operating the probe systems.

Abstract: A metal frame that is used in a dummy wafer in which chip-like semiconductor elements and a rewiring layer are integrated. A plurality of openings in which the chip-like semiconductor elements are disposed are formed in the metal plate, and a lattice structure is formed with the frames that are the portions between adjacent openings of the plurality of openings. Of the frames forming the lattice structure, the frames located in dicing areas of the dummy wafer are arranged in a discontinuous manner.

Abstract: A dynamic probe for probing a dynamic data signal comprising a switching unit configured to provide at least two different input impedances, wherein the switching unit is configured to select a first input impedance in a first mode and a second input impedance in a second mode, the switching unit being configured to be operated dynamically based on an event in the data signal processed. Further, a dynamic measurement system and a method for probing a dynamic data signal are described.

Abstract: Techniques for implementing a self-test procedure of an integrated circuit are provided, where the self-test procedure comprises testing for an electrical connection between first and second input-output pads of the integrated circuit. A control device is capable of adapting a functional configuration of usage of the first and second input-output pads in dependence on presence of the electrical connection. A corresponding integrated circuit, printed circuit and method are also provided. These techniques allow the integrated circuit to be used in a variety of contexts, without requiring physical customisation of the integrated circuit to adapt it to its usage context, in particular where connections from the context to the pads of the integrated circuit may be made to individual pads in some contexts or may span more than one pad in other contexts.

Abstract: The present disclosure includes apparatuses and methods related to test devices, for example testing devices by measuring signals emitted by a device. One example apparatus can include a first portion including a number of sidewalls positioned to at least partially surround a device under test; and a second portion electrically coupled to the first portion, wherein the second portion is configured to move in the x-direction, the y-direction, and z-direction.

Abstract: A per-chip equivalent oxide thickness (EOT) circuit sensor resides in an integrated circuit. The per-chip EOT circuit sensor determines electrical characteristics of the integrated circuit. The measured electrical characteristics include leakage current. The determined electrical characteristics are used to determine physical attributes of the integrated circuit. The physical attributes, including EOT, are used in a reliability model to predict per-chip failure rate.

Abstract: An interposer is provided which includes: a substrate having a first surface with a plurality of first conductive pads and a second surface opposite to the first surface, the second surface having a plurality of second conductive pads; a plurality of conductive through holes penetrating the first and second surfaces of the substrate and electrically connecting the first and second conductive pads; and a first removable electrical connection structure formed on the first surface and electrically connecting a portion of the first conductive pads so as to facilitate electrical testing of the interposer.

Abstract: A connector pin device includes a test socket body made of a flexible insulating material and including a pin mounting part in which mounting holes have been formed and a support part supporting the pin mounting part, sliding contact pins respectively formed in the mounting holes and each including a first contact pin having a first end externally exposed and a second end located within the mounting hole and a second contact pin having a first end externally located on the side opposite the first end of the first contact pin and a second end located within the mounting hole, wherein the first and second ends of the first and the second contact pins are provided to slide and come into contact with each other, and an cavity portion formed in a portion where the second ends of the sliding contact pins in the mounting hole are located.

Abstract: A testing probe apparatus for testing die. The testing probe may include a probe interface and a carrier for supporting at least one die comprising 3DI structures. The probe interface may be positionable on a first side of the at least one die and include a voltage source and at least one first inductor operably coupled to the voltage source. A voltage sensor and at least one second inductor coupled to the voltage sensor may be disposed on a second opposing side of the at least one die. The voltage source of the probe interface may be configured to inductively cause a voltage within the 3DI structures of the at least one die via the at least one first inductor. The voltage sensor may be configured to sense a voltage within the at least one 3DI structure via the at least one second inductor. Related systems and methods are also disclosed.

Abstract: A method for manufacturing electronic apparatus includes: a step (A) of preparing a structure provided with an adhesive film and at least one electronic component affixed to an adhesive surface of the adhesive film; a step (B) of disposing the structure in an electronic component testing apparatus such that the electronic component is positioned over an electronic component installation region of a sample stand with the adhesive film interposed between the electronic component and the electronic component installation region, the electronic component testing apparatus being provided with a probe card at a position facing the sample stand and includes a probe terminal; a step (C) of evaluating the properties of the electronic component while being affixed to the adhesive film with the probe terminal being in contact with a terminal of the electronic component; and a subsequent step (D) of picking up the electronic component from the adhesive film.

Abstract: Probe location candidates for parasitic extraction are identified from geometric elements on a probe layer. The probe layer is a physical layer of a layout design for a circuit design predetermined for placing one or more new probes. The probe location candidates are geometric elements on the probe layer within a boundary of an area having a predetermined size and covering an original probe location or having a distance from the original probe location less than a predetermined value. Moreover, the probe location candidates are conductively connected to the original probe location. One or more new probe locations on the probe location candidates are selected based on predetermined criteria. From the layout design, a parasitic resistance value for parasitic resistance between a geometric element representing a circuit pad or another device pin and the new one or more probe locations is extracted.

Abstract: Disclosed is a differential test probe tip. The probe tip comprises a socket of electrically conductive material at a proximate end of the probe tip. The socket includes a concavity to receive a signal pin. The probe tip also comprises a reference body of conductive material surrounding the socket. The probe tip further comprises a insulating spacer element of non-conductive material surrounding the reference body at the proximate end of the probe tip. The insulating spacer element includes a signal port to receive the signal pin into the socket. The insulating spacer element further includes a reference port to receive a reference pin and maintain the reference pin in electrical communication with a proximate end of the reference body.

Abstract: The present disclosure includes apparatuses and methods related to test devices, for example testing devices by measuring signals emitted by a device. One example apparatus can include a first portion including a number of sidewalls positioned to at least partially surround a device under test; and a second portion electrically coupled to the first portion, wherein the second portion is configured to move in the x-direction, the y-direction, and z-direction.

Abstract: A testing apparatus includes a holster including a jack defining a conductive periphery configured to connect with a reference lead of the voltage probe to form a common ground. The apparatus includes a shunt defining first and second regions of different potential having predetermined difference. The second region is configured to connect with a reference lead of the shunt probe. The apparatus includes a bridge configured to connect the shunt probe lead with the common ground.

Abstract: The present disclosure provides a substrate, a display panel and a display device. The substrate includes a body provided with an opening, and guiding protrusions arranged on the body at a position adjacent to the opening.

Abstract: A method for estimating resistances of a source contact and a drain contact of a MOS transistor includes the following steps. A MOS transistor is provided. The MOS transistor includes a substrate, a gate, a source region and a drain region, a source contact electrically connected to the source region, and a drain contact electrically connected to the drain region. A resistance difference between a source contact resistance and a drain contact resistance is obtained. A resistance sum of the source contact resistance and the drain contact resistance is obtained. The source contact resistance and the drain contact resistance are calculated based on the resistance sum of the source contact resistance and the drain contact resistance, and on the resistance difference between the source contact resistance and the drain contact resistance.

Abstract: A tester apparatus is provided. Slot assemblies are removably mounted to a frame. Each slot assembly allows for individual heating and temperature control of a respective cartridge that is inserted into the slot assembly. A closed loop air path is defined by the frame and a heater and cooler are located in the closed loop air path to cool or heat the cartridge with air. Individual cartridges can be inserted or be removed while other cartridges are in various stages of being tested or in various stages of temperature ramps.

Abstract: A semiconductor package assembly includes a redistribution layer (RDL) structure, which RDL structure includes a conductive trace. A redistribution layer (RDL) contact pad is electrically coupled to the conductive trace, and the RDL contact pad is composed of a symmetrical portion and an extended wing portion connected to the symmetrical portion. The RDL structure includes a first region for a semiconductor die to be disposed thereon and a second region surrounding the first region, and the extended wing portion of the RDL contact pad is offset from a center of the first region.

Abstract: Provided are embodiments including methods, systems, and computer-program products for mitigating power supply noise using one or more current supplies. In some embodiments, power is provided to an integrated circuit, wherein a first circuit is coupled to the integrated circuit over a first path. A variation of the current level of the integrated circuit may be determined. Additional power from a second circuit is provided to the integrated circuit may be provided based at least in part on the determined variation, wherein the second circuit is coupled to the integrated circuit over a second path.

Abstract: Systems and methods can provide a fast and accurate way to measure conductivity and Hall effect, such that transient conductivities, transient carrier densities or transient mobilities can be measured on millisecond time scales, for example. The systems and methods can also reduce the minimum magnetic field needed to extract carrier density or mobility of a given sample, and reduce the minimum mobility that can be measured with a given magnetic field.

Abstract: A probe card for integrated circuit testing includes a printed circuit support and a probe head having a first surface mounted to a surface of the printed circuit support. A flexible substrate is positioned adjacent to a second surface of the probe head and includes at least one flexible extension which extends beyond an edge of the probe head and includes a bend to make contact with the surface of the printed circuit support. The flexible substrate further includes a test antenna configured to support a wireless communications channel with an integrated circuit under test. The integrated circuit under test includes at least one conductive structure that extends in the peripheral portion on different planes of metallizations to form an integrated antenna that is coupled for communication and/or power transfer to the test antenna.

Abstract: A circuit adapter board has a film circuit board, a spring probe assembly, a space, and a filler. The film circuit board has a film body and multiple conductors. The film body has multiple first contacts and multiple second contacts. A density of distribution of the second contacts is higher than a density of distribution of the first contacts. The conductors are respectively connected to the first contacts. The spring probe assembly is disposed out of the first outer layer and has a plate and multiple spring probes. The spring probes are respectively disposed in the plate. Each spring probe has a base, a connecting portion, and a contacting portion being retractable. The space is formed between the film body of the film circuit board and the plate. The filler is disposed between the film body and the plate.

Abstract: In the modern world, electricity has become ubiquitous. Electrical connectors that connect and disconnect the electricity from the end use device have become important. If the connector has established a good quality contact across its mating conductors, there is no cause for concern. Also, if the connector has not established any contact with associated contacts being far away, then also there is no cause for a safety concern. However, when a connector has established marginal contact between the source and drain side contacts, and if the load and the source are switched on, the possibility of an arc across the thin layer of oxide separating the two contacts is high. This invention teaches a method to measure the quality of electrical connection established across an electrical connector. The method described here can be used to ascertain the quality of the connection before turning on the current across the connection.

Abstract: A diagnostic device comprises a comparison section to compare an input voltage with a threshold voltage, wherein the input voltage is a power supply voltage for a component on a circuit board; and an indicator to provide an indication of the result of the comparison by the comparison section, the indication to render the circuit board identifiable to direct inspection, wherein the supply of power to the component is independent of the result of the comparison.

Abstract: A testing device includes a circuit board, a carrier, a probe pin, a main body, a shaft, a pressing portion and a resilient spiral spring. The carrier is used to hold a device under test (DUT). The probe pin is electrically connected to the circuit board and the DUT. The shaft is movably connected to the main body with a screwing rotation method. The pressing portion is connected to one end surface of the shaft. The resilient spiral spring is retractably coiled on the shaft, and one end of the resilient spiral spring being far away from the shaft extends in a transverse direction intersecting an axial direction of the shaft.

Abstract: In one embodiment a circuit arrangement for disturber detection comprises an input for receiving an input signal, the input being adapted to be coupled to an antenna, a receiver circuit coupled to the input which is configured to provide a demodulated signal as a function of the input signal, and a disturber rejection circuit which is coupled to an output of the receiver circuit. Therein the disturber rejection circuit is configured to provide a first signal indicative of a low energy disturber and/or a second signal indicative of a square envelope disturber, the first and second signals being provided as a function of the demodulated signal at respective outputs of the disturber rejection circuit. Furthermore, a lightning detector and a method for disturber detection are described.

Abstract: An integrated circuit optical die test interface and associated testing method are described for using scribe area optical mirror structures (106) to perform wafer die tests on MEMS optical beam waveguide (112) and optical circuit elements (113) by perpendicularly deflecting optical test signals (122) from the scribe area optical mirror structures (106) into and out of the plane of the integrated circuit die under test (104) and/or production test die (157).