Contact Probe Patents (Class 324/754.03)
  • Patent number: 10809293
    Abstract: A method for manufacturing electronic apparatus includes: a step (A) of preparing a structure provided with an adhesive film and at least one electronic component affixed to an adhesive surface of the adhesive film; a step (B) of disposing the structure in an electronic component testing apparatus such that the electronic component is positioned over an electronic component installation region of a sample stand with the adhesive film interposed between the electronic component and the electronic component installation region, the electronic component testing apparatus being provided with a probe card at a position facing the sample stand and includes a probe terminal; a step (C) of evaluating the properties of the electronic component while being affixed to the adhesive film with the probe terminal being in contact with a terminal of the electronic component; and a subsequent step (D) of picking up the electronic component from the adhesive film.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: October 20, 2020
    Assignee: MITSUI CHEMICALS TOCHELLO, INC.
    Inventor: Eiji Hayashishita
  • Patent number: 10769340
    Abstract: Probe location candidates for parasitic extraction are identified from geometric elements on a probe layer. The probe layer is a physical layer of a layout design for a circuit design predetermined for placing one or more new probes. The probe location candidates are geometric elements on the probe layer within a boundary of an area having a predetermined size and covering an original probe location or having a distance from the original probe location less than a predetermined value. Moreover, the probe location candidates are conductively connected to the original probe location. One or more new probe locations on the probe location candidates are selected based on predetermined criteria. From the layout design, a parasitic resistance value for parasitic resistance between a geometric element representing a circuit pad or another device pin and the new one or more probe locations is extracted.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: September 8, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Sridhar Srinivasan, Yi-Ting Lee, Patrick D. Gibson, Padmaja Susarla, Alex Thompson
  • Patent number: 10753961
    Abstract: Disclosed is a differential test probe tip. The probe tip comprises a socket of electrically conductive material at a proximate end of the probe tip. The socket includes a concavity to receive a signal pin. The probe tip also comprises a reference body of conductive material surrounding the socket. The probe tip further comprises a insulating spacer element of non-conductive material surrounding the reference body at the proximate end of the probe tip. The insulating spacer element includes a signal port to receive the signal pin into the socket. The insulating spacer element further includes a reference port to receive a reference pin and maintain the reference pin in electrical communication with a proximate end of the reference body.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: August 25, 2020
    Assignee: Tektronix, Inc.
    Inventors: Michael J. Mende, David T. Engquist, Richard A. Booman
  • Patent number: 10718805
    Abstract: The present disclosure includes apparatuses and methods related to test devices, for example testing devices by measuring signals emitted by a device. One example apparatus can include a first portion including a number of sidewalls positioned to at least partially surround a device under test; and a second portion electrically coupled to the first portion, wherein the second portion is configured to move in the x-direction, the y-direction, and z-direction.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: July 21, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Paul E. Gregory, Randon K. Richards
  • Patent number: 10705118
    Abstract: A testing apparatus includes a holster including a jack defining a conductive periphery configured to connect with a reference lead of the voltage probe to form a common ground. The apparatus includes a shunt defining first and second regions of different potential having predetermined difference. The second region is configured to connect with a reference lead of the shunt probe. The apparatus includes a bridge configured to connect the shunt probe lead with the common ground.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: July 7, 2020
    Assignee: Ford Global Technologies, LLC
    Inventors: Xi Lu, Krishna Prasad Bhat, Chingchi Chen, Zhuxian Xu, Guangyin Lei
  • Patent number: 10700305
    Abstract: The present disclosure provides a substrate, a display panel and a display device. The substrate includes a body provided with an opening, and guiding protrusions arranged on the body at a position adjacent to the opening.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: June 30, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Tao Wang, Ziyu Zhang, Song Zhang
  • Patent number: 10627442
    Abstract: A method for estimating resistances of a source contact and a drain contact of a MOS transistor includes the following steps. A MOS transistor is provided. The MOS transistor includes a substrate, a gate, a source region and a drain region, a source contact electrically connected to the source region, and a drain contact electrically connected to the drain region. A resistance difference between a source contact resistance and a drain contact resistance is obtained. A resistance sum of the source contact resistance and the drain contact resistance is obtained. The source contact resistance and the drain contact resistance are calculated based on the resistance sum of the source contact resistance and the drain contact resistance, and on the resistance difference between the source contact resistance and the drain contact resistance.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: April 21, 2020
    Assignee: Nanya Technology Corporation
    Inventors: Shih-Ting Lin, Kung-Ming Fan, Hung-Hsiang Xsiao
  • Patent number: 10468341
    Abstract: A semiconductor package assembly includes a redistribution layer (RDL) structure, which RDL structure includes a conductive trace. A redistribution layer (RDL) contact pad is electrically coupled to the conductive trace, and the RDL contact pad is composed of a symmetrical portion and an extended wing portion connected to the symmetrical portion. The RDL structure includes a first region for a semiconductor die to be disposed thereon and a second region surrounding the first region, and the extended wing portion of the RDL contact pad is offset from a center of the first region.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: November 5, 2019
    Assignee: MEDIATEK INC.
    Inventors: Nai-Wei Liu, Tzu-Hung Lin, I-Hsuan Peng, Che-Hung Kuo, Che-Ya Chou, Wei-Che Huang
  • Patent number: 10466292
    Abstract: A tester apparatus is provided. Slot assemblies are removably mounted to a frame. Each slot assembly allows for individual heating and temperature control of a respective cartridge that is inserted into the slot assembly. A closed loop air path is defined by the frame and a heater and cooler are located in the closed loop air path to cool or heat the cartridge with air. Individual cartridges can be inserted or be removed while other cartridges are in various stages of being tested or in various stages of temperature ramps.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: November 5, 2019
    Assignee: Aehr Test Systems
    Inventors: Jovan Jovanovic, Kenneth W. Deboe, Steven C. Steps
  • Patent number: 10461715
    Abstract: Provided are embodiments including methods, systems, and computer-program products for mitigating power supply noise using one or more current supplies. In some embodiments, power is provided to an integrated circuit, wherein a first circuit is coupled to the integrated circuit over a first path. A variation of the current level of the integrated circuit may be determined. Additional power from a second circuit is provided to the integrated circuit may be provided based at least in part on the determined variation, wherein the second circuit is coupled to the integrated circuit over a second path.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: October 29, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Martin Bernhard Schmidt, Thomas Strach, Hubert Harrer, Jochen Supper
  • Patent number: 10444187
    Abstract: Systems and methods can provide a fast and accurate way to measure conductivity and Hall effect, such that transient conductivities, transient carrier densities or transient mobilities can be measured on millisecond time scales, for example. The systems and methods can also reduce the minimum magnetic field needed to extract carrier density or mobility of a given sample, and reduce the minimum mobility that can be measured with a given magnetic field.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: October 15, 2019
    Assignee: Northwestern University
    Inventors: Matthew Grayson, Jiajun Luo
  • Patent number: 10424633
    Abstract: A probe card for integrated circuit testing includes a printed circuit support and a probe head having a first surface mounted to a surface of the printed circuit support. A flexible substrate is positioned adjacent to a second surface of the probe head and includes at least one flexible extension which extends beyond an edge of the probe head and includes a bend to make contact with the surface of the printed circuit support. The flexible substrate further includes a test antenna configured to support a wireless communications channel with an integrated circuit under test. The integrated circuit under test includes at least one conductive structure that extends in the peripheral portion on different planes of metallizations to form an integrated antenna that is coupled for communication and/or power transfer to the test antenna.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: September 24, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Alberto Pagani, Alessandro Finocchiaro
  • Patent number: 10416194
    Abstract: A circuit adapter board has a film circuit board, a spring probe assembly, a space, and a filler. The film circuit board has a film body and multiple conductors. The film body has multiple first contacts and multiple second contacts. A density of distribution of the second contacts is higher than a density of distribution of the first contacts. The conductors are respectively connected to the first contacts. The spring probe assembly is disposed out of the first outer layer and has a plate and multiple spring probes. The spring probes are respectively disposed in the plate. Each spring probe has a base, a connecting portion, and a contacting portion being retractable. The space is formed between the film body of the film circuit board and the plate. The filler is disposed between the film body and the plate.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: September 17, 2019
    Inventor: Hsin Lung Wu
  • Patent number: 10408869
    Abstract: In the modern world, electricity has become ubiquitous. Electrical connectors that connect and disconnect the electricity from the end use device have become important. If the connector has established a good quality contact across its mating conductors, there is no cause for concern. Also, if the connector has not established any contact with associated contacts being far away, then also there is no cause for a safety concern. However, when a connector has established marginal contact between the source and drain side contacts, and if the load and the source are switched on, the possibility of an arc across the thin layer of oxide separating the two contacts is high. This invention teaches a method to measure the quality of electrical connection established across an electrical connector. The method described here can be used to ascertain the quality of the connection before turning on the current across the connection.
    Type: Grant
    Filed: December 17, 2017
    Date of Patent: September 10, 2019
    Inventor: Satyajit Patwardhan
  • Patent number: 10359452
    Abstract: A diagnostic device comprises a comparison section to compare an input voltage with a threshold voltage, wherein the input voltage is a power supply voltage for a component on a circuit board; and an indicator to provide an indication of the result of the comparison by the comparison section, the indication to render the circuit board identifiable to direct inspection, wherein the supply of power to the component is independent of the result of the comparison.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: July 23, 2019
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jordi Hernandez Creus, Marc Bautista Palacios, Juan Luis López Rodríguez
  • Patent number: 10352965
    Abstract: A testing device includes a circuit board, a carrier, a probe pin, a main body, a shaft, a pressing portion and a resilient spiral spring. The carrier is used to hold a device under test (DUT). The probe pin is electrically connected to the circuit board and the DUT. The shaft is movably connected to the main body with a screwing rotation method. The pressing portion is connected to one end surface of the shaft. The resilient spiral spring is retractably coiled on the shaft, and one end of the resilient spiral spring being far away from the shaft extends in a transverse direction intersecting an axial direction of the shaft.
    Type: Grant
    Filed: June 11, 2017
    Date of Patent: July 16, 2019
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Ting Shih, Chia-Jung Hsieh, Chia-Jen Kao
  • Patent number: 10281614
    Abstract: In one embodiment a circuit arrangement for disturber detection comprises an input for receiving an input signal, the input being adapted to be coupled to an antenna, a receiver circuit coupled to the input which is configured to provide a demodulated signal as a function of the input signal, and a disturber rejection circuit which is coupled to an output of the receiver circuit. Therein the disturber rejection circuit is configured to provide a first signal indicative of a low energy disturber and/or a second signal indicative of a square envelope disturber, the first and second signals being provided as a function of the demodulated signal at respective outputs of the disturber rejection circuit. Furthermore, a lightning detector and a method for disturber detection are described.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: May 7, 2019
    Assignee: ams AG
    Inventor: Ruggero Leoncavallo
  • Patent number: 10230458
    Abstract: An integrated circuit optical die test interface and associated testing method are described for using scribe area optical mirror structures (106) to perform wafer die tests on MEMS optical beam waveguide (112) and optical circuit elements (113) by perpendicularly deflecting optical test signals (122) from the scribe area optical mirror structures (106) into and out of the plane of the integrated circuit die under test (104) and/or production test die (157).
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: March 12, 2019
    Assignee: NXP USA, INC.
    Inventors: Michael B. McShane, Perry H. Pelley, Tab A. Stephens
  • Patent number: 10184956
    Abstract: A probe card including a circuit board, a transformer, a probe head, and a reinforcement structure is provided. The transformer including a body, a plurality of solder balls, and a plurality of first contact points are disposed on the substrate. The body has a first surface and a second surface, wherein the first surface is located between the circuit board and the second surface. The solder balls are disposed on the first surface, and the first contact points are disposed on the second surface. The probe head is disposed on the second surface. The probe head is electrically connected to the circuit board by the first solder balls. The reinforcement structure is disposed between the probe head and the circuit board.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: January 22, 2019
    Assignee: VIA Technologies, Inc.
    Inventors: Chen-Yueh Kung, Wen-Yuan Chang, Wei-Cheng Chen
  • Patent number: 10166779
    Abstract: A method for manufacturing a liquid-discharge-head substrate includes providing a substrate having an energy-generating element and a pad, the pad having a wiring layer and a contact-probe receiving section, the contact-probe receiving section having a Vickers hardness that is higher than a Vickers hardness of the wiring layer; bringing a contact probe into contact with the contact-probe receiving section; and performing an electrical inspection by bringing the contact probe into contact with the wiring layer in the pad.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: January 1, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shiro Sujaku, Keiji Watanabe, Kouji Hasegawa, Junya Hayasaka, Satoshi Ibe
  • Patent number: 10132836
    Abstract: A method of forming surface protrusions on an article, and the article with the protrusions attached. The article may be an Integrated Circuit (IC) chip, a test probe for the IC chip or any suitable substrate or nanostructure. The surface protrusions are electroplated to a template or mold wafer, transferred to the article and easily separated from the template wafer. Thus, the attached protrusions may be, e.g., micro-bumps or micro pillars on an IC chip or substrate, test probes on a probe head, or one or more cantilevered membranes in a micro-machine or micro-sensor or other micro-electro-mechanical systems (MEMS) formed without undercutting the MEMS structure.
    Type: Grant
    Filed: May 9, 2015
    Date of Patent: November 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Bing Dang, John Knickerbocker, Yang Liu, Maurice Mason, Lubomyr T. Romankiw
  • Patent number: 10119995
    Abstract: A probe card including a circuit board, a transformer, a probe head, and a reinforcement structure is provided. The transformer including a body, a plurality of solder balls, and a plurality of first contact points are disposed on the substrate. The body has a first surface and a second surface, wherein the first surface is located between the circuit board and the second surface. The solder balls are disposed on the first surface, and the first contact points are disposed on the second surface. The probe head is disposed on the second surface. The probe head is electrically connected to the circuit board by the first solder balls. The reinforcement structure is disposed between the probe head and the circuit board.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: November 6, 2018
    Assignee: VIA Technologies, Inc.
    Inventors: Chen-Yueh Kung, Wen-Yuan Chang, Wei-Cheng Chen
  • Patent number: 10088522
    Abstract: An apparatus according to embodiments detects locations of faults in a multilayer semiconductor (MLS). The apparatus comprises a laser source that outputs a laser beam, an optical system that directs the laser beam selectively onto a target region in the MLS to generate an irradiated zone in the MLS, a stage and a scanner that control a relative position between the irradiated zone and the MLS so that the irradiated zone moves along the target region, a controller system that measures electrical signals or electrical signal changes induced by a temperature increase in the MLS, and identifies a location of the target region and locations of faults in the MLS based on the measured electrical signal or the measured electrical signal changes. The target region is made of a material of which thermal conductivity is higher than that of a material around the target region and has a structure penetrating from shallow layers to deep layers of the MLS.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: October 2, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Juan Felipe Torres, Kei Matsuoka
  • Patent number: 10018667
    Abstract: A method for testing semiconductor dies includes: providing a test apparatus; providing an electrically conductive carrier; providing a semiconductor substrate having a first main face, a second main face opposite to the first main face, and a plurality of semiconductor dies, the semiconductor dies including a first contact element on the first main face and a second contact element on the second main face; placing the semiconductor substrate on the carrier with the second main face facing the carrier; electrically connecting the carrier to a contact location disposed on the first main face; and testing a first semiconductor die of the plurality of semiconductor dies by electrically connecting the test apparatus with the first contact element of the first semiconductor die and the contact location.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: July 10, 2018
    Assignee: Infineon Technologies AG
    Inventors: Erwin Thalmann, Michael Leutschacher, Christian Musshoff, Stefan Kramp
  • Patent number: 9995770
    Abstract: One or more probe cards, wafer testers, and techniques for testing a semiconductor arrangement are provided. Testline arrangements are formed within scribe lines of a semiconductor wafer, in multiple directions, such as an x-direction and a y-direction. A wafer tester is configured to concurrently test the semiconductor arrangement in multiple directions using a multidirectional probe arrangement of a probe card. In some embodiments, a first pin arrangement of the multidirectional probe arrangement is mated with a first testline arrangement in a first direction, and a second pin arrangement of the multidirectional probe arrangement is mated with a second testline arrangement in a second direction. The wafer tester concurrently tests the semiconductor arrangement in multiple directions, such as in the first direction and the second direction, through the pin arrangements mated with the testline arrangements.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: June 12, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tseng-Chin Lo, Huan Chi Tseng, Kuo-Chuan Chang, Yuan-Yao Chang, Chien-Chang Lee
  • Patent number: 9989558
    Abstract: Probe head assemblies, components of probe head assemblies, test systems including the probe head assemblies and/or components thereof, and methods of operating the same. The probe head assemblies are configured to convey a plurality of test signals to and/or from a device under test and include a space transformer, a contacting assembly, and a riser that spatially separates the space transformer from the contacting assembly and conveys the plurality of test signals between the space transformer and the contacting assembly. The contacting assembly may include a frame that defines an aperture and has a coefficient of thermal expansion that is within a threshold difference of that of the device under test, a flexible dielectric body that is attached to the frame, maintained in tension by the frame, and extends across the aperture, and a plurality of conductive probes. The plurality of conductive probes may include a dual-faceted probe tip.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: June 5, 2018
    Assignee: Cascade Microtech, Inc.
    Inventors: Koby Duckworth, Eric Hill
  • Patent number: 9977052
    Abstract: An example test fixture, which interfaces a tester and a unit under test (UUT), includes the following: first electrical contacts that face the tester; second electrical contacts that face the UUT; a substrate made of sections of printed first material, with the first material being electrically non-conductive, and with the substrate being between the first electrical contacts and the second electrical contacts; and structures through the substrate, with the structures including sections of second material, with the second material being electrically conductive, and with at least one of the structures electrically connecting a first electrical contact and a second electrical contact.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: May 22, 2018
    Assignee: Teradyne, Inc.
    Inventors: Anthony J. Suto, Joseph Francis Wrinn, John P. Toscano, John Joseph Arena
  • Patent number: 9972890
    Abstract: A wireless device including at least one parallel resonance element and a plurality of serial resonance components is provided. The at least one parallel resonance element may be configured to radiate in at least one frequency. The plurality of serial resonance components may be configured to radiate in a plurality of frequencies. The device may further include a distributed feed element configured to couple to the parallel resonance element and the serial resonance components and serve as a radiofrequency signal feed.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: May 15, 2018
    Assignee: Galtronics Corporation Ltd.
    Inventor: Matti Martiskainen
  • Patent number: 9928767
    Abstract: A system and method of testing chip-on-glass (COG) bonding quality automatically includes a glass panel comprising two test pads, the test pads electrically interconnected, a display driver comprising an input node and an output node, and an adhesive layer between the glass panel and the display driver, the adhesive layer binding the glass panel with the display driver, the adhesive layer comprising conductive portions across the adhesive layer between the glass panel and the display driver, wherein the input node, the output node, the two test pads, and the conductive portions are electrically connected to form an electrical testing loop, the electrical testing loop configured to measure a voltage drop across the conductive portions.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: March 27, 2018
    Assignee: Futurewei Technologies, Inc.
    Inventors: Xiangan Zhu, Guoping Luo, Qian Han, Shunlin Chen, Guangrong Wu, Jose Garcia, Steven R. Loza, Chuanning Chen
  • Patent number: 9880202
    Abstract: A probe card for an apparatus for testing electronic devices comprises at least one probe head, a plurality of contact probes housed within the probe head, each contact probe having at least one contact tip suitable to abut against contact pads of a device to be tested, a supporting plate of the probe head, an interface plate, a stiffener associating the supporting plate and the interface plate, a plurality of connecting elements with clearance disposed between the supporting plate and the interface plate and housed in a floating manner in a plurality of respective seats made in the supporting plate, and a plurality of connecting elements without clearance disposed between the interface plate and the stiffener.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: January 30, 2018
    Assignee: Technoprobe S.p.A.
    Inventors: Riccardo Vettori, Riccardo Liberini
  • Patent number: 9870959
    Abstract: Techniques for electrically testing a flip-chip assembly during its manufacture include a flip-chip assembly having an integrated circuit (IC) die and an IC package substrate. The IC package substrate is placed on a substrate part holder that includes test sockets and heating elements. The IC die is then placed on the placed IC package substrate. The placed IC die and IC package substrate are aligned such that conductive contacts are formed from conductive bumps and pads deposited on the surface of the IC die and IC package substrate. While the bumps and pads are in conductive contact, but prior to attachment, the flip-chip assembly is electrically tested. If the flip-chip assembly passes electrical testing, the conductive contacts may be attached by the heating elements on the substrate part holder, such as in a solder reflow process when the bumps are made from solder.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: January 16, 2018
    Assignee: ALTERA CORPORATION
    Inventor: Nagesh Vodrahalli
  • Patent number: 9846193
    Abstract: A semiconductor package testing apparatus comprises a package holder for holding a semiconductor package and which is positionable together with the semiconductor package at a test contactor station. There are probe pins located at the test contactor station for contacting a bottom surface of the semiconductor package and which are configured to apply an upwards force on the semiconductor package during testing of the semiconductor package. A restraining mechanism that is movable from a first position remote from the package holder and a second position over the package holder is configured to restrict lifting of the semiconductor package by the probe pins during testing of the semiconductor package when the restraining mechanism is at its second position.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: December 19, 2017
    Assignee: ASM TECHNOLOGY SINGAPORE PTE LTD
    Inventors: Chak Tong Sze, Pei Wei Tsai, Cho Hin Cheuk, Si Ming Chan, Kam Sing Lee
  • Patent number: 9843493
    Abstract: The measuring system comprises a measuring device and a device under test (9). This measuring device comprises a high-frequency processing unit (11), which is embodied to receive high-frequency signals from the device under test (9) and/or to transmit high-frequency signals to the device under test (9) via a first connection (5). The measuring system further comprises a test-software server unit (12), which is embodied to supply test-software to the device under test (9).
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: December 12, 2017
    Assignee: ROHDE & SCHWARZ GMBH & CO. KG
    Inventors: Uwe Baeder, Holger Jauch, Ingo Gruber
  • Patent number: 9804194
    Abstract: A contact for use in a test set which can be mounted to a load board of a tester apparatus. The contact, which serves to electrically connect at least one lead of a device being tested with a corresponding metallic trace on the load board, has a first end defining multiple contact points. As the test pin is rotated about an axis generally perpendicular to a plane defined by the contact, successive contact points are sequentially engaged by a lead of the device being tested. The test pin has a hard stop edge which engages a hard stop wall which limits its rotation movement. The bottom of the pin has a shallow convex curvature preferably with a flat region and the tip of the test pin has a chisel edge.
    Type: Grant
    Filed: February 28, 2016
    Date of Patent: October 31, 2017
    Assignee: Johnstech International Corporation
    Inventor: Michael Andres
  • Patent number: 9766269
    Abstract: A conductive probe may include a probe body for communicating with a circuit tester or a jumper. The probe body may be formed of metal and may have a free end. A probe tip may be mounted to the end of the probe body. The probe tip may be formed of thorium-tungsten. The probe tip may be configured for contacting a circuit node.
    Type: Grant
    Filed: December 29, 2012
    Date of Patent: September 19, 2017
    Assignee: Power Probe TEK, LLC
    Inventor: Wayne Russell
  • Patent number: 9678142
    Abstract: The present invention relates generally to testing of interconnects in a semiconductor die, and more particularly to testing of semiconductor chips that are three-dimensionally stacked via an interposer. In one aspect, a method for testing an interconnect in a semiconductor die comprises providing the semiconductor die, which includes a plurality of electrical contact elements formed at one or more surfaces of the semiconductor die, at least one interconnect-under-test disposed between a first electrical contact element and a second electrical contact element, and an electrical component electrically coupled between the interconnect-under-test and at least one third electrical contact element.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: June 13, 2017
    Assignee: IMEC
    Inventors: Julien Ryckaert, Erik Jan Marinissen, Dimitri Linten
  • Patent number: 9678110
    Abstract: A probe card includes a circuit board, a plurality of probes, and at least one deviation-compensating member. An end of each of the probes is connected to the circuit board. The deviation-compensating member is fixed to the circuit board and connected to the probes. The probes have a first thermal expansion characteristic, the deviation-compensating member has a second thermal expansion characteristic, and the first thermal expansion characteristic and the second thermal expansion characteristic are different.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: June 13, 2017
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chieh Liao, Yu-Min Sun, Chih-Feng Cheng
  • Patent number: 9632044
    Abstract: A method that includes performing multiple test iterations to provide multiple test results; and processing the multiple test results to provide estimates of a conductivity of each of the multiple bottoms segments. The multiple test iterations includes repeating, for each bottom segment of the multiple bottom segments, the steps of: (a) illuminating the bottom segment by a charging electron beam; wherein electrons emitted from the bottom segment due to the illuminating are prevented from exiting the hole; (b) irradiating, by a probing electron beam, an area of an upper surface of the dielectric medium; (c) collecting electrons emitted from the area of the upper surface as a result of the irradiation of the area by the probing electron beam to provide collected electrons; and (d) determining an energy of at least one of the collected electrons to provide a test result.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: April 25, 2017
    Assignee: APPLIED MATERIALS ISREAL LTD.
    Inventors: Alon Litman, Konstantin Chirko
  • Patent number: 9535091
    Abstract: A probe head includes a first substrate, a second substrate, a spacer, at least one probe, and an insulating material. The first substrate has at least one first through hole. The second substrate has at least one second through hole. The spacer is disposed between the first substrate and the second substrate. The spacer, the first substrate, and the second substrate together form a cavity. The probe is disposed in the cavity and protrudes from the first through hole and the second through hole. The insulating material is on the probe and at least partially disposed in the first through hole.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: January 3, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Cheng Hsu, Wen-Feng Liao, Wen-Tsai Su, Yuan-Pin Huang
  • Patent number: 9506974
    Abstract: An active probe card capable of improving testing bandwidth of a device under (DUT) test includes a printed circuit board; at least one probe needle, affixed to a first surface of the printed circuit board for probing the DUT; at least one connection member, electrically connected to the at least one probe needle; and an amplification circuit, formed on the printed circuit board and coupled to the at least one connection member for amplifying an input or output signal of the DUT.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: November 29, 2016
    Assignee: Sitronix Technology Corp.
    Inventors: Hung-Wei Lai, Tsung-Jun Lee
  • Patent number: 9459307
    Abstract: An in-circuit testing auto open and close system, apparatus and method includes an in-circuit tester having an upper panel and a lower panel, wherein the upper and lower panels are used to test electrical connections of one or more electronic units. One or more actuators are each coupled to both the upper panel and the lower panel such that they are able to move the upper and lower panels with respect to each other. As a result, a controller coupled with the in-circuit tester and the actuators is able to cause the actuators to automatically close the panels such that the panels sandwich the electronic units at the beginning of a testing program and to automatically open the panels such that the panels are separated at the end of the testing program.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: October 4, 2016
    Assignee: Flextronics AP, LLC
    Inventors: Juan Francisco Duran Hernandez, Jose Antonio Becerra Castrejon
  • Patent number: 9449920
    Abstract: An electronic device is disclosed. The electronic device comprises a transistor provided on a substrate, a transmission line provided on the substrate and connected to the transistor, an electrode pad connected to the transmission line, and a connection wiring electrically connecting the electrode pad and the transmission line through a first wiring and a second wiring. Both of the first wiring and the second wiring are connected to different positions of the electrode pad.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: September 20, 2016
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Osamu Baba, Takeshi Kawasaki
  • Patent number: 9418970
    Abstract: Redistribution layers for microfeature workpieces, and associated systems and methods are disclosed. One method for processing a microfeature workpiece system includes positioning a pre-formed redistribution layer as a unit proximate to and spaced apart from a microfeature workpiece having an operable microfeature device. The method can further include attaching the redistribution layer to the microfeature workpiece and electrically coupling the redistribution layer to the operable microfeature device.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: August 16, 2016
    Assignee: Micron Technology, Inc.
    Inventor: David Pratt
  • Patent number: 9383389
    Abstract: A prober 10 including a probe card 16 having multiple probe needles 17 includes a needle-tip polishing unit 24, and the needle-tip polishing unit 24 includes a WAPP 28 to be contacted with needle tips and a supporting member 27 configured to support the WAPP 28. On a top surface of the WAPP 28, a wrapping sheet 29 is provided, and the WAPP 28 includes multiple recesses 31 formed on a bottom surface 30 thereof and the supporting member 27 includes multiple protrusions 33 formed on a ceiling surface 32 thereof. When the WAPP 28 is moved to a retreat position, the protrusions 33 are respectively inserted and fitted into the recesses 31, and when the WAPP 28 is moved to a contact position, top portions of the protrusions 33 are respectively brought into contact with portions on the bottom surface 30 where the recesses 31 are not formed.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: July 5, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kazuya Yano, Shuji Akiyama
  • Patent number: 9354192
    Abstract: The present invention relates to a ferroelectric analyzing device and a method for adjusting ferroelectric domain switching speed with the ferroelectric analyzing device, and pertains to the technical field of characteristic test of solid-state dielectrics. The ferroelectric analyzing device comprises a voltage pulse generator for generating square pulse signal, which is biased on a ferroelectric thin film so as to switch the polarization of ferroelectric domains, the ferroelectric analyzing device further comprises a variable resistor which is connected in series with the ferroelectric thin film. The variable resistor is used for adjusting domain switching current so as to realize adjustment of domain switching speed of ferroelectric domains. In the method, the square pulse signal is biased on the ferroelectric thin film, and an adjustment of domain switching speed of ferroelectric domains can be realized by adjusting the resistance value of the variable resistor.
    Type: Grant
    Filed: April 4, 2011
    Date of Patent: May 31, 2016
    Assignee: Fudan University
    Inventors: Anquan Jiang, Xiaobing Liu
  • Patent number: 9347971
    Abstract: A probing device includes a circuit board, a reinforcing plate, at least one space transformer and at least one probe assembly. The reinforcing plate is disposed on the circuit board, and the reinforcing plate has a plurality of inner conductive wires electrically connecting to those of the circuit board. The reinforcing plate defines a plurality of receiving space therein. The space transformer is disposed on the reinforcing plate, and the space transformer has a plurality of inner conductive wires electrically connecting to those of the reinforcing plate via a plurality of first solder balls. The probe assembly is disposed on the space transformer, and the probe assembly includes a plurality of probes. The first solder balls are disposed in the receiving spaces, and the reinforcing plate abuts against the space transformer.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: May 24, 2016
    Assignee: MPI CORPORATION
    Inventors: Chien-Chou Wu, Ming-Chi Chen, Chung-Che Li
  • Patent number: 9335376
    Abstract: The disclosed ring-oscillator-based test architecture comprises a plurality of boundary scan cells coupled to a plurality of interconnects and control circuitry. Each of the plurality of boundary scan cells can be configured to operate as, based on control signals, a conventional boundary scan cell or any bit of an asynchronous counter. The control signals are supplied by the control circuitry.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: May 10, 2016
    Assignee: Mentor Graphics Corporation
    Inventors: Wu-Tung Cheng, Ruifeng Guo, Yu Huang, Liyang Lai, Jing Ye, Yu Hu
  • Patent number: 9322714
    Abstract: A method of manufacturing a particle-based image display having a plurality of imaging cells is disclosed. The method includes filling the plurality of imaging cells with a plurality of first particles, identifying a defect associated with one or more of the imaging cells, and repairing the defect within a unit corresponding to part of the plurality of imaging cells.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: April 26, 2016
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Jui-Yu Lin, Jen-Ming Chang, Jiunn-Jye Hwang, Jung-Yang Juang, Ming-Hai Chang, Hao-Jan Wan
  • Patent number: 9304341
    Abstract: A signal panel for checking images displayed on liquid crystal devices is disclosed. The signal panel includes: a power supply mainboard; a plurality of low voltage differential signaling plugs arranged on the power supply mainboard for directly engaging with the low voltage differential signaling sockets of the liquid crystal device; a plurality of low voltage differential signaling adapters arranged on the power supply mainboard for engaging with the low voltage differential signaling sockets of the liquid crystal device via the adapters; and a plurality of frequency-angle adjusting switches of the low voltage differential signals arranged on the power supply mainboard for adjusting frequency-angle parameters of the low voltage differential signals of the liquid crystal device. The signal panel can test the liquid crystal device without using connecting wires and signal generators, which effectively reduce the cost.
    Type: Grant
    Filed: December 24, 2013
    Date of Patent: April 5, 2016
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Guochuan Huang
  • Patent number: 9291669
    Abstract: A semiconductor device, a test structure of the semiconductor device, and a method of testing the semiconductor device are provided. The test structure including a first pad and a second pad being separated from each other, and a first test element and a second test element connected between the first pad and the second pad, a first value of a characteristic parameter of the first test element being different from a second value of the characteristic parameter of the second test element, may be provided.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: March 22, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-Myoung Lee, Il-Kwon Lee, Jun-Woo Lee, Sang-Goo Jung, Kyoung-Mi Park, In-Ae Lee