Test Probe Techniques Patents (Class 324/754.01)
  • Patent number: 10416512
    Abstract: A display substrate and a test method thereof are disclosed. The display substrate includes a test wire connected to a first gate driving circuit and a second gate driving circuit; a high vertical alignment process test pad disposed on at least one side of the test wire; a first array test pad electrically connected to the first gate driving circuit and connected to the test wire to form a first connection node; a second array test pad electrically connected to the second gate driving circuit and connected to the test wire to form a second connection node; and a switch unit formed between the first connection node and the second connection node for controlling the test wire to connect or disconnect.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: September 17, 2019
    Assignees: HKC CORPORATION LIMITED, CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CORPORATION LIMITED
    Inventor: Yu-jen Chen
  • Patent number: 10186180
    Abstract: A display device includes a display panel including a first and a second non-display area, a main active area, and a sub active area, wherein the active areas each include a matrix of sub-pixels; a data driver in the first non-display area to provide image data to the matrices of sub-pixels; a main gate driver in the second non-display area to provide a corresponding gate signal to each sub-pixel in the main active area; a sub gate driver in the second non-display area to provide a corresponding gate signal to each sub-pixel in the sub active area; an auto-probe test pad in the non-display area for transmitting a first start signal received from an auto-probe signal generating device to one of the main gate driver and the sub gate driver while testing the display panel; and a signal transmission circuit connecting the main gate driver and the sub gate driver.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: January 22, 2019
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Jaehoon Park, Jinho Lim, Cheolhwan Lee, Kyunghyun Jeon
  • Patent number: 10012676
    Abstract: A probe card and a testing method are disclosed herein. The probe card includes a plurality of probe sets arranged as a testing unit. The testing unit is configured to test a plurality of dies in a test region on a wafer, and to move m unit along a first direction and n unit along a second direction when the test complete so as to test the next test region, in which m and n are integers.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: July 3, 2018
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Chang-Ming Liu
  • Patent number: 9837289
    Abstract: Package-on-Package (PoP) structures and methods of forming the same are disclosed. In some embodiments, a method of forming a PoP structure may include: plating at least one through-assembly via (TAV) over a peripheral region of a conductive seed layer; forming a dam member over a central region of the conductive seed layer; and placing a die over the central region of the conductive seed layer. The dam member may be laterally separated from the die and disposed between the die and the at least one TAV. The method may further include encapsulating the die, the dam member, and the at least one TAV in a polymer material.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: December 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shou-Cheng Hu, Ching-Wen Hsiao, Chen-Shien Chen
  • Patent number: 9613715
    Abstract: The various embodiments described herein include systems, methods and/or devices used to package non-volatile memory. In one aspect, the method includes: (1) selecting, from a set of non-volatile memory die, a plurality of non-volatile memory die on which one or more tests have been deferred until after packaging, the selecting in accordance with wafer positions of the plurality of non-volatile memory die and statistical die performance information corresponding to the wafer positions; and (2) packaging the selected plurality of non-volatile memory die. In some embodiments, after said packaging, the method further includes performing a set of tests on the plurality of non-volatile memory die to identify respective units of memory within the plurality of non-volatile memory die that meet predefined validity criteria, wherein the set of tests performed include at least one of the deferred one or more tests.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: April 4, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jack Edward Frayer, Vidyabhushan Mohan
  • Patent number: 9500674
    Abstract: A probe structure includes a sleeve, a needle shaft and an elastic member. The needle shaft is accommodated in the sleeve and includes a first groove for accommodating the elastic member. The probe structure further includes a conductive component installed at the bottom of the sleeve and having an end connected into the first groove, and a second groove, so that the elastic member is situated in the first and second grooves. When the needle shaft is pressed and moved, the inner wall of the second groove is contacted with an outer sidewall of the conductive component to define a second conductive channel. With the two conductive channels, the effects of maintaining stable current transmission efficiency, reducing poor contact or disconnection, and providing good structural stability are achieved.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: November 22, 2016
    Assignee: C.C.P. CONTACT PROBES CO., LTD.
    Inventors: Yu-Min Cheng, You-Yu Lo, Chien-Yu Hsieh
  • Patent number: 9030216
    Abstract: Various exemplary embodiments provide probes, systems and methods for measuring an effective electrical resistance/resistivity with high sensitivity. In one embodiment, the measuring system can include an upper probe set and a similar lower probe set having a sample device sandwiched there-between. The device-under-test (DUT) samples can be sandwiched between two conductors of the sample device. Each probe set can have an inner voltage sense probe coaxially configured inside an electrically-isolated outer current source probe that has a large contact area with the sample device. The measuring system can also include a computer readable medium for storing circuit simulations including such as FEM simulations for extracting a bulk through-plane electrical resistivity and an interface resistivity for an effective electrical z-resistivity of the DUT, in some cases, having sub-micro-ohm resistance.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: May 12, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Michael Anthony Lamson, Siva Prakash Gurrum, Rajiv Dunne
  • Patent number: 9018958
    Abstract: An apparatus for measuring electrical parameters for an electrical system measures a first and second parameters of the electrical system between connections to the electrical system. A processor determines a third electrical parameter of the electrical system as a function of the first parameter and the second parameter. Wireless communication is provided between components of the apparatus.
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: April 28, 2015
    Assignee: Midtronics, Inc.
    Inventor: Kevin I. Bertness
  • Patent number: 8988092
    Abstract: A probing apparatus for semiconductor devices provides a primary circuit board and a signal-adapting board positioned on the primary circuit board. The primary circuit board includes an inner area having a plurality of first contacts and an outer area having a plurality of first terminals and second terminals, and the first contacts are electrically connected to the first terminals via first conductive members in the primary circuit board. The signal-adapting board includes a plurality of second contacts electrically connected to the first contacts via second conductive members in the signal-adapting board.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: March 24, 2015
    Assignee: Star Technologies Inc.
    Inventors: Chen Jung Hsu, Chao Cheng Tseng
  • Patent number: 8988094
    Abstract: The invention relates to a test contact arrangement (15) for testing semiconductor components, comprising at least one test contact (10) which is arranged in a test contact frame (13) and is designed in the type of a cantilever arm and which has a fastening base (12) and a contact arm (30) which is provided with a contact tip (11) and which is connected to the fastening base, wherein the fastening base is inserted with a fastening projection (16) thereof into a frame opening (14) of the test contact frame in such a manner that a lower edge (17) of the fastening projection is essentially aligned flush with a lower side (18) of the test contact frame.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: March 24, 2015
    Assignee: Pac Tech-Packaging Technologies GmbH
    Inventor: Ghassem Azdasht
  • Patent number: 8981803
    Abstract: A method for cleaning a contact pad of a microstructure or device to be tested when it is in electric contact with a measure apparatus, being obtained by electrically contacting a flexible probe with said contact pad. The method includes mechanically engaging a free end of the flexible probe in a manner that sticks the free end in the pad; and laterally flexing, by a tip charge, the flexible probe in a manner that keeps the free end stuck in the pad, so as to locally dig into a covering layer of the pad and realize a localized crushing thereof.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: March 17, 2015
    Assignee: Technoprobe S.p.A.
    Inventor: Riccardo Vettori
  • Patent number: 8975905
    Abstract: A display apparatus includes a display panel including a plurality of pixels, a plurality of first lines and a plurality of second lines, a plurality of first pads electrically connected to the first lines, respectively, where the first pads are divided into a first group and a second group, a plurality of pads including a second pad, a third pad, a fourth pad and a fifth pad, a first shorting bar configured to be connected to the first group of the first pads and to be connected between the second pad and the fourth pad during a test process of the first lines, and a second shorting bar configured to be connected to the second group of the first pads and to be connected between the third pad and the fifth pad during the test process of the first lines.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: March 10, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: EunJu Kim, Bonyong Koo, Dong-Yoon Lee
  • Patent number: 8975906
    Abstract: A probe for inspecting electronic components, and more particularly, to a probe for inspecting electronic components, which connects a target electronic component to an inspection apparatus to inspect defects of the target electronic component. The probe for inspecting electronic components includes: a cylinder body having a cylindrical shape; a piston body reciprocating between an inside and an outside of the cylinder body; a spring surrounding an outer circumference of the cylinder body and the piston body, and forcing a part of the piston body to resiliently move out of the cylinder body when inserted into the cylinder body; a probing unit extending from the cylinder body to be brought into contact with a target electronic component to be inspected as to flow of electric current therethrough; and a contact unit extending from the piston body to be connected to an inspection apparatus for inspecting the target electronic component.
    Type: Grant
    Filed: July 6, 2010
    Date of Patent: March 10, 2015
    Assignee: NTS Co., Ltd.
    Inventor: Woo-Yoel Jeong
  • Patent number: 8976609
    Abstract: The various embodiments described herein include systems, methods and/or devices used to packaging non-volatile memory. In one aspect, the method includes, selecting, from a set of non-volatile memory die, a plurality of non-volatile memory die on which predefined die-level and sub-die level tests have been deferred until after packaging, in accordance with predefined criteria and predefined statistical die performance information corresponding to the set of non-volatile memory die. The method further includes packaging the selected plurality of non-volatile memory die into a memory device. After said packaging, the method further includes performing a set of tests on the plurality of non-volatile memory die in the memory device to identify respective units of memory within the non-volatile memory die in the memory device that meet predefined validity criteria, wherein the set of tests performed include the deferred predefined die-level and sub-die level tests.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: March 10, 2015
    Assignee: SanDisk Enterprise IP LLC
    Inventors: Jack Edward Frayer, Vidyabhushan Mohan
  • Patent number: 8970245
    Abstract: A probing device for a TFT-LCD substrate, which includes a device body, a device body, a circuit board mounted on the device body, a plurality of motors mounted on the device body, and a plurality of probe pins respectively mounted to the motors. The motors and the probe pins are arranged in a one-to-one corresponding manner. The circuit board includes a programmable logic controller and a man-machine interface terminal electrically connected to the programmable logic controller. The plurality of motors and the plurality of probe pins are electrically connected to the programmable logic controller. The plurality of probe pins is set at locations corresponding to locations of panel inspection signal input pads of TFT substrates of various sizes. The programmable logic controller uses the motors to control the elevation and lowering of the probe pins.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: March 3, 2015
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventor: Haijian Zhang
  • Patent number: 8970238
    Abstract: A probe module for testing an electronic device comprises at least two contacts, each contact including a first end portion extending in a first direction along a first line, a second end portion extending linearly in a second direction opposite from the first direction and along a second line, and a third curved portion extending between the first end portion and the second end portion. The first line is spaced apart from and in parallel with the second line, and the at least two contacts are spaced apart from each other in a direction perpendicular to the first line and the second line. Methods for making such a probe module are also taught.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: March 3, 2015
    Assignee: Electro Scientific Industries, Inc.
    Inventor: Douglas J. Garcia
  • Patent number: 8952713
    Abstract: A device tester is provided. The device tester includes a probe card and a substrate coupled to the probe card. The substrate has a plurality of layers for routing a signal. An integrated circuit is coupled to the substrate. The integrated circuit is operable to transmit an input signal received from a testing apparatus to a device under test through the substrate to a signal probe. The signal probe is further operable to receive a test signal from the device under test in response to the input signal, wherein the integrated circuit is operable to amplify the test signal, and transmit the amplified test signal to the testing apparatus.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: February 10, 2015
    Assignee: Altera Corporation
    Inventors: Jayabrata Ghosh Dastidar, Aman Aflaki Beni, Zunhang Yu Kasnavi
  • Patent number: 8947114
    Abstract: An inspecting method for an object to be inspected is provided to bring probes of a probe card into electrical contact with a predetermined number of devices of target devices of the object at a time to inspect electrical characteristics of the target devices by moving a mounting table for mounting thereon the object under the control of a control unit. Upon completion of the inspection of the target devices, if inspection errors have occurred in specific devices of the target devices in a regular pattern, the target devices are re-examined, and when the re-examination is carried out, a contact position between the probe card and the object is displaced from a contact position in a previous inspection by a distance of at least one device to inspect electrical characteristics of the number of devices of the target devices at a time.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: February 3, 2015
    Assignee: Tokyo Electron Limited
    Inventor: Hideaki Tanaka
  • Patent number: 8937484
    Abstract: The terminals of a device under test are temporarily electrically connected to corresponding contact pads on a load board by a series of electrically conductive pin pairs. The pin pairs are held in place by an interposer membrane that includes a top contact plate facing the device under test, a bottom contact plate facing the load board, and a vertically resilient, non-conductive member between the top and bottom contact plates. Each pin pair includes a top and bottom pin, which extend beyond the top and bottom contact plates, respectively, toward the device under test and the load board, respectively. The top and bottom pins contact each other at an interface that is inclined with respect to the membrane surface normal. When compressed longitudinally, the pins translate toward each other by sliding along the interface. The sliding is largely longitudinal, with a small and desirable lateral component determined by the inclination of the interface.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: January 20, 2015
    Assignee: Johnstech International Corporation
    Inventors: John E. Nelson, Jeffrey C. Sherry, Patrick J. Alladio, Russell F. Oberg, Brian Warwick, Gary W. Michalko
  • Patent number: 8928343
    Abstract: A method and apparatus are provided for transmission/reception of signals between automatic test equipment (ATE) and a device under test (DUT). A probe card has a plurality of associated proximate active probe integrated circuits (APIC) connected to a plurality of probes. Each APIC interfaces with one or more test interface points on the DUT through probes. Each APIC receives and processes signals communicated between the ATE and the DUT. Low information content signals transmitted from the ATE are processed into high information content signals for transmission to the probe immediately adjacent the APIC, and high information content or time critical signals received by the APIC from the DUT are transmitted as low information content signals to the ATE. Because the APIC is immediately adjacent the probe there is minimum loss or distortion of the information in the signal from the DUT.
    Type: Grant
    Filed: April 3, 2008
    Date of Patent: January 6, 2015
    Assignee: Scanimetrics Inc.
    Inventors: Christopher V. Sellathamby, Steven Slupsky, Brian Moore
  • Patent number: 8922229
    Abstract: A method is disclosed for the measurement of a power device in a prober, which serves the examination and testing of such components. In the process, a power device is held by a chuck, and at least one electric probe is held by a probe holder, and optionally, the power device or the probe is positioned each relative to the other using a positioning device with an electrical drive, and contacts the power device. At the same time, an electrical connection remains between the probe to a signal unit with which a power signal is sent out or received, is blocked and only unblocked when it is determined that the contact between probe 26 and contact area is established.
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: December 30, 2014
    Assignee: Cascade Microtech, Inc.
    Inventors: Botho Hirschfeld, Stojan Kanev
  • Patent number: 8922196
    Abstract: A multifunction test instrument probe includes a housing having a hollow bore with an open end. A clamp plunger is carried in the hollow bore, with a first end including a thumb press, and a second end including an alligator clamp having a pair of jaws, with a compression spring normally biasing the thumb press away from the housing, and normally biasing the alligator clamp substantially within the hollow bore proximate the open end. A point plunger is also carried in the bore, with a first end including a thumb press, and a second end terminating in a point, with a second compression spring normally biasing the thumb press away from the housing, and biasing the point within the hollow bore proximate the open end.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 30, 2014
    Inventors: Paul Nicholas Chait, Stanley Chait
  • Patent number: 8917105
    Abstract: A testing apparatus for measuring the material properties of solder balls includes a frame and a chuck base moveable in X, Y, Z dimensions, relative to the frame. A probe tip is fixed to the frame. A measuring device is mounted to the frame and maintains a spacing with relationship to the probe tip and which has an initial, known height above the chuck base.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventor: David L. Gardell
  • Patent number: 8907689
    Abstract: A retention arrangement that includes one or more templates for securing and aligning probes for testing a device under test.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: December 9, 2014
    Assignee: MicroProbe, Inc.
    Inventors: January Kister, Alex Shtarker
  • Patent number: 8901947
    Abstract: Detecting misalignment of test probes with component carriers in an automated test system is taught. Automated test systems for testing electronic components can have electronic components held in component carriers in preparation for testing. Testing can include moving test probes through openings provided in the component carrier to contact the electronic components held therein. Aspects of disclosed implementations use force feedback from the test probes to determine if the test probes have successfully contacted the electronic component without, for example, contacting the component carrier.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: December 2, 2014
    Assignee: Electro Scientific Industries, Inc.
    Inventors: Joseph Johann Emery, Jae H. Kim, Daniel Joel Boatright, Michael Charley Stocks, James Ray Huntington
  • Patent number: 8901946
    Abstract: Apparatus and methods for identifying a signal on a printed circuit board (‘PCB’) under test, including an integrated circuit mounted on the PCB, the integrated circuit having a test signal generator that transmits a test signal to an output pin of the integrated circuit, with the output pin connected to a test point on the PCB; the integrated circuit also having signal identification logic that inserts into the test signal, an identifier of the signal; a test probe in contact with the test point; and a signal-identifying controller that receives the test signal and the identifier from the test probe and displays, in dependence upon the identifier, the identity of the signal.
    Type: Grant
    Filed: May 24, 2010
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bhyrav M. Mutnury, Nam H. Pham, Terence Rodrigues
  • Patent number: 8896339
    Abstract: A semiconductor wafer includes semiconductor chips divided by a dicing line, one of the semiconductor chips including terminals of an identical potential; a wiring located on the dicing line, and electrically connecting the terminals to each other; and a pad electrically connected through the wiring to the terminals, wherein the pad is located entirely on the semiconductor chip and is not present on the dicing line.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: November 25, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventor: Jun Takaso
  • Patent number: 8884638
    Abstract: A circuit configuration monitors the electrical insulation of an electrically conductive part in relation to a first pole and a second pole of an electrical power network for example, an electrical drive network in a hybrid vehicle. The circuit configuration is characterized in that between the electrically conductive part and the two poles, a voltage divider having at least two resistors is arranged in each case. A measuring unit is associated with each of the two voltage dividers and provided for measuring a partial voltage, which drops via at least one of the resistors. A switch unit is associated each with the two voltage dividers and is provided for alternately bypassing at least one of the resistors.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: November 11, 2014
    Assignee: Continental Automotive GmbH
    Inventors: Volker Karrer, Christian Kuschnarew
  • Patent number: 8884639
    Abstract: In one embodiment, a method for testing a plurality of singulated semiconductor die involves 1) placing each of the singulated semiconductor die on a surface of a die carrier, 2) mating an array of electrical contactors with the plurality of singulated semiconductor die, and then 3) performing electrical tests on the plurality of singulated semiconductor die, via the array of electrical contactors.
    Type: Grant
    Filed: August 27, 2009
    Date of Patent: November 11, 2014
    Assignee: Advantest (Singapore) Pte Ltd
    Inventors: James C. Anderson, Alan D. Hart, Kenneth D. Karklin
  • Patent number: 8878560
    Abstract: The present disclosure provide a probe card for wafer level testing. The probe card includes a space transformer having a power line, a ground line, and signal lines embedded therein, wherein the space transformer includes various conductive lines having a first pitch on a first surface and a second pitch on a second surface, the second pitch being substantially less than the first pitch; a printed circuit board configured approximate the first surface of the space transformer; and a power plane disposed on the first surface of the space transformer and patterned to couple the power line and the ground line of the space transformer to the printed circuit board.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: November 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Hsin Kuo, Wensen Hung
  • Publication number: 20140320157
    Abstract: A probe for a measurement instrument comprises an input terminal configured to receive an input signal from a device under test (DUT), an output terminal configured to transmit an output signal to a measurement instrument, and a clamping circuit disposed in a signal path between the input terminal and the output terminal and configured to clamp an internal probe signal between an upper clamping threshold and a lower clamping threshold to produce the output signal, wherein the clamping circuit operates with substantial gain and amplitude linearity throughout a range between the upper clamping threshold and the lower clamping threshold.
    Type: Application
    Filed: April 24, 2013
    Publication date: October 30, 2014
    Applicant: Agilent Technologies, Inc.
    Inventors: Edward Vernon BRUSH, IV, Michael T. MCTIGUE, Kenneth W. JOHNSON
  • Patent number: 8866505
    Abstract: A measurement apparatus for surface analysis carried out in a gaseous environment such as air comprises a measurement device capable of measuring a contact potential difference between a probe and a surface, and a light source that triggers photoelectric emission from a sample. The apparatus may operate in “dual” photoemission and contact potential difference (CPD) measurement modes.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: October 21, 2014
    Assignee: KP Technology Ltd.
    Inventor: Iain Baikie
  • Patent number: 8866506
    Abstract: A contact structure for inspection that is installed on a bottom surface of a circuit board includes a ground conductor that is grounded; an elastic contact member that is brought into contact with an inspection target object; and a conductive line that electrically connects the circuit board and the elastic contact member. Here, the elastic contact member may be provided on a bottom surface of the ground conductor that is grounded. The elastic contact member may include an insulating layer, a wiring layer, a contactor and an elastic body provided at a position corresponding to the contactor. The elastic body provides the elastic contact member with elasticity when the contactor is brought into contact with an electrode. The elastic contact member is provided in parallel with the ground conductor. The wiring layer and the ground conductor form a microstrip line.
    Type: Grant
    Filed: June 17, 2009
    Date of Patent: October 21, 2014
    Assignee: Tokyo Electron Limited
    Inventor: Jun Mochizuki
  • Patent number: 8836362
    Abstract: A switch probe for use in a substrate inspection device to inspect a substrate includes a first tubular element, a first rod element partially accommodated in the first tubular element, and pressed into the first tubular element when the certain part is mounted for substrate inspection, a second tubular element fixed in the first tubular element, a second rod element partially accommodated in the second tubular element which is inside the first tubular element, and contacting with the first rod element when the first rod element is pressed into the first tubular element, and a fixing mechanism configured to temporarily fix the second rod element in a position so that the second rod element does not contact with the first rod element even when the first rod element is pressed into the first tubular element.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: September 16, 2014
    Assignee: Ricoh Company, Ltd.
    Inventor: Tohru Hasegawa
  • Patent number: 8829933
    Abstract: Various embodiments of a semiconductor apparatus and related methods are disclosed. In one exemplary embodiment, a semiconductor apparatus may include a chip, scribe lanes disposed around the chip, and a probe test logic circuit for conducting a probe test on the chip. The probe test logic circuit is disposed on a portion of the scribe lanes.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: September 9, 2014
    Assignee: SK Hynix Inc.
    Inventors: Tae Sik Yun, Jong Chern Lee
  • Patent number: 8816708
    Abstract: Electronic test system and associated method, including a first and a second connection terminals respectively coupled to two pins of a chip under test, a signal source terminal coupled to a signal generator, a first and a second measurement terminals coupled to a tester, a fifth switch, a seventh switch and a switch circuit which has a first and a fourth front terminals coupled to the signal source terminal, has a first and a fourth back terminals coupled to the first and second connection terminals, and controls conduction between the first front terminal and the first back terminal, as well as conduction between the fourth front terminal and the fourth back terminal. The fifth switch is coupled between the fourth back terminal and the first measurement terminal, and the seventh switch is coupled between the first connection terminal and the second measurement terminal.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: August 26, 2014
    Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Shin-Cheng Chu, Ching-Tsung Chen, Teng-Hui Lee, Chia-Jen Kao
  • Patent number: 8803538
    Abstract: A contactless measuring system having at least one test probe forming part of a coupling structure for the contactless decoupling of a signal running on a signal waveguide, wherein the signal waveguide is designed as a conductor of the electric circuit on a circuit board and as part of an electric circuit. To this end, at least one contact structure is configured and disposed on the circuit board such that said contact structure is galvanically separated from the signal waveguide, forms part of the coupling structure, is displaced completely within the near field of the signal waveguide, and has at least one contact point, which may be electrically contacted by a contact of the test probe.
    Type: Grant
    Filed: July 24, 2008
    Date of Patent: August 12, 2014
    Assignee: Rosenberger Hochfrequenztechnik GmbH & Co. KG
    Inventor: Thomas Zelder
  • Patent number: 8797056
    Abstract: Systems and methods are provided for testing partially completed three-dimensional ICs. Example methods may incorporate one or more of the following features: design for testing (DFT); design for partial wafer test; design for partial probing; partial IC probecards; partial IC test equipment; partial IC quality determinations; partial IC test optimization; and partial test optimization. Other aspects may also be included. Systems and methods incorporating these features to test partially completed three-dimensional ICs may result in saved time and effort, and less scraped material, as the partial device is not built any further when a bad partial device is detected. This results in lower costs and higher yield.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: August 5, 2014
    Assignee: Advantest (Singapore) PTE Ltd
    Inventors: Ajay Khoche, Erik Volkerink
  • Patent number: 8791689
    Abstract: Disclosed is a probe for an oscilloscope comprising a multi-stage transistor amplifier that acts as an impedance transformer. Said amplifier is a d.c.-coupled emitter follower circuit that is composed of bipolar transistors or a d.c.-coupled source follower circuit which is composed of field effect transistors and the successive amplifier elements of which are dimensioned and tuned to each other in such a way that the resulting offset direct voltage between the input and the output is minimal.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: July 29, 2014
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventors: Martin Peschke, Alexander Schild
  • Patent number: 8786302
    Abstract: A test circuit that senses a misaligned probe during a test includes a first power control section that senses voltage levels of a plurality of sensing lines and controls power supplied to a lower circuit section provided below a part of a pad group, and a second power control section that selectively provides an internal voltage in response to a sensing result of the first power control section.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: July 22, 2014
    Assignee: SK hynix Inc.
    Inventor: Hong-Sok Choi
  • Patent number: 8773154
    Abstract: A mounting structure for a continuity testing unit is provided in which the plurality of continuity testing units can easily be mounted to or removed from a test board without using the bolt or the intricately-shaped pin, and which improves the efficiency of restoring the mounting arrangement of the continuity testing units. The mounting structure for a continuity testing unit includes a plurality of parallely-arranged rails arranged at a frame, a joint block arranged on the respective rails and a plurality of continuity testing units each including a plate portion and a pin portion arranged at the plate portion. The joint block includes a plurality of holes into which the pin portion is fitted in a disengageable manner. The plurality of holes is arranged in two lines. The plate portion is placed on the joint blocks on the two adjacent rails.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: July 8, 2014
    Assignee: Yazaki Corporation
    Inventor: Kozo Kogasumi
  • Patent number: 8766658
    Abstract: A probe includes a contact member brought into contact with an object to be tested. Contact particles having conductivity are uniformly distributed in the contact member. A part of the contact particles protrude from a surface of the contact member on the side of the object to be tested. A conductive member having elasticity is placed on a surface of the contact member on the opposite side to the object to be tested. The probe further includes an insulating sheet including a through hole and the contact member is so positioned as to penetrate the through hole. An upper part of the contact member is formed of a conductor which does not include the contact particles. An additional conductor is placed on a surface of the conductor on the side opposite to the object to be tested.
    Type: Grant
    Filed: April 1, 2009
    Date of Patent: July 1, 2014
    Assignee: Tokyo Electron Limited
    Inventor: Shigekazu Komatsu
  • Patent number: 8760187
    Abstract: A first device and a second device can include at least one alignment feature and at least one corresponding constraint. The alignment feature and the constraint can be configured to align the first device and the second device when the alignment feature is inserted into the constraint. The alignment feature and the constraint can be further configured to direct relative movement between the first device and the second device due to relative thermal expansion or contraction between the first device and the second device. The directed relative movement can keep the first device and the second device aligned over a predetermined temperature range.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: June 24, 2014
    Assignee: L-3 Communications Corp.
    Inventor: Eric D. Hobbs
  • Patent number: 8760185
    Abstract: An improved system for capacitive testing electrical connections in a low signal environment. The system includes features that increase sensitivity of a capacitive probe. One feature is a spacer positioned to allow the probe to be partially inserted into the component without contacting the pins. The spacer may be a collar on the probe that contacts the housing of the component, contacts the substrate of the circuit assembly, or both. In some other embodiments, the spacer may be a riser extending beyond the surface of the sense plate that contacts the component, a riser portion of the component, or a combination of both. The spacer improves sensitivity by establishing a small gap between a sense plate of the probe and pins under test without risk of damage to the pins. A second feature is a guard plate of the probe with reduced capacitance to a sense plate of the probe. Reducing capacitance also increases the sensitivity of the probe.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: June 24, 2014
    Inventor: Anthony J. Suto
  • Patent number: 8749259
    Abstract: The invention relates to a full grid cassette for a parallel tester for testing a non-componented printed circuit board, to a spring contact pin for such a full grid cassette and to an adapter for a parallel tester for testing a non-componented printed circuit board.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: June 10, 2014
    Assignee: DTG International GmbH
    Inventors: Andreas Gülzow, Rüdiger Dehmel
  • Patent number: 8742783
    Abstract: A contactor is brought into contact with and separated from an electrode formed on a test target, and includes an elastic member that overlaps with a conductive member having a contact and which urges the contact in a pressing direction. The elastic member is fixed at a predetermined fixed position in a state projecting to the outside of a main body member and the conductive member is electrically connected from the outside of a housing of the main body member of the contactor.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: June 3, 2014
    Assignee: NGK Insulators, Ltd.
    Inventor: Kazuiku Miwa
  • Patent number: 8686358
    Abstract: Methods and apparatus are provided herein for time-resolved analysis of the effect of a perturbation (e.g., a light or voltage pulse) on a sample. By operating in the time domain, the provided method enables sub-microsecond time-resolved measurement of transient, or time-varying, forces acting on a cantilever.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: April 1, 2014
    Assignee: University of Washington through its Center for Commercialization
    Inventors: David Ginger, Rajiv Giridharagopal, David Moore, Glennis Rayermann, Obadiah Reid
  • Patent number: 8680880
    Abstract: An embodiment of a method for testing an integrated circuit comprises a first step for determining at least one of a group selected from whether or not the chuck top receiving the integrated circuit exists near a probe card which transmits and receives electrical signals to and from the integrated circuit, whether or not the integrated circuit is under testing, and whether or not the probe card has a given temperature, and a second step for adjusting power for heating to be supplied to a heating element provided in the probe card according to the determination result in the first step.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: March 25, 2014
    Assignee: Kabushiki Kaisha Nihon Micronics
    Inventors: Hidehiro Kiyofuji, Tetsuya Iwabuchi, Toshiyuki Kudo, Seiji Kanazawa
  • Publication number: 20140070830
    Abstract: A measuring device includes: a probe applying a voltage to an electrode of an element; and a supplying member supplying an insulating liquid to a contact portion between the electrode and the probe via a surface of the probe. Accordingly, the insulating liquid can be securely supplied to the contact portion between the electrode and the probe via the surface of the probe positioned relative to the electrode.
    Type: Application
    Filed: July 26, 2013
    Publication date: March 13, 2014
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Mitsuhiko Sakai, Takeyoshi Masuda, Kenji Hiratsuka
  • Patent number: 8648615
    Abstract: A method of testing a multi-die integrated circuit (IC) can include testing an inter-die connection of the multi-die IC. The inter-die connection can include a micro-bump coupling a first die to a second die. The method can include detecting whether a fault occurs during testing of the inter-die connection. Responsive to detecting the fault, the multi-die integrated circuit can be designated as including a faulty inter-die connection. Also described is an integrated circuit that includes a first die, a second die on which the first die may be disposed, a plurality of inter-die connections coupling the first die to the second die, and a plurality of probe pads, where each probe pad is coupled to at least one of the inter-die connections.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: February 11, 2014
    Assignee: Xilinx, Inc.
    Inventor: Arifur Rahman