Abstract: The disclosure relates to an integrated circuit and associated method and packaged integrated circuit. The integrated circuit comprises a first pad; a second pad; an active element having a node that is capacitively coupled to the first and second pads; a voltage or current source connected to the first pad; and a detection module connected to the second pad and configured to determine an electrical continuity between the second pad and the first pad.

Abstract: A longitudinal differential protection method for a transformer comprises: calculating a corrected parameter of a transformer according to a voltage and electrical parameters of the transformer, wherein the electrical parameters of the transformer comprise a rated capacity of the transformer, and the corrected parameter of the transformer comprise a capacity of the transformer.

Abstract: A measuring system for measuring signals with multiple measurement probes includes a multi probe measurement device having at least two probe interfaces that each couple the multi probe measurement device with at least one of the measurement probes, a data interface that couples the multi probe measurement device to a measurement data receiver, and a processing unit coupled to the at least two probe interfaces that records measurement values via the at least two probe interfaces from the measurement probes. The processing unit is further coupled to the data interface and provides the recorded measurement values to the measurement data receiver that also includes a data interface. The data interface of the measurement data receiver is coupled to the data interface of the multi probe measurement device.

Abstract: A current sensor element includes a resistance section, a first electrically conductive connection section connected to a first end of the resistance section and having a first voltage measurement contact, and a second electrically conductive connection section connected to a second end of the resistance section and having a second voltage measurement contact and a third voltage measurement contact. The first electrically conductive connection section and the second electrically conductive connection section are connectable to feed a current to be measured through the resistance section. The first voltage measurement contact, the second voltage measurement contact, and the third voltage measurement contact are arranged in a way that a first resistance between the first voltage measurement contact and the second voltage measurement contact is smaller than a second resistance between the first voltage measurement contact and the third voltage measurement contact.

Abstract: Disclosed is a probe card for testing a wafer. The probe card includes a substrate and a block including an insulation portion and a conducting portion disposed on the insulation portion. Here, the insulation portion includes a via and a probe pin which comes into contact with an object to be tested. The conducting portion includes a contact point electrically connected to the substrate and a conducting pattern passing through the via and electrically connecting the contact point to the probe pin. A pitch between a plurality of such probe pins is smaller than a pitch between a plurality of such contact points. The block includes a plurality of unit blocks. The plurality of unit blocks each include the insulation portion and the conducting portion, and at least parts of the insulation portions of the unit blocks are arranged while being spaced apart from each other.

Abstract: An inspection device for inspecting an inspection target substrate includes a probe card, a tester, a plurality of conductive lines, and a resistor. The probe card has probes to be in contact with the inspection target substrate. The tester is configured to transmit and receive electric signals for an inspection to and from the inspection target substrate through the probes. The conductive lines electrically connect the probe card with the tester, and at least a part of the conductive lines is electrically connected to the probes. The resistor is formed at the probe card and serves as an electrical resistor. The tester is further configured to measure a resistance of the resistor based on the electric signals transmitted and received through the conductive lines.

Abstract: A measuring system for measuring signals with multiple measurement probes comprises a multi probe measurement device comprising at least two probe interfaces that each couple the multi probe measurement device with at least one of the measurement probes, a data interface that couples the multi probe measurement device to a measurement data receiver, and a processing unit coupled to the at least two probe interfaces that records measurement values via the at least two probe interfaces from the measurement probes, wherein the processing unit is further coupled to the data interface and provides the recorded measurement values to the measurement data receiver, and a measurement data receiver comprising a data interface, wherein the data interface of the measurement data receiver is coupled to the data interface of the multi probe measurement device.

Abstract: A probe holder holds contact probes each of which comes in contact with one electrode of a contact target on one end portion side in a longitudinal direction. The probe holder includes a plate in which holder holes configured to hold the respective contact probes are formed and penetrate the probe holder. Each of the holder holes includes a first hole portion disposed on one end of a penetrating direction and extending in the penetrating direction, a large diameter portion connected to the first hole portion and extending in the penetrating direction, the large diameter portion being larger than a diameter of the first hole portion, and a second hole portion disposed on another end of the penetrating direction, connected to the large diameter portion, and extending in the penetrating direction, the second hole portion being smaller than a diameter of the large diameter portion.

Abstract: An example apparatus includes an input buffer coupled to an input terminal, wherein the input buffer is configured to provide an input signal based on a voltage received at the input terminal, a test terminal configured to receive a probe signal, and a power supply terminal configured to receive an external supply voltage. The example apparatus further includes a test logic circuit configured to, in response to the probe signal indicating a test and an external supply voltage detection signal having a value indicating detection of the external supply voltage, initiate a probe contact detection test. During the initiate a probe contact detection test, the test logic circuit is configured to receive the input signal and to provide an output signal having a value based on the input signal.

Abstract: A display substrate and a test method thereof are disclosed. The display substrate includes a test wire connected to a first gate driving circuit and a second gate driving circuit; a high vertical alignment process test pad disposed on at least one side of the test wire; a first array test pad electrically connected to the first gate driving circuit and connected to the test wire to form a first connection node; a second array test pad electrically connected to the second gate driving circuit and connected to the test wire to form a second connection node; and a switch unit formed between the first connection node and the second connection node for controlling the test wire to connect or disconnect.

Abstract: A display device includes a display panel including a first and a second non-display area, a main active area, and a sub active area, wherein the active areas each include a matrix of sub-pixels; a data driver in the first non-display area to provide image data to the matrices of sub-pixels; a main gate driver in the second non-display area to provide a corresponding gate signal to each sub-pixel in the main active area; a sub gate driver in the second non-display area to provide a corresponding gate signal to each sub-pixel in the sub active area; an auto-probe test pad in the non-display area for transmitting a first start signal received from an auto-probe signal generating device to one of the main gate driver and the sub gate driver while testing the display panel; and a signal transmission circuit connecting the main gate driver and the sub gate driver.

Abstract: A probe card and a testing method are disclosed herein. The probe card includes a plurality of probe sets arranged as a testing unit. The testing unit is configured to test a plurality of dies in a test region on a wafer, and to move m unit along a first direction and n unit along a second direction when the test complete so as to test the next test region, in which m and n are integers.

Abstract: Package-on-Package (PoP) structures and methods of forming the same are disclosed. In some embodiments, a method of forming a PoP structure may include: plating at least one through-assembly via (TAV) over a peripheral region of a conductive seed layer; forming a dam member over a central region of the conductive seed layer; and placing a die over the central region of the conductive seed layer. The dam member may be laterally separated from the die and disposed between the die and the at least one TAV. The method may further include encapsulating the die, the dam member, and the at least one TAV in a polymer material.

Abstract: The various embodiments described herein include systems, methods and/or devices used to package non-volatile memory. In one aspect, the method includes: (1) selecting, from a set of non-volatile memory die, a plurality of non-volatile memory die on which one or more tests have been deferred until after packaging, the selecting in accordance with wafer positions of the plurality of non-volatile memory die and statistical die performance information corresponding to the wafer positions; and (2) packaging the selected plurality of non-volatile memory die. In some embodiments, after said packaging, the method further includes performing a set of tests on the plurality of non-volatile memory die to identify respective units of memory within the plurality of non-volatile memory die that meet predefined validity criteria, wherein the set of tests performed include at least one of the deferred one or more tests.

Abstract: A probe structure includes a sleeve, a needle shaft and an elastic member. The needle shaft is accommodated in the sleeve and includes a first groove for accommodating the elastic member. The probe structure further includes a conductive component installed at the bottom of the sleeve and having an end connected into the first groove, and a second groove, so that the elastic member is situated in the first and second grooves. When the needle shaft is pressed and moved, the inner wall of the second groove is contacted with an outer sidewall of the conductive component to define a second conductive channel. With the two conductive channels, the effects of maintaining stable current transmission efficiency, reducing poor contact or disconnection, and providing good structural stability are achieved.

Abstract: Various exemplary embodiments provide probes, systems and methods for measuring an effective electrical resistance/resistivity with high sensitivity. In one embodiment, the measuring system can include an upper probe set and a similar lower probe set having a sample device sandwiched there-between. The device-under-test (DUT) samples can be sandwiched between two conductors of the sample device. Each probe set can have an inner voltage sense probe coaxially configured inside an electrically-isolated outer current source probe that has a large contact area with the sample device. The measuring system can also include a computer readable medium for storing circuit simulations including such as FEM simulations for extracting a bulk through-plane electrical resistivity and an interface resistivity for an effective electrical z-resistivity of the DUT, in some cases, having sub-micro-ohm resistance.

Abstract: An apparatus for measuring electrical parameters for an electrical system measures a first and second parameters of the electrical system between connections to the electrical system. A processor determines a third electrical parameter of the electrical system as a function of the first parameter and the second parameter. Wireless communication is provided between components of the apparatus.

Abstract: A probing apparatus for semiconductor devices provides a primary circuit board and a signal-adapting board positioned on the primary circuit board. The primary circuit board includes an inner area having a plurality of first contacts and an outer area having a plurality of first terminals and second terminals, and the first contacts are electrically connected to the first terminals via first conductive members in the primary circuit board. The signal-adapting board includes a plurality of second contacts electrically connected to the first contacts via second conductive members in the signal-adapting board.

Abstract: The invention relates to a test contact arrangement (15) for testing semiconductor components, comprising at least one test contact (10) which is arranged in a test contact frame (13) and is designed in the type of a cantilever arm and which has a fastening base (12) and a contact arm (30) which is provided with a contact tip (11) and which is connected to the fastening base, wherein the fastening base is inserted with a fastening projection (16) thereof into a frame opening (14) of the test contact frame in such a manner that a lower edge (17) of the fastening projection is essentially aligned flush with a lower side (18) of the test contact frame.

Abstract: A method for cleaning a contact pad of a microstructure or device to be tested when it is in electric contact with a measure apparatus, being obtained by electrically contacting a flexible probe with said contact pad. The method includes mechanically engaging a free end of the flexible probe in a manner that sticks the free end in the pad; and laterally flexing, by a tip charge, the flexible probe in a manner that keeps the free end stuck in the pad, so as to locally dig into a covering layer of the pad and realize a localized crushing thereof.

Abstract: A display apparatus includes a display panel including a plurality of pixels, a plurality of first lines and a plurality of second lines, a plurality of first pads electrically connected to the first lines, respectively, where the first pads are divided into a first group and a second group, a plurality of pads including a second pad, a third pad, a fourth pad and a fifth pad, a first shorting bar configured to be connected to the first group of the first pads and to be connected between the second pad and the fourth pad during a test process of the first lines, and a second shorting bar configured to be connected to the second group of the first pads and to be connected between the third pad and the fifth pad during the test process of the first lines.

Abstract: A probe for inspecting electronic components, and more particularly, to a probe for inspecting electronic components, which connects a target electronic component to an inspection apparatus to inspect defects of the target electronic component. The probe for inspecting electronic components includes: a cylinder body having a cylindrical shape; a piston body reciprocating between an inside and an outside of the cylinder body; a spring surrounding an outer circumference of the cylinder body and the piston body, and forcing a part of the piston body to resiliently move out of the cylinder body when inserted into the cylinder body; a probing unit extending from the cylinder body to be brought into contact with a target electronic component to be inspected as to flow of electric current therethrough; and a contact unit extending from the piston body to be connected to an inspection apparatus for inspecting the target electronic component.

Abstract: The various embodiments described herein include systems, methods and/or devices used to packaging non-volatile memory. In one aspect, the method includes, selecting, from a set of non-volatile memory die, a plurality of non-volatile memory die on which predefined die-level and sub-die level tests have been deferred until after packaging, in accordance with predefined criteria and predefined statistical die performance information corresponding to the set of non-volatile memory die. The method further includes packaging the selected plurality of non-volatile memory die into a memory device. After said packaging, the method further includes performing a set of tests on the plurality of non-volatile memory die in the memory device to identify respective units of memory within the non-volatile memory die in the memory device that meet predefined validity criteria, wherein the set of tests performed include the deferred predefined die-level and sub-die level tests.

Abstract: A probe module for testing an electronic device comprises at least two contacts, each contact including a first end portion extending in a first direction along a first line, a second end portion extending linearly in a second direction opposite from the first direction and along a second line, and a third curved portion extending between the first end portion and the second end portion. The first line is spaced apart from and in parallel with the second line, and the at least two contacts are spaced apart from each other in a direction perpendicular to the first line and the second line. Methods for making such a probe module are also taught.

Abstract: A probing device for a TFT-LCD substrate, which includes a device body, a device body, a circuit board mounted on the device body, a plurality of motors mounted on the device body, and a plurality of probe pins respectively mounted to the motors. The motors and the probe pins are arranged in a one-to-one corresponding manner. The circuit board includes a programmable logic controller and a man-machine interface terminal electrically connected to the programmable logic controller. The plurality of motors and the plurality of probe pins are electrically connected to the programmable logic controller. The plurality of probe pins is set at locations corresponding to locations of panel inspection signal input pads of TFT substrates of various sizes. The programmable logic controller uses the motors to control the elevation and lowering of the probe pins.

Abstract: A device tester is provided. The device tester includes a probe card and a substrate coupled to the probe card. The substrate has a plurality of layers for routing a signal. An integrated circuit is coupled to the substrate. The integrated circuit is operable to transmit an input signal received from a testing apparatus to a device under test through the substrate to a signal probe. The signal probe is further operable to receive a test signal from the device under test in response to the input signal, wherein the integrated circuit is operable to amplify the test signal, and transmit the amplified test signal to the testing apparatus.

Abstract: An inspecting method for an object to be inspected is provided to bring probes of a probe card into electrical contact with a predetermined number of devices of target devices of the object at a time to inspect electrical characteristics of the target devices by moving a mounting table for mounting thereon the object under the control of a control unit. Upon completion of the inspection of the target devices, if inspection errors have occurred in specific devices of the target devices in a regular pattern, the target devices are re-examined, and when the re-examination is carried out, a contact position between the probe card and the object is displaced from a contact position in a previous inspection by a distance of at least one device to inspect electrical characteristics of the number of devices of the target devices at a time.

Abstract: The terminals of a device under test are temporarily electrically connected to corresponding contact pads on a load board by a series of electrically conductive pin pairs. The pin pairs are held in place by an interposer membrane that includes a top contact plate facing the device under test, a bottom contact plate facing the load board, and a vertically resilient, non-conductive member between the top and bottom contact plates. Each pin pair includes a top and bottom pin, which extend beyond the top and bottom contact plates, respectively, toward the device under test and the load board, respectively. The top and bottom pins contact each other at an interface that is inclined with respect to the membrane surface normal. When compressed longitudinally, the pins translate toward each other by sliding along the interface. The sliding is largely longitudinal, with a small and desirable lateral component determined by the inclination of the interface.

Abstract: A method and apparatus are provided for transmission/reception of signals between automatic test equipment (ATE) and a device under test (DUT). A probe card has a plurality of associated proximate active probe integrated circuits (APIC) connected to a plurality of probes. Each APIC interfaces with one or more test interface points on the DUT through probes. Each APIC receives and processes signals communicated between the ATE and the DUT. Low information content signals transmitted from the ATE are processed into high information content signals for transmission to the probe immediately adjacent the APIC, and high information content or time critical signals received by the APIC from the DUT are transmitted as low information content signals to the ATE. Because the APIC is immediately adjacent the probe there is minimum loss or distortion of the information in the signal from the DUT.

Abstract: A multifunction test instrument probe includes a housing having a hollow bore with an open end. A clamp plunger is carried in the hollow bore, with a first end including a thumb press, and a second end including an alligator clamp having a pair of jaws, with a compression spring normally biasing the thumb press away from the housing, and normally biasing the alligator clamp substantially within the hollow bore proximate the open end. A point plunger is also carried in the bore, with a first end including a thumb press, and a second end terminating in a point, with a second compression spring normally biasing the thumb press away from the housing, and biasing the point within the hollow bore proximate the open end.

Abstract: A method is disclosed for the measurement of a power device in a prober, which serves the examination and testing of such components. In the process, a power device is held by a chuck, and at least one electric probe is held by a probe holder, and optionally, the power device or the probe is positioned each relative to the other using a positioning device with an electrical drive, and contacts the power device. At the same time, an electrical connection remains between the probe to a signal unit with which a power signal is sent out or received, is blocked and only unblocked when it is determined that the contact between probe 26 and contact area is established.

Abstract: A testing apparatus for measuring the material properties of solder balls includes a frame and a chuck base moveable in X, Y, Z dimensions, relative to the frame. A probe tip is fixed to the frame. A measuring device is mounted to the frame and maintains a spacing with relationship to the probe tip and which has an initial, known height above the chuck base.

Abstract: A retention arrangement that includes one or more templates for securing and aligning probes for testing a device under test.

Abstract: Detecting misalignment of test probes with component carriers in an automated test system is taught. Automated test systems for testing electronic components can have electronic components held in component carriers in preparation for testing. Testing can include moving test probes through openings provided in the component carrier to contact the electronic components held therein. Aspects of disclosed implementations use force feedback from the test probes to determine if the test probes have successfully contacted the electronic component without, for example, contacting the component carrier.

Abstract: Apparatus and methods for identifying a signal on a printed circuit board (‘PCB’) under test, including an integrated circuit mounted on the PCB, the integrated circuit having a test signal generator that transmits a test signal to an output pin of the integrated circuit, with the output pin connected to a test point on the PCB; the integrated circuit also having signal identification logic that inserts into the test signal, an identifier of the signal; a test probe in contact with the test point; and a signal-identifying controller that receives the test signal and the identifier from the test probe and displays, in dependence upon the identifier, the identity of the signal.

Abstract: A semiconductor wafer includes semiconductor chips divided by a dicing line, one of the semiconductor chips including terminals of an identical potential; a wiring located on the dicing line, and electrically connecting the terminals to each other; and a pad electrically connected through the wiring to the terminals, wherein the pad is located entirely on the semiconductor chip and is not present on the dicing line.

Abstract: A circuit configuration monitors the electrical insulation of an electrically conductive part in relation to a first pole and a second pole of an electrical power network for example, an electrical drive network in a hybrid vehicle. The circuit configuration is characterized in that between the electrically conductive part and the two poles, a voltage divider having at least two resistors is arranged in each case. A measuring unit is associated with each of the two voltage dividers and provided for measuring a partial voltage, which drops via at least one of the resistors. A switch unit is associated each with the two voltage dividers and is provided for alternately bypassing at least one of the resistors.

Abstract: In one embodiment, a method for testing a plurality of singulated semiconductor die involves 1) placing each of the singulated semiconductor die on a surface of a die carrier, 2) mating an array of electrical contactors with the plurality of singulated semiconductor die, and then 3) performing electrical tests on the plurality of singulated semiconductor die, via the array of electrical contactors.

Abstract: The present disclosure provide a probe card for wafer level testing. The probe card includes a space transformer having a power line, a ground line, and signal lines embedded therein, wherein the space transformer includes various conductive lines having a first pitch on a first surface and a second pitch on a second surface, the second pitch being substantially less than the first pitch; a printed circuit board configured approximate the first surface of the space transformer; and a power plane disposed on the first surface of the space transformer and patterned to couple the power line and the ground line of the space transformer to the printed circuit board.

Abstract: A probe for a measurement instrument comprises an input terminal configured to receive an input signal from a device under test (DUT), an output terminal configured to transmit an output signal to a measurement instrument, and a clamping circuit disposed in a signal path between the input terminal and the output terminal and configured to clamp an internal probe signal between an upper clamping threshold and a lower clamping threshold to produce the output signal, wherein the clamping circuit operates with substantial gain and amplitude linearity throughout a range between the upper clamping threshold and the lower clamping threshold.

Abstract: A contact structure for inspection that is installed on a bottom surface of a circuit board includes a ground conductor that is grounded; an elastic contact member that is brought into contact with an inspection target object; and a conductive line that electrically connects the circuit board and the elastic contact member. Here, the elastic contact member may be provided on a bottom surface of the ground conductor that is grounded. The elastic contact member may include an insulating layer, a wiring layer, a contactor and an elastic body provided at a position corresponding to the contactor. The elastic body provides the elastic contact member with elasticity when the contactor is brought into contact with an electrode. The elastic contact member is provided in parallel with the ground conductor. The wiring layer and the ground conductor form a microstrip line.

Abstract: A measurement apparatus for surface analysis carried out in a gaseous environment such as air comprises a measurement device capable of measuring a contact potential difference between a probe and a surface, and a light source that triggers photoelectric emission from a sample. The apparatus may operate in “dual” photoemission and contact potential difference (CPD) measurement modes.

Abstract: A switch probe for use in a substrate inspection device to inspect a substrate includes a first tubular element, a first rod element partially accommodated in the first tubular element, and pressed into the first tubular element when the certain part is mounted for substrate inspection, a second tubular element fixed in the first tubular element, a second rod element partially accommodated in the second tubular element which is inside the first tubular element, and contacting with the first rod element when the first rod element is pressed into the first tubular element, and a fixing mechanism configured to temporarily fix the second rod element in a position so that the second rod element does not contact with the first rod element even when the first rod element is pressed into the first tubular element.

Abstract: Various embodiments of a semiconductor apparatus and related methods are disclosed. In one exemplary embodiment, a semiconductor apparatus may include a chip, scribe lanes disposed around the chip, and a probe test logic circuit for conducting a probe test on the chip. The probe test logic circuit is disposed on a portion of the scribe lanes.

Abstract: Electronic test system and associated method, including a first and a second connection terminals respectively coupled to two pins of a chip under test, a signal source terminal coupled to a signal generator, a first and a second measurement terminals coupled to a tester, a fifth switch, a seventh switch and a switch circuit which has a first and a fourth front terminals coupled to the signal source terminal, has a first and a fourth back terminals coupled to the first and second connection terminals, and controls conduction between the first front terminal and the first back terminal, as well as conduction between the fourth front terminal and the fourth back terminal. The fifth switch is coupled between the fourth back terminal and the first measurement terminal, and the seventh switch is coupled between the first connection terminal and the second measurement terminal.

Abstract: A contactless measuring system having at least one test probe forming part of a coupling structure for the contactless decoupling of a signal running on a signal waveguide, wherein the signal waveguide is designed as a conductor of the electric circuit on a circuit board and as part of an electric circuit. To this end, at least one contact structure is configured and disposed on the circuit board such that said contact structure is galvanically separated from the signal waveguide, forms part of the coupling structure, is displaced completely within the near field of the signal waveguide, and has at least one contact point, which may be electrically contacted by a contact of the test probe.

Abstract: Systems and methods are provided for testing partially completed three-dimensional ICs. Example methods may incorporate one or more of the following features: design for testing (DFT); design for partial wafer test; design for partial probing; partial IC probecards; partial IC test equipment; partial IC quality determinations; partial IC test optimization; and partial test optimization. Other aspects may also be included. Systems and methods incorporating these features to test partially completed three-dimensional ICs may result in saved time and effort, and less scraped material, as the partial device is not built any further when a bad partial device is detected. This results in lower costs and higher yield.

Abstract: Disclosed is a probe for an oscilloscope comprising a multi-stage transistor amplifier that acts as an impedance transformer. Said amplifier is a d.c.-coupled emitter follower circuit that is composed of bipolar transistors or a d.c.-coupled source follower circuit which is composed of field effect transistors and the successive amplifier elements of which are dimensioned and tuned to each other in such a way that the resulting offset direct voltage between the input and the output is minimal.

Abstract: A test circuit that senses a misaligned probe during a test includes a first power control section that senses voltage levels of a plurality of sensing lines and controls power supplied to a lower circuit section provided below a part of a pad group, and a second power control section that selectively provides an internal voltage in response to a sensing result of the first power control section.

Abstract: A mounting structure for a continuity testing unit is provided in which the plurality of continuity testing units can easily be mounted to or removed from a test board without using the bolt or the intricately-shaped pin, and which improves the efficiency of restoring the mounting arrangement of the continuity testing units. The mounting structure for a continuity testing unit includes a plurality of parallely-arranged rails arranged at a frame, a joint block arranged on the respective rails and a plurality of continuity testing units each including a plate portion and a pin portion arranged at the plate portion. The joint block includes a plurality of holes into which the pin portion is fitted in a disengageable manner. The plurality of holes is arranged in two lines. The plate portion is placed on the joint blocks on the two adjacent rails.