Abstract: Embodiments of the present application provide a time offset method and device for a test signal. When a signal source sends a test signal to a DUT on a test platform, the offset device can determine a time delay caused by impedance matching of the test signal to the DUT at the upper side of each test location, and conduct time offset for TCK signals sent by the signal source to different DUTs according to the time delay.

Abstract: The embodiments relate to array substrate technologies. Provided is an array substrate and a display panel, the array substrate includes a display region and a non-display region. A first bonding-lead part, a second bonding-lead part and a third bonding-lead part are arranged in sequence in a bonding area of the non-display region. A first side of the first bonding-lead part is used for connecting with a gate driver unit test wiring, and a second side of the first bonding-lead part is used for connecting with a gate driver signal wiring. A width of the first bonding-lead part is smaller than that of the second bonding-lead part, such that a wiring area is formed on the first side of the first bonding-lead part and/or the second side of the first bonding-lead part, thereby providing sufficient wiring space for the GOA unit test wiring and the GOA signal wiring.

Abstract: A wafer inspection method and inspection apparatus are provided. On a wafer having layout lines connecting electrode points of individual dies in series, the dies within a matrix range are inspected one after another in turn in a column/row control means by a first switch group and a second switch group of a probe card, so that each die is selectively configured in a test loop of a test process by turning on/off of a corresponding switch. Thus, after inspection of a die under inspection (a selected die) within the matrix range is complete, the column/row control means is used to switch to a next die to achieve fast switching. Accordingly, for the inspection procedure of each die within the matrix region, a conventional procedure of moving one after another in turn can be eliminated, significantly reducing the total test time needed and enhancing inspection efficiency.

Abstract: Disclosed are dielectric cavity arrays with cavities formed by pairs of dielectric tips, wherein the cavities have low mode volume (e.g., 7*10?5?3, where X is the resonance wavelength of the cavity array), and large quality factor Q (e.g., 106 or more). Applications for such dielectric cavity arrays include, but are not limited to, Raman spectroscopy, second harmonic generation, optical signal detection, microwave-to-optical transduction, and as light emitting devices.

Abstract: A lighting device contains a first circuit board and a second circuit board. The first circuit board has one or more connecting sections having overall at least two contact areas. The second circuit board has an opening through which the connecting section of the first circuit board can extend. At least two contact elements, which are electrically connected to conductive tracks of the second circuit board, are arranged on the second circuit board. Each contact element has a contact region by which the contact element butts against one of the contact areas of the first circuit board. As a result, an electrical connection is produced between the two circuit boards.

Abstract: A probe card test apparatus including an insulating substrate; a conductive pattern on the insulating substrate; and a plurality of device under test (DUT) units on the conductive pattern, wherein each of the DUT units includes a merged-probe opening, a probe opening, and a detector in parallel, and an isolator surrounding the merged-probe opening, the probe opening, and the detector.

Abstract: A waterproof button module includes a pressing element, a circuit board, an adhesive layer, and an elastic layer sequentially stacked. The adhesive layer is attached to the circuit board and the elastic layer. The adhesive layer includes a first opening, and the elastic layer includes a second opening. The first opening is aligned with the second opening and exposes a part of the rear surface of the circuit board. The adhesive layer has an annular zone adjacent to and surrounding the first opening. The annular zone directly contacts the circuit board. The waterproof button module further includes an electric-connection assembly and a switch. The electric-connection assembly is electrically connected to the circuit board, and passes through the first opening and the second opening. The switch is electrically connected to the circuit board, and has a button. In addition, an electronic device including the waterproof button module is disclosed.

Abstract: A prober head to interface an E-testing apparatus to a device under test, which may be an unpackaged die, for example. In some embodiments, the prober head includes an array of conductive pins, each of the pins extending outwardly from a first pin end anchored to a substrate. At least a partial length of each of the pins is coated with a hydrophobic monolayer. The conductive pins may be composite metal wires including a core metal encased by one or more peripheral metal. At a tip of the pins, opposite the first pin end anchored to the substrate, the peripheral metals are recessed from the core metal. In further embodiments, the hydrophobic monolayer is disposed on an outer surface of the peripheral metals, but is substantially absent from a surface of the core metal exposed at the tip.

Abstract: A cantilever probe head includes a support ring associated with a PCB board and a plurality of contact probes, protruding from the support ring in a cantilever manner and being held by a support associated with the support ring. Each contact probe has a rod-like body having a longitudinal axis inclined with respect to a reference plane corresponding to a plane of a wafer of devices under test by the cantilever probe head, as well as at least one first end portion, provided in a first probe section protruding from the support in the direction of the wafer of devices under test, the first end portion being bent with respect to the longitudinal axis starting from a bending point and ending with a contact tip of the contact probe able to abut onto a contact pad of a device under test of the wafer.

Abstract: A display device including a first substrate including a display area and a non-display area, a circuit film connected to the first substrate, a printed circuit board (PCB) connected to the circuit film, and a first inspection pad, a second inspection pad, and a third inspection pad located in the non-display area and a bridge configured to electrically connect the first inspection pad, the second inspection pad, and the third inspection pad. The circuit film includes a first line electrically connected to the first inspection pad, a second line electrically connected to the second inspection pad, a third line electrically connected to the third inspection pad, and a branch point configured to branch at least one line from the first line, the second line, and the third line into two sub-lines. The PCB includes a test pad unit connected to the first line, the second line, and the third line.

Abstract: An image test system includes a test assembly and an image capture card. The test assembly is provided for capturing test signals from test objects, and incudes a first transmission interface, a second transmission interface, and an interface conversion circuit. The interface conversion circuit is connected with the first transmission interface, and converts signal transmission forms of the test signals. The second transmission interface is connected with the interface conversion circuit. Besides, the image capture card is provided for connecting with the second transmission interface, and captures image data from the test signals.

Abstract: A handler has a processing unit, first and second driving units, a holding unit and a crank unit. The processing unit processes a device provided in a placement area. The first driving unit moves the processing unit along a movement path. The holding unit holds the device and is attached to the crank unit. The second driving unit moves the holding unit. The crank unit comprises a first portion to which the holding unit is attached and a second portion connected to the first portion. The handler is allowed to be in a first posture for causing the holding unit to be located inside the movement path and to be in a second posture for causing the processing unit to be located in vicinity of the device.

Abstract: A probe head and methods of testing a device using a probe head are provided. The probe head includes a first end connected to a first substrate. The first substrate is configured to be connected to a test head. The probe head also includes second end having a first inner recess surrounded by a first protrusion and a first plurality of probe needles connected to the first protrusion.

Abstract: A test apparatus includes a probe card and a tester. The probe card has a plurality of regions corresponding to dies of a wafer, respectively. The probe card includes a tray having a first region with a lens and a second region without a lens. The tester is configured to generate a drive control signal for moving the tray in a first direction or a second direction to locate the first region or the second region at a position facing the dies.

Abstract: A method for detecting errors of a first field-programmable gate array (FPGA) program includes: receiving, by a monitoring program executed on a processor connected to an FPGA on which the first FPGA program is executed, a signal value read out from the first FPGA program; and comparing, by the monitoring program executed on the processor, the signal value to a reference value from a source other than the first FPGA program in order to detect errors of the first FPGA program.

Abstract: A wafer testing system may comprise a chuck, a wafer carrier, a cathode plate, and a probe card. The chuck may be configured to hold the wafer carrier. The wafer carrier may be configured to hold a wafer on a surface of the wafer carrier, wherein the surface of the wafer carrier comprises one or more contact features protruding from the surface of the wafer carrier. The cathode plate may be configured to provide an electrical connection between the wafer carrier and the probe card, wherein a portion of a surface of the cathode plate is configured to be disposed on the one or more contact features of the wafer carrier. The probe card may be configured to test, using one or more probes associated with the probe card, the wafer when the wafer is on the surface of the wafer carrier.

Abstract: A high-frequency testing probe is disclosed. The probe includes a layered probe substrate having a first and second PCB, as well as first and second conducting traces disposed on opposite sides of the substrate. The probe substrate has an ungrounded differential region including two probe tips coupled to the traces, a grounded differential region, and a decoupled differential region including two probe connectors coupled to the traces. The probe also includes a ground plane between the two PCBs and between the two traces in the decoupled and grounded differential regions. In the ungrounded differential region, the first and second traces form a first differential transmission pair having a differential impedance. In the grounded differential region, the first and second traces form a second differential transmission pair having the differential impedance. The probe connectors are configured to couple to one of a vector network analyzer and a time domain reflectometer.

Abstract: An illustrative method disclosed herein includes measuring at least one electrical-related parameter of a doped semiconductor material by simultaneously irradiating at least a portion of an upper surface of the doped semiconductor material, urging a conductive tip of a cantilever beam probe into conductive contact with the upper surface of the irradiated portion of the doped semiconductor material, and generating an electrical current that flows through the doped semiconductor material, through a measurement device that is operatively coupled to the cantilever beam probe and through the cantilever beam probe, wherein the measurement device measures the at least one electrical-related parameter of the doped semiconductor material.

Abstract: A stiffener of a probe card includes: a body plate arranged between a test head and a printed circuit board (PCB) of the probe card, wherein the test head is configured to apply a test signal to an object, and the PCB is configured to receive the test signal; a plurality of ribs radially extending from the body plate; an inner rim configured to surround the body plate to connect middle portions of the ribs with each other; and a plurality of contact members arranged on upper surfaces of at least two ribs among the ribs, and configured to make contact with the test head.

Abstract: A display device comprises a light emitting base layer, a transporting layer, a metal layer and a packaging layer that are sequentially stacked; the transporting layer comprising a conductive lead wire and a test pin; the metal layer comprising a plurality of metal blocks arranged in an array, each of the metal blocks being electrically connected to the test pin through the conductive lead wire; and the packaging layer being used for blocking outside moisture from contacting the metal layer, by testing the electric resistance of the metal block electrically connected to the test pin, determining the moisture blocking effect of the area of the packaging layer corresponding to the metal block. The moisture blocking effect of the area of packaging layer corresponding to the metal block can be determined, and the area where the moisture blocking effect of the packaging layer is poor can be accurately determined.

Abstract: An integrated substrate for testing a semiconductor wafer and a method are provided. The integrated substrate includes a first redistribution structure including a fine redistribution circuitry, a plurality of testing tips disposed on a first surface of the first redistribution structure and electrically connected to the fine redistribution circuitry to probe the semiconductor wafer, a second redistribution structure including a coarse redistribution circuitry and disposed over a second surface of the first redistribution structure opposite to the first surface, and a plurality of conductive joints interposed between the coarse redistribution circuitry and the fine redistribution circuitry to provide electrical connections therebetween. A layout density of the fine redistribution circuitry is denser than that of the coarse redistribution circuitry.

Abstract: A display device includes a substrate including a display area and a peripheral area, an inspection terminal in the peripheral area and configured to transmit an inspection signal to the display area, an inspection wiring that connects the display area to the inspection terminal, a semiconductor resistor connected to each of the inspection terminal and the inspection wiring, an insulating film, and a planarization layer including a terminal opening. The planarization layer covers at least one end of the inspection terminal and the inspection terminal exposes a portion of the inspection terminal. The semiconductor resistor is below the inspection terminal, with an insulating film therebetween, and is in contact with the inspection terminal through a first contact hole defined in the insulating film. A portion of the semiconductor resistor is overlapped by the terminal opening.

Abstract: Presented embodiments facilitate efficient and effective access to a device under test. In one embodiment, a test system comprises: a primitive configured to control testing of a device under test (DUT) and a device interface board (DIB). The device interface board comprises: a loadboard, an environmental control component and a device under test access interface. The loadboard is configured to selectively couple with a device under test and a primitive. The environmental control component is configured to control environmental conditions. The device under test access interface is configured to allow robotic manipulation of the device under test. The manipulation can include selectively coupling the device under test to the loadboard. The device under test access interface can be configured to enable unobstructed access for robotic manipulation of the device under test.

Abstract: In one embodiment, the present invention includes an interface assembly for a vertical probe contactor. The interface assembly comprises a base board, a mounting board, a depth adjust plate, and an interface apparatus. The depth adjust plate is between the base board and the mounting board, and the interface apparatus is mounted to the mounting board. The interface apparatus is configured to receive the vertical probe contactor through an opening in the base board and a corresponding opening in the depth adjust plate. A thickness of the depth adjust plate defines a vertical distance between a wafer side of the base board and a plurality of probe tips of the vertical probe contactor.

Abstract: A test-probe tip having a tip component, a resistive element, and a compliance member. The tip component is configured to electrically connect to a device under test at a first end of the tip component. The resistive element is electrically connected to a second end of the tip component along a signal-flow axis. The resistive element is configured to provide electrical impedance to an electrical signal passing through the resistive element. The compliance member is configured to allow movement of the tip component in a first direction when a mechanical force applied to the tip component in the first direction and to cause movement of the tip component in an opposite, second direction when the mechanical force applied to the tip component is removed or reduced. Architectures for the resistive element are also described.

Abstract: The present disclosure provides a probe card device and a conductive probe thereof. The conductive probe includes a metallic pin, an outer electrode, and a dielectric layer. The metallic pin includes a middle segment, a first connecting segment and a second connecting segment respectively extending from two opposite ends of the middle segment, and a first contacting segment and a second contacting segment respectively extending from the first connecting segment and second contacting segment along two opposite directions away from the middle segment. At least part of the outer electrode corresponds in position to the middle segment and is arranged adjacent to the first connecting segment. The dielectric layer is sandwiched between and entirely separates the metallic pin and the outer electrode, so that the outer electrode, the dielectric layer, and the metallic pin are jointly configured to generate a capacitance effect.

Abstract: A multilayer circuit board 3a includes a core substrate 7; a resin section 8, which covers the side surface and a lower surface 12 of the core substrate 7; and a plurality of metal pins 11, which are disposed within the resin section 8. The core substrate 7 includes a ceramic multilayer section 9, which is disposed on the mother-substrate side of the core substrate 7; and a resin multilayer section 10, which is stacked on a main surface 13 on a side of the ceramic multilayer section 9, the side being opposite to the mother substrate. The resin section 8 includes the plurality of metal pins 11, and a through-hole 22, which extends through the resin section 8 in its thickness direction. A fastening part 24 penetrates the through-hole 22, to mount the multilayer circuit board 3a on the mother substrate.

Abstract: A testing arrangement for testing Integrated Circuit (IC) interconnects is provided. In an example, the testing arrangement includes a substrate, and a first interconnect structure. The first interconnect structure may include a first member having a first end to attach to the substrate and a second end opposite the first end, and a second member having a first end to attach to the substrate and a second end opposite the first end. In some examples, the second end of the first member and the second end of the second member are to contact a second interconnect structure of a IC device under test, and the first end of the first member and the first end of the second member are coupled such that the first member and the second member are to transmit, in parallel, current to the second interconnect structure of the IC device under test.

Abstract: The embodiments of the present disclosure relate to a packaging method, a panel assembly, a wafer package and a chip package. The semiconductor device packaging method includes: providing at least one wafer including a first surface and a second surface opposite to each other and a side surface connecting the first surface and the second surface, the first surface being an active surface; forming a connection portion on the side surface of the at least one wafer around the wafer, the wafer and the connection portion forming a panel assembly, the connection portion includes a third surface on the same side of the first surface of the wafer and a fourth surface on the same side as the second surface of the wafer, the third surface and the first surface forming a to-be-processed surface of the panel assembly. The packaging method of the embodiments of the present disclosure may improve packaging efficiency and utilization of a wafer.

Abstract: Disclosed is a guide plate for a probe card guiding a probe pin of the probe card and a manufacturing method thereof, and the probe card having the same. Particularly, the guide plate and a manufacturing method thereof, and the probe card securing reliability of the probe card are intended to be provided, wherein probe pins are easily inserted into the guide plate, and pin insertion holes into which the probe pins are inserted are precisely formed in a small size.

Abstract: The present application provides a display control method and device, and relates to the display field. The method comprises: determining a beam shaping parameter according to to-be-displayed content and a location of a light-emitting diode (LED) array, wherein the beam shaping parameter comprises a beam direction, a beam intensity, and a scanning track; and sending a beam to the LED array according to the beam shaping parameter. According to the method and device, displayed content can be presented on an LED array through beam shaping. The LED array does not need input of a power supply and can implement a passive display, and therefore can be deployed more flexibly.

Abstract: A wafer test probe system, probe card, and method to test back-to-back connected first and second transistors of a wafer. The probe card includes a waveform generator circuit and probe needles to couple the waveform generator circuit to provide a first pulse signal of a first polarity using a body diode of the first transistor to test the second transistor, and to provide a second pulse signal of a second polarity using a body diode of the second transistor to the test the first transistor. One example includes a resistor connected between the waveform generator circuit and one of the probe needles. The probe card includes a probe needle to connect a sense transistor of the wafer to the first transistor during wafer probe testing.

Abstract: A contact probe comprises a probe body being extended in a longitudinal direction between respective end portions adapted to realize a contact with respective contact pads, at least one end portion having transverse dimensions greater than the probe body. Suitably, the end portion comprises at least one indentation adapted to house a material scrap being on the contact probe after a separation from a substrate wherein the contact probe has been realized.

Abstract: The present disclosure provides a display device and a detection method for the display device. The display device includes a display area and a non-display area. The display device comprises: a pixel array at the display area, a plurality of switching transistors at the non-display area, and at least one detection line at the non-display area. The pixel array includes a plurality of sub-pixels. The plurality of switching transistors are electrically connected to a plurality of columns of sub-pixels of the pixel array in one-to-one correspondence. Each of the at least one detection line is electrically connected to a part of the plurality of switching transistors.

Abstract: A semiconductor device including a test circuit is disclosed. The semiconductor device includes a test pad coupled to a probe of a test device during a wafer test; a normal pad configured to receive a power or a signal during a normal mode; and a test circuit configured to perform a predetermined test operation based on a test signal received through the test pad. The test circuit is disposed below the normal pad.

Abstract: Provided is a semiconductor testing apparatus that a testing pin is rendered to electrically connect to another testing pin or an external substrate through a conductive layer formed in the guide hole, so that it results in enhancement in various characteristics such as poor electrical contact of the testing pin, space efficiency, noise, and high frequency characteristics, thereby improving reliability in testing results.

Abstract: A wiring substrate for inspection apparatus includes a base substrate and a plurality of tile substrates. The tile substrate is composed of a ceramic substrate section and a first resin substrate section. Each ceramic substrate section is composed of a plurality of ceramic layers and has a plurality of upper-surface connection terminals provided on an upper surface thereof, a plurality of lower-surface connection terminals provided on a lower surface thereof, and a plurality of through conductors for conducting electricity between the upper-surface connection terminals and the lower-surface connection terminals. The first resin substrate section is laminated on the upper surface and includes a laminate of a plurality of resin layers, a plurality of probe pads formed on a resin front-surface thereof, a plurality of inner wiring layers formed between the resin layers, and a plurality of electrically conductive paths for conducting electricity between the probe pads and the upper-surface connection terminals.

Abstract: A handler for holding an electronic device during high voltage testing includes conductive lead guides for shorting leads on one side of the isolator together and connectors connecting the lead guides to conductors.

Abstract: An automatic test equipment (ATE) contactor adapter compatible with at least one test board. The contactor adapter includes a contactor adapter body having a first side and a second side. The contactor adapter body includes: 1) a first set of contact components disposed on the first side in an arrangement to contact conductive pads of the at least one test board; and 2) a second set of contact components disposed on the second side and coupled to the first set of contact points. The contactor adapter also includes an adapter interface disposed on the contactor adapter body. The adapter interface includes a third set of contact components coupled to the second set of contact components. The ATE contactor adapter is configured to convey signals between a device under test (DUT) and the at least one test board via the first, second, and third sets of contact components.

Abstract: An optrode may provide a cylindrical substrate with two or more electrodes deposited on said cylindrical substrate. The cylindrical substrate and electrodes may be coated by an insulating layer with openings or vias over certain portions of the electrodes that may provide a contact for the neural probe or may be utilized to connect lead lines. Manufacturing of an optrode may utilize a jig that secures a cylindrical substrate coated by a conductive material and a resist. A first mask may be positioned in an opening provided by the jig, and the cylindrical substrate may expose ions or neutral particles to define one or more electrode patterns. After regions of the resist and conductive material are removed to form the electrodes, a second mask may be utilized to define via regions in which portions of the electrodes are exposed and uncoated by an insulating layer.

Abstract: An electrical connector and a transmission wafer thereof are provided. The transmission wafer includes an insulating frame, a plurality of grounding terminals fixed to the insulating frame, and a shielding member disposed on the insulating frame. Each of the grounding terminals includes a middle grounding segment embedded in the insulating frame, a front grounding segment, and a rear grounding segment, the latter two of which respectively extend from two ends of the middle grounding segment in two different directions. The shielding member includes a grounding sheet disposed on the insulating frame and a plurality of elastic arms curvedly extending from the grounding sheet to protrude from the insulating frame. The elastic arms are respectively abutted against portions of the front grounding segments arranged adjacent to the insulating frame.

Abstract: Provided are a wafer probe card that matches in one-to-one correspondence with an LED wafer by implementing a probe system having the same size as the LED wafer, and inspects brightness and wavelength of light emitted from a plurality of LEDs provided on the LED wafer at once by controlling the plurality of LEDs to emit light, an analysis apparatus including the same, and a method of fabricating the wafer probe card.

Abstract: An inspection apparatus includes a focus assistant loader and a camera assembly. The focus assistant loader includes a fetching member and a focus member connected to the fetching member. The focus member includes a plurality of focus portions respectively located at different levels. The camera assembly includes a plurality of cameras. The cameras may face the focus assistant loader and respectively focus on the focus portions. Thus, by using the cameras to focus on the focus portions, the inspection apparatus may find out tiny defects on a tested device held by the focus assistant loader. In addition, the present disclosure also discloses a focus assistant loader of an inspection apparatus and a method for inspecting a sensor package structure.

Abstract: A connector for use in a free-standing connector port for mating with an external pluggable module is disclosed. The connector has terminals that extend lengthwise of the connector so that cables may be terminated to the terminals and the terminals and cable generally are horizontally aligned together. The connector includes a housing and a pair of connecting elements that flank a card-receiving slot of the connector. The cables exit from the rear of the connector elements and from the connector port. The connector elements engage the connector port to fix the connector in place within the connector port.

Abstract: Disclosed is an integrated circuit (1) including two electrical power supply terminals (2a, 2b), respectively positive and ground, forming part of a first electrical power supply system (2) internal to the integrated circuit and providing its electrical power supply using an electrical power supply source external to the integrated circuit. The integrated circuit includes two pins (3a, 3b), respectively positive and ground, forming part of a second electrical power supply system (3) and providing an auxiliary electrical connection of the integrated circuit with the outside, the second power supply system being in parallel with the first power supply system, the first power supply system being open when the second power supply system is closed and vice versa.

Abstract: Embodiments for automated testing of a virtualization management system are described. An example computer-implemented method for automated testing of a virtualization management system includes sending, by a test server, a test case to a plurality of instances of the system under test, the test case sent to each instance of the system under test via each interface from a plurality of interfaces supported by the system under test. The method further includes, for each instance of the system under test, performing multi-interface comparison. The comparison includes comparing, by the test server, responses to the test case from each of the interfaces. The method also includes in response to the responses from each of the interfaces being identical, storing the responses in an instance-response file corresponding to the instance. The method also includes reporting, by the test server, an error in response to the responses from each interface not being identical.

Abstract: A testing method for testing wafer level chip scale packages formed on a wafer including a wafer substrate and spaced-apart contact electrodes disposed on the wafer substrate, includes: providing a test device including a probe card formed with a plurality of parallel probe holes having a uniform cross-sectional dimension, and a plurality of probes respectively received in the probe holes and extending respectively in the probe holes along axes of the probe holes; and electrically connecting the contact electrodes to the probes. A distance between the axes of two adjacent ones of the probe holes is equal to a smallest spacing between two adjacent ones of the contact electrodes and is not greater than 0.5 mm.

Abstract: Improved impedance matching is provided in vertical probe arrays having conductive guide plates by providing ground pins connecting the guide plates that do not mechanically touch the device under test or the input test apparatus. Such ground pins can be disposed in predetermined patterns around corresponding signal probes to improve an impedance match between the probes and the test apparatus and/or the device under test. Preferably all impedances are matched to 50? as is customary for high frequency work.

Abstract: A circuit test system is provided for testing a circuit of a circuit board. The circuit test system includes a test platform, a pressing plate and a computing device. The test platform includes plural contact elements. Each contact element includes a strain gauge and a pogo pin. During the process of testing the circuit board, a test program of the computing device monitors and reads a pressure value, a downward displacement and an impedance value of the contact element. Moreover, the test program judges whether the function of the contact element is normal according to the pressure value, the downward displacement and the impedance value.

Abstract: A method of making and testing transfer-printable micro-devices on a source wafer includes providing a source wafer comprising a plurality of sacrificial portions spatially separated by anchors, the source wafer comprising one or more test contact pads, providing a micro-device entirely over each of the plurality of sacrificial portions, each micro-device physically connected to at least one anchor with one or more tethers, providing one or more electrical test connections from each micro-device to a corresponding test contact pad, testing the micro-devices through the test connections to determine functional micro-devices and faulty micro-devices, and removing at least a portion of the one or more test connections.