Abstract: A chip structure includes a first substrate, a second substrate, a conductive via, and a redistribution layer. The first substrate has a first inclined sidewall. The second substrate is located on a bottom surface of the first substrate, and has an upper portion and a lower portion. The lower portion extends from the upper portion. The upper portion is between the first substrate and the lower portion. The upper portion has a second inclined sidewall, and a slope of the first inclined sidewall is substantially equal to a slope of the second inclined sidewall. The conductive via is in the lower portion. The redistribution layer extends from a top surface of the first substrate to a top surface of the lower portion of the second substrate sequentially along the first inclined sidewall and the second inclined sidewall, and is electrically connected to the conductive via.

Abstract: An inspecting device including a carrier, multiple telescopic probes, a locking component and a conductive structure is provided. The carrier has a through hole and a ground pad corresponding to the through hole. The through hole penetrates from the first surface to the second surface of the carrier, and the ground pad is disposed on the second surface. The telescopic probes are disposed in parallel on the first surface of the carrier. The locking component passes through the through hole and is disposed between two adjacent telescopic probes of the multiple telescopic probes. The locking component includes a screw. A head of the screw has a first pitch and a second pitch, and a density of the first pitch is different from a density of the second pitch. The conductive structure is partially embedded in the locking component, and the conductive structure, the locking component and the ground pad are electrically connected.

Abstract: Apparatus for testing an integrated circuit is described, including a set of signal conductors for communicating signals to respective external conductors of the integrated circuit. The apparatus also includes a tester comprising circuitry for outputting a signal. An interposer is electrically coupled between the set of signal conductors and the tester. The interposer comprises circuitry for selecting a set of signals between the set of signal conductors and the tester and outputting the set of signals. A signal processing apparatus is coupled to receive the set of signals, and the signal processing apparatus is operable to evaluate a parameter associated with each signal in the set of signals.

Abstract: Systems, methods, and apparatuses for coupling a flexible circuit to a printed circuit board (PCB) with an interposer in an ultrasound probe are disclosed. A bolster plate configured to compress the PCB, interposer, and flexible circuit against a transducer mount is disclosed. A method of coupling a bolster plate to a transducer mount with fasteners is disclosed. Fasteners that do not pass through the PCB, interposer, and flexible circuit are disclosed.

Abstract: A testing system for electrical interconnects having a removable device under test printed circuit board (DUT PCB) that electrically connects with the electrical testing components of the system. A removable top plate is placed on top of the DUT PCB and is locked in place by a plurality of locking posts that selectively connect to cam surfaces in the top plate that pull the top plate down sandwiching the DUT PCB between the top plate and the electrical testing components of the system. An actuator is also presented that presses the device under test into the electrical interconnect at increments where tests are performed on one, some or all of the contact points of the electrical interconnect. This information is then analyzed and graphed to assist with determine the optimum force and/or height to use during actual use.

Abstract: Some embodiments include an integrated assembly having a memory array, and having digit lines extending along a first direction through the memory array. Insulative spacers are along sidewalls of the digit lines. The insulative spacers extend continuously along the digit lines through the memory array. Conductive regions are laterally spaced from the digit lines by intervening regions. The conductive regions are configured as segments spaced apart from one another along the first direction. The intervening regions include regions of the insulative spacers and include void regions adjacent the regions of the insulative spacers. The void regions are configured as void-region-segments which are spaced apart from one another along the first direction by insulative structures. Storage-elements are associated with the conductive regions. Some embodiments include methods of forming integrated assemblies.

Abstract: A probe includes a probe body for providing an object with a test signal; a tip arranged on an end of the probe body to make contact with the object; and an alignment key protruded from a side of the probe body.

Abstract: The device and method for measuring effect of soiling on a photovoltaic device includes a device in which a photovoltaic device (reference solar cell, solar cells, PV module, etc.) may be shifted between partially and fully enclosed compartments in quick succession for measurements of the same device (1) when directly exposed to illumination or solar radiation; (2) when placed under a glass or transparent cover maintained cleared or cleaned of soil; and (3) when placed under glass or transparent cover left exposed to natural outdoor soiling, or attenuated using simulated soil that is not periodically cleaned. The measurements may be of short circuit current (Isc), maximum power (Pmax), which are used to calculate the to soiling ratio. If the transparent covers have substantially identical optical properties and meet identical requirements for positioning relative to the DUT, only measurements (2) and (3) are required, and calculations of the soiling ratio are simplified.

Abstract: Methods of fabricating semiconductor devices and Radio Frequency (RF) components are provided. The method includes providing a circuit layout on a semiconductor layer and providing one or more sacrificial connections to connect bump pads in the circuit layout. The method also includes testing the circuit layout using the one or more sacrificial connections and removing at least a portion of the one or more sacrificial connections. In this way, the performance of the semiconductor device is improved by reducing or avoiding capacitive or inductive leakage paths that can be caused by leftover materials.

Abstract: A test and measurement system including a test and measurement instrument, a probe connected to the test and measurement instrument, a device under test connected to the probe, at least one memory configured to store parameters for characterizing the probe, a user interface and a processor. The user interface is configured to receive a nominal source impedance of the device under test. The processor is configured to receive the parameters for characterizing the probe from the memory and the nominal source impedance of the device under test from the user interface and to calculate an equalization filter using the parameters for characterizing the probe and nominal source impedance from the user interface.

Abstract: A testing probe card for wafer level testing semiconductor IC packaged devices. The card includes a circuit board including testing circuitry and a testing probe head. The probe head includes a probe array having a plurality of metallic testing probes attached to a substrate including a plurality of conductive vias. In one embodiment, the probes have a relatively rigid construction and have one end that may be electrically coupled to the vias using a flip chip assembly solder reflow process. In one embodiment, the probes may be formed from a monolithic block of conductive material using reverse wire electric discharge machining.

Abstract: Wafer test structures and methods of providing wafer test structures are described. The methods include: fabricating multiple test devices and multiple fuse devices on the wafer, each test device having a respective fuse device associated therewith, which open circuits upon failure of the test device; and fabricating a selection circuit operative to selectively connect one test device to a sense contact pad, and the other test devices to a stress contact pad. The selection circuit facilitates sensing one or more electrical signals of the one test device by electrical contact with the sense contact pad, while stress testing the other test devices by electrical contact with the stress contact pad. In one embodiment, each test device has respective first and second switch devices, operative to selectively electrically connect the test device to the sense or stress contact pads. In another embodiment, the method includes wafer testing using the test structure.

Abstract: A collapsible probe tower device and methods of forming thereof, are disclosed. In one example embodiment, a method of forming a device includes providing a semiconductor die substrate having a contact pad and a probe pad, wherein the contact pad and probe pad are adhered to the substrate, forming a contact bump by applying a conductive material to a contact structure surface of a contact tower, wherein the contact tower includes the contact pad, forming a probe bump by applying a conductive material to a probe structure surface of a probe tower, wherein the probe tower includes the probe pad, and heating the conductive material that forms the contact bump and the probe bump to provide a first reflow, wherein after the first reflow, the height of a top surface of the probe bump exceeds the height of a top surface of the contact bump.

Abstract: A package of an electronic device, a system including the same and a method for fabricating the same are provided. The package of the electronic device includes a substrate, a step difference layer and a connecting bump. The substrate allows a connecting contact part to be exposed on a surface thereof. The step difference layer covers the substrate so as to leave the connecting contact part exposed. The connecting bump is connected to the connecting contact part so that one end part of the connecting bump is extended on the step difference layer, and has a sloped upper surface formed by a step difference formed by the step difference layer.

Abstract: Methods and apparatus for testing unsingulated integrated circuits on a wafer include adapting a wafer prober for use with full-wafer-contacter disposed on the wafer. Some embodiments include placing wafer on a chuck of the prober, aligning the wafer to a full-wafer contacter incorporated in the wafer prober, removably attaching the wafer to the full wafer contacter, separating the wafer from the chuck, and making electrical contact to one or more integrated circuits of the wafer by making physical contact with a surface of the full-wafer contacter that faces away from the wafer.

Abstract: A method comprises connecting a testing setup having a plurality of probes to a device under test having a plurality of vias, wherein a probe is aligned with a corresponding via of the device under test and conducting a plurality of via electrical characteristic tests through a conductive path comprising the vias, the probes and a plurality of conductive devices, each of which connects two adjacent probes, wherein the conductive devices are in the testing setup.

Abstract: An apparatus includes a probe card, a plurality of sort probes coupled to the probe card and detector circuitry to detect a real time over current occurrence at the sort probes.

Abstract: [Problems to be solved] To provide a test-use individual substrate capable of improving testing accuracy and connecting reliability. [Means for solving the Problems] A test-use individual substrate 30 which is used for testing a semiconductor wafer, comprises a main body portion 31, thin portions 321, 322 extending from the main body portion 31 and being relatively thinner than the main body portion, and bumps 33 provided on the thin portions 321, 322.

Abstract: Composite materials having conductive properties are described for use in testing circuits and in manufacturing electrical switches. The composite materials described, when in an unstressed state, generally behave as insulators. However, when sufficient mechanical pressure is applied to portions of the composite materials, the portions to which the mechanical pressure is applied become increasingly conductive. Methods for testing a PCB using composite material switches are also disclosed. A sheet that includes a composite material may be used to test electrical functionality of various regions on a PCB by way of local pressure application. The sheet may be easily applied to and removed from the PCB. Additionally, in forming an electrical switch, a voltage applied to one or more actuating elements may be used to provide mechanical pressure to a composite material that is disposed between two conductive members.

Abstract: A probe card includes a plurality of probe pins, and a switch network connected to the plurality of probe pins. The switch network is configured to connect the plurality of probe pins in a first pattern, and reconnect the plurality of probe pins in a second pattern different from the first pattern.

Abstract: An interposer to be mounted with an integrated circuit to be a test object is provided with a switch and a probe to detect an electric current corresponding to individual terminals of the integrated circuit. A test pattern signal is then inputted to the integrated circuit through a test substrate as a switch that is connected to a power supply terminal of the integrated circuit and that is turned off. If the integrated circuit normally operates and the current values of all the terminals of the integrated circuit are within a tolerance, the power supply terminal connected to the turned-off switch is identified as a terminal that may be removed.

Abstract: In accordance with an embodiment, a probe card structure comprises a base board, a connection interposer over the base board, a substrate over the connection interposer, and a fixture over the substrate securing the substrate and the connection interposer to the base board. The connection interposer comprises interposer electrodes that provide an electrical connection between electrodes on the base board and first electrodes on the substrate.

Abstract: A test system for testing a plurality of semiconductor chips formed on a semiconductor wafer includes: a test wafer on which a plurality of test circuits corresponding to the plurality of semiconductor chips are formed, each test circuit testing a corresponding one of the plurality of semiconductor chips based on test data provided to the test circuit; where each of the plurality of test circuits includes a nonvolatile and rewritable pattern memory for storing the test data such as pattern data and sequence data, and the test system writes the same test data to all the plurality of test circuits in parallel.

Abstract: A signal capture system for capturing a signal and storing the captured signal in a storage apparatus in real time, and a test apparatus including the signal capture system. The signal capture system includes a printed circuit board; a socket that is connected to the printed circuit board and on which a reference memory component is mounted; and an interposer that is mounted on the printed circuit board, is connected to the socket, an external apparatus, and a storage apparatus, receives first signals from the reference memory component and transmits the received first signals to the external apparatus and the storage apparatus, and receives second signals from the external apparatus and transmits the received second signals to the reference memory component and the storage apparatus, wherein a shape of the socket is defined according to a type of the reference memory component.

Abstract: A probe card is provided that is capable of accurately ensuring the flatness and the parallelism with respect to a predetermined reference surface. A point (Q) of application of force applied from a leaf spring (17) that presses a portion near an edge portion of a surface of a probe head (15) from which a plurality of probes projects over an entire circumference in a direction of a substrate to the probe head (15) is positioned inside of an outer edge of the probe head (15), and a point (P) of application of force applied from the retainer (16) that presses a portion near an edge portion of a space transformer (14) over an entire circumference in the direction of the substrate to the space transformer (14) is positioned inside of an outer edge of the space transformer (14).

Abstract: There is provided a testing system for testing a plurality of semiconductor chips formed on a single semiconductor wafer. The testing system includes a wafer substrate, a plurality of wafer connector terminals that are provided on the wafer substrate in such a manner that one or more wafer connector terminals correspond to each of the semiconductor chips, where each wafer connector terminal is to be electrically connected to an input/output terminal of a corresponding semiconductor chip, a plurality of circuit units that are provided on the wafer substrate in such a manner that one or more circuit units corresponds to each of the semiconductor chips, where each circuit unit generates a test signal to be used for testing a corresponding semiconductor chip and supplies the test signal to the corresponding semiconductor chip to test the corresponding semiconductor chip, and a controller that generates a control signal used to control the plurality of circuit units.

Abstract: In one embodiment, a test system has a set of test electronics for testing a device under test (DUT). The test system also has at least one test electronics to DUT interface having a zero insertion force (ZIF) connector. Each ZIF connector has a ZIF connector to DUT clamping mechanism configured to i) apply a first orthogonal force to a probe card that interfaces with a DUT, by pressing the ZIF connector against the probe card, and simultaneously ii) exert at least one second orthogonal force on the probe card, the at least one second orthogonal force being opposite in direction to the first orthogonal force.

Abstract: Recesses are formed on one surface of a substrate. A conductive film covers an inner surface of each of the recesses. This conductive film contacts a bump of a semiconductor device to be inspected and is electrically connected to the bump. It is therefore possible to prevent damages of the bump to be caused by contact of a probe pin.

Abstract: Disclosed is a contactor interconnect in an integrated circuit device test fixture comprises a plurality of contactor pins enabled to provide electrical contact with the contact points of an integrated circuit device, the contactor pins being mounted in the test fixture; and an electrical circuit coupled to two or more of the contactor pins of the test fixture, wherein the electrical circuit is isolated from other contactor pins of the plurality of contactor pins and wherein the electrical circuit is coupled to the two or more contactor pins by an electronically direct pathway.

Abstract: A set of first substrate and second substrate are manufactured with a built-in N-fold rotational symmetry around the center axis of each substrate, wherein N is an integer greater than 1. A set of N different interposers is provided such that an i-th interposer provides electrical connection between the first substrate and the second substrate with a rotational angle of (i?1)/N×2?. The first and second substrates are tested with each of the N different interposers therebetween. Once the rotational angle that provides the highest stacked chip yield is determined, the first and the second substrates can be bonded with an azimuthal rotation that provides the highest stacked chip yield.

Abstract: Flexible and rigid interposers for use in the semiconductor industry and methods for manufacturing the same are described. Auto-catalytic processes are used to minimize the costs associated with the production of flexible interposers, while increasing the yield and lifetime. Electrical contact regions are easily isolated and the risk of corrosion is reduced because all portions of the interposer are plated at once. Leads projecting from the flexible portion of the interposers accommodate a greater variety of components to be tested. Rigid interposers include a pin projecting from a probe pad affixed to a substrate. The rigidity of the pin penetrates oxides on a contact pad to be tested. Readily available semiconductor materials and processes are used to manufacture the flexible and rigid interposers according to the invention. The flexible and rigid interposers can accommodate pitches down to 25 ?m.

Abstract: A probe test card assembly for testing a device under test includes interposer probes to connect a printed circuit board to a substrate. The probe test card assembly includes a printed circuit board, a substrate and a substrate holder. A plurality of test probes is connected to the substrate for making electrical contact with the device under test. A plurality of interposer probes is attached to the substrate for providing electrical connections between the substrate and the printed circuit board. The substrate holder holds the substrate in position with respect to the printed circuit board so that the interposer probes contact the printed circuit board. The interposer probes may be arranged in interposer probe groups to facilitate maintenance and replacement of the interposer probes. Hardstop elements may also be used to protect the interposer probes.

Abstract: An interposer to be mounted with an integrated circuit to be a test object is provided with a switch and a probe to detect an electric current corresponding to individual terminals of the integrated circuit. A test pattern signal is then inputted to the integrated circuit through a test substrate as a switch that is connected to a power supply terminal of the integrated circuit and that is turned off. If the integrated circuit normally operates and the current values of all the terminals of the integrated circuit are within a tolerance, the power supply terminal connected to the turned-off switch is identified as a terminal that may be removed.

Abstract: A test system including a package with switchable paths. The package may have conductive paths that are selected by switches. The electrically switchable conductive paths may yield increased data without significantly increasing the required testing hardware.

Abstract: There is provided a testing system for testing a plurality of semiconductor chips formed on a single semiconductor wafer. The testing system includes a wafer substrate, a plurality of wafer connector terminals that are provided on the wafer substrate in such a manner that one or more wafer connector terminals correspond to each of the semiconductor chips, where each wafer connector terminal is to be electrically connected to an input/output terminal of a corresponding semiconductor chip, a plurality of circuit units that are provided on the wafer substrate in such a manner that one or more circuit units corresponds to each of the semiconductor chips, where each circuit unit generates a test signal to be used for testing a corresponding semiconductor chip and supplies the test signal to the corresponding semiconductor chip to test the corresponding semiconductor chip, and a controller that generates a control signal used to control the plurality of circuit units.