Penetrative Patents (Class 324/754.2)
  • Patent number: 10784204
    Abstract: Integrated circuit (IC) chip die to die channel interconnect configurations (systems and methods for their manufacture) may improve signaling to and through a single ended bus data signal communication channel by including on-die induction structures; on-die interconnect features; on-package first level die bump designs and ground webbing structures; on-package high speed horizontal data signal transmission lines; on-package vertical data signal transmission interconnects; and/or on-package electro-optical (EO) connectors in various die to die interconnect configurations for improved signal connections and transmission through a data signal channel extending through one or more semiconductor device package devices, that may include an electro-optical (EO) connector upon which at least one package device may be mounted, and/or be semiconductor device packages in a package-on-package configuration.
    Type: Grant
    Filed: July 2, 2016
    Date of Patent: September 22, 2020
    Assignee: Intel Corporation
    Inventors: Kemal Aygun, Richard J. Dischler, Jeff C. Morriss, Zhiguo Qian, Wilfred Gomes, Yu Amos Zhang, Ram S. Viswanath, Rajasekaran Swaminathan, Sriram Srinivasan, Yidnekachew S. Mekonnen, Sanka Ganesan, Eduard Roytman, Mathew J. Manusharow
  • Patent number: 10777410
    Abstract: Methods of synthesis and fabrication of a transition metal dichalcogenide (TMD) structures are disclosed. A method can include first patterning a transition metal (TM) on a substrate and placing the substrate in a process chamber. Oxygen can be applied to the transition metal on the substrate and a mixture of highly reactive transition metal oxides can be formed and simultaneously thinned down by sublimation. Finally, a chalcogen can be applied to the substrate and a transition metal dichalcogenide structure can be formed.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: September 15, 2020
    Assignee: University of South Carolina
    Inventors: Ifat Jahangir, Goutam Koley, MVS Chandrashekhar
  • Patent number: 10594047
    Abstract: A functional contactor is provided. The functional contactor according to one embodiment of the present invention includes: a conductive elastic portion configured to be in electrical contact with a conductor of an electronic device and have elasticity; and a functional device including a first electrode electrically connected to a circuit board or the conductor of the electronic device and a second electrode on which the conductive elastic portion is laminated through solder. Here, the second electrode includes a stopper in which no electrode is formed to prevent the solder from being introduced into a periphery of a lamination region on which the conductive elastic portion is laminated.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: March 17, 2020
    Assignee: AMOTECH CO., LTD.
    Inventors: Jae Woo Choi, Byung Guk Lim, Seong Ha Lee, Yun Suk Choi, Dong Hun Kong
  • Patent number: 10578650
    Abstract: Disclosed is a shunt resistor for measuring current, and a shunt resistor for measuring current, in which one or more protrusions having an unevenness shape, which are formed on one lateral surface of a shunt resistor and one or more solders are bonded to each other, respectively and the shunt resistor and a printed circuit board are electrically connected to each other to measure current of a battery through a shunt resistance included in the shunt resistor unit.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: March 3, 2020
    Assignee: LG Chem, Ltd.
    Inventors: Dong Kwan Jang, Ki Chan Kim, Sang Dae Park, Kil Ja Lim
  • Patent number: 9885749
    Abstract: A method in accordance with various embodiments may include: measuring a contact force between at least one probe and at least one contact pad for a plurality of probe overdrive positions, and determining a relationship between contact force and probe overdrive position from the measured contact forces; determining a first region in the relationship exhibiting a non-linear dependence of the contact force from the probe overdrive position, and a second region exhibiting a linear dependence of the contact force from the probe overdrive position; and determining a process window for a pad probing process based on the determined first region and second region.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: February 6, 2018
    Inventors: Ivan Penjovic, Josef Martin Paul Hennig, Oliver Nagler
  • Patent number: 9685717
    Abstract: A method and structure for improving signal integrity probing. A coaxial or a microcoaxial cable is threaded through an optional alignment substrate where the cable is used to support or align the cable or an array of cables. A conductive elastomer is placed on a cable or a microcoaxial cable to improve signal integrity probing.
    Type: Grant
    Filed: October 13, 2014
    Date of Patent: June 20, 2017
    Assignee: R+D Sockets, Inc.
    Inventors: Thomas P. Warwick, James V. Russell
  • Patent number: 9297832
    Abstract: The terminals of a device under test (DUT) are temporarily electrically connected to corresponding contact pads on a load board by a series of electrically conductive pin pairs. The pin pairs are held in place by an interposer membrane with a top facing the device under test, a bottom facing the load board, and a vertically resilient, non-conductive member between the top and bottom contact plates. Each pin pair includes a top and bottom pin, which extend beyond the top and bottom contact plates, respectively, toward the device under test and the load board, respectively. The bottom pins has a lower contact surface which includes an arcuate portion or ridge which increases contact pressure and ablates oxides by the rocking action of ridge when the DUT in inserted.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: March 29, 2016
    Assignee: Johnstech International Corporation
    Inventors: John E. Nelson, Jeffrey C. Sherry, Brian Warwick, Gary W. Michalko
  • Patent number: 8988092
    Abstract: A probing apparatus for semiconductor devices provides a primary circuit board and a signal-adapting board positioned on the primary circuit board. The primary circuit board includes an inner area having a plurality of first contacts and an outer area having a plurality of first terminals and second terminals, and the first contacts are electrically connected to the first terminals via first conductive members in the primary circuit board. The signal-adapting board includes a plurality of second contacts electrically connected to the first contacts via second conductive members in the signal-adapting board.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: March 24, 2015
    Assignee: Star Technologies Inc.
    Inventors: Chen Jung Hsu, Chao Cheng Tseng
  • Publication number: 20150015288
    Abstract: A test probe is provided for probing signal information on a back-drilled plated through hole connector formed in a printed circuit board, where the test probe includes a conductive probe body with a distal tip region extending a predetermined minimum coverage length (LTIP) that is longer than a recess depth dimension (DPL) for a recessed plating layer formed in the back-drilled plated through hole connector with an elastomer test probe tip formed around the distal tip region and having a total tip width (WTIP) which is compressed when inserted into the recessed plating layer formed in a back-drilled plated through hole connector, thereby establishing a conductive path between the conductive probe body and the recessed plating layer.
    Type: Application
    Filed: July 10, 2013
    Publication date: January 15, 2015
    Inventor: Wai M. Ma
  • Patent number: 8633720
    Abstract: High-frequency resonance method is used to measure magnetic parameters of magnetic thin film stacks that show magnetoresistance including MTJs and giant magnetoresistance spin valves. The thin film sample can be unpatterned. Probe tips are electrically connected to the surface of the film (or alternatively one probe tip can be punched into the thin film stack) and voltage measurements are taken while injecting high frequency oscillating current between them to cause a change in electrical resistance when one of the layers in the magnetic film stack changes direction. A measured resonance curve can be determined from voltages at different current frequencies. The damping, related to the width of the resonance curve peak, is determined through curve fitting. In embodiments of the invention a variable magnetic field is also applied to vary the resonance frequency and extract the magnetic anisotropy and/or magnetic saturation of the magnetic layers.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: January 21, 2014
    Assignee: Avalanche Technology Inc.
    Inventors: Ioan Tudosa, Yuchen Zhou, Jing Zhang, Rajiv Yadav Ranjan, Yiming Huai
  • Patent number: 8599031
    Abstract: A system for detecting stray voltage in a conductive object is disclosed herein. The system includes a pick-up element, electrical circuitry, a housing for enclosing the circuitry, a support for mounting the housing, and an indicator. The pick-up element is separated from the conductive object and capable of detecting an electric field from the conductive object. The support of the housing is such that the pick-up element remains separated from the conductive object. The electrical circuitry determines a voltage level corresponding to the electric field detected by the pick-up element and generates, based on a comparison of the determined voltage level relative to a reference voltage level, an indicator signal representative of whether stray voltage is present in the conductive object. Based on the indicator signal, the indicator indicates to a user of the system whether stray voltage is present in the conductive object.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: December 3, 2013
    Assignee: NSTAR Electric Company
    Inventors: Lawrence J. Gelbien, Werner J. Schweiger, Philip B. Andreas
  • Patent number: 8451017
    Abstract: A substrate, preferably constructed of a ductile material and a tool having the desired shape of the resulting device for contacting contact pads on a test device is brought into contact with the substrate. The tool is preferably constructed of a material that is harder than the substrate so that a depression can be readily made therein. A dielectric (insulative) layer, that is preferably patterned, is supported by the substrate. A conductive material is located within the depressions and then preferably lapped to remove excess from the top surface of the dielectric layer and to provide a flat overall surface. A trace is patterned on the dielectric layer and the conductive material. A polyimide layer is then preferably patterned over the entire surface. The substrate is then removed by any suitable process.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: May 28, 2013
    Assignee: Cascade Microtech, Inc.
    Inventors: K. Reed Gleason, Michael A. Bayne, Kenneth Smith, Timothy Lesher, Martin Koxxy
  • Patent number: 8451015
    Abstract: A method of testing an electrical component includes coupling the electrical component to at least a first probe, a second probe, and a third probe. The probes are in communication with a test control module. Furthermore, the method includes confirming that the probes are in sufficient electrical connection with the electrical component by allowing the test control module to supply a current through the electrical component via the first probe and the third probe, and simultaneously detecting a potential difference across the electrical component by the second probe and the third probe. Furthermore, the method includes testing a performance characteristic of the electrical component by supplying a redundant signal to the electrical component via at least two of the first probe, the second probe, and the third probe.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: May 28, 2013
    Assignee: Medtronic, Inc.
    Inventors: Christian S. Nielsen, Timothy T. Bomstad
  • Publication number: 20120262198
    Abstract: A method of testing a semiconductor device includes providing a first wafer that includes a first surface, a second surface that is allocated at an opposite side of the first surface, a first electrode penetrating the first wafer from the first surface to the second surface, and a pad formed on the first surface and coupled electrically with the first electrode, providing a second wafer that includes a second electrode penetrating the second wafer, stacking the first wafer onto the second wafer to connect the first electrode with the second electrode such that the second surface of the first wafer faces the second wafer, probing a needle to the pad, and supplying, in such a state that the first wafer is stacked on the second wafer, a test signal to the first electrode to input the test signal into the second wafer via the first electrode and the second electrode.
    Type: Application
    Filed: June 22, 2012
    Publication date: October 18, 2012
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Yoshiro RIHO
  • Patent number: 8253430
    Abstract: A test point of a circuit board is probed using an edge probe provided in a fixed orientation when the edge of the probe contacts a solder mound of the test point. The solder mound has an elongated shape. A length of the edge is substantially perpendicular to a length of the solder mound when the edge contacts the solder mound and is maintained in the fixed orientation.
    Type: Grant
    Filed: October 14, 2008
    Date of Patent: August 28, 2012
    Assignee: Hewlett-Packard Development Company
    Inventor: Alexander Leon
  • Publication number: 20120049876
    Abstract: [Problems to be solved] To provide a test-use individual substrate capable of improving testing accuracy and connecting reliability. [Means for solving the Problems] A test-use individual substrate 30 which is used for testing a semiconductor wafer, comprises a main body portion 31, thin portions 321, 322 extending from the main body portion 31 and being relatively thinner than the main body portion, and bumps 33 provided on the thin portions 321, 322. [Selected Drawing] FIG.
    Type: Application
    Filed: August 18, 2011
    Publication date: March 1, 2012
    Inventors: Shigeru MATSUMURA, Kohei KATO, Katsushi SUGAI, Koichi SHIROYAMA, Mitsutoshi HIGASHI, Akinori SHIRAISHI, Hideaki SAKAGUCHI