Abstract: The present invention relates to a pogo pin cooling system and a pogo pin cooling method and an electronic device testing apparatus having the system. The system mainly comprises a coolant circulation module, which includes a coolant supply channel communicated with an inlet of a chip socket and a coolant recovery channel communicated with an outlet of the chip socket. When an electronic device is accommodated in the chip socket, the coolant circulation module supplies a coolant into the chip socket through the coolant supply channel and the inlet, and the coolant passes through the pogo pins and then flows into the coolant recovery channel through the outlet.

Abstract: Electronic device characterization platforms, systems, devices, and methods for use in testing instruments, devices, and sensors that is portable, modular, multiplexed, and automated are disclosed. The system includes a substrate, a chip adapter, such as a chip socket, and an optional housing. Chip samples to be tested can be disposed in the chip adapter and various environmental modules designed to supply different environmental conditions to the chip sample can be disposed over the chip adapter, enabling testing of the chip samples to be performed in the different environment conditions. The system can further include various connectors that allow for add-on modules to be included as part of the system. Methods of characterizing electronic devices and sensors are also disclosed.

Abstract: An apparatus includes a test head frame and a tray slidably coupled to the frame and configured to receive a printed circuit board (PCB) to be tested. The PCB is positioned within the frame when the tray is in a retracted position and outside the frame when the tray is in an ejected position. A bed of nails (BON) opposes a lower side of the PCB and includes a plurality of pins having first portions arranged on an upper side of the BON to connect with corresponding electrical pads on the lower side of the PCB when the tray containing the PCB is in the retracted position. A plurality of interface printed circuit boards is configured for connection to second portions of the plurality of pins exposed on a lower side of the BON and for receiving test signals when the tray containing the PCB is in the retracted position.

Abstract: A semiconductor test device may include a chamber, a plurality of slots, a plurality of test boards and a plurality of temperature control modules. The slots may be arranged in the chamber. The test boards may be inserted into a part of the slots. The test boards may be configured to receive a plurality of semiconductor devices. The temperature control modules and the test boards may be alternately inserted into other parts of the slots. The temperature control modules may be configured to provide each of the test boards with air having a set temperature.

Abstract: In a connector system for a battery system, the connector system includes: a connector configured to electrically connect to a counterpart of the connector, wherein the connector comprises a negative connection element and a positive connection element; a first temperature sensor thermally connected to the negative connection element; a second temperature sensor thermally connected to the positive connection element; and a control unit configured to receive a first temperature signal from the first temperature sensor and to receive a second temperature signal from the second temperature sensor; wherein the control unit configured to generate a first value based on the first temperature signal and a second value based on the second temperature signal; and wherein the control unit is further configured to generate an alert signal in response to an absolute value of a difference between the first value and the second value exceeding a predefined threshold.

Abstract: A testing system for electrical interconnects having a removable device under test printed circuit board (DUT PCB) that electrically connects with the electrical testing components of the system. A removable top plate is placed on top of the DUT PCB and is locked in place by a plurality of locking posts that selectively connect to cam surfaces in the top plate that pull the top plate down sandwiching the DUT PCB between the top plate and the electrical testing components of the system. An actuator is also presented that presses the device under test into the electrical interconnect at increments where tests are performed on one, some or all of the contact points of the electrical interconnect. This information is then analyzed and graphed to assist with determine the optimum force and/or height to use during actual use.

Abstract: An apparatus such as a node in a daisy chain of electronic devices includes a serial data input port receive input from an electronic device in the daisy chain. The apparatus includes a serial data output port to send output to another electronic device in the daisy chain. The apparatus includes a chip select input port configured to receive input from a master control unit, and an interface circuit configured to, in a daisy chain streaming mode, and based on a received command and changed edge of a signal on the chip select input port, repeatedly: read data from a data source of the apparatus to yield data, output the data to the serial data output port, and copy other data received at the serial data input port to the serial data output port after the data.

Abstract: An apparatus is described for burn-in and/or functional testing of microelectronic circuits of unsingulated wafers. A large number of power, ground, and signal connections can be made to a large number of contacts on a wafer. The apparatus has a cartridge that allows for fanning-in of electric paths. A distribution board has a plurality of interfaces that are strategically positioned to provide a dense configuration. The interfaces are connected through flexible attachments to an array of first connector modules. Each one of the first connector modules can be independently connected to a respective one of a plurality of second connector modules, thereby reducing stresses on a frame of the apparatus. Further features include for example a piston that allows for tight control of forces exerted by terminals onto contacts of a wafer.

Abstract: This application relates to a method and apparatus for outputting signals. In one aspect, the apparatus includes a signal control unit configured to generate two or more control signals upon two or more conditions, which respectively correspond to the two or more control signals being satisfied. The apparatus also includes a signal output unit configured to output a final output signal depending on the two or more control signals upon an input signal being inputted into the signal output unit.

Abstract: An electronic device having a structure that electrically connects the contactor to an electronic device during a testing process is disclosed. The contactor includes a holder for accommodating the electronic device during the testing process; a flexible circuit, having a first set of contacts electrically connected to the corresponding electrode terminals of the electronic device, and a second set of contacts electrically connected to a control unit that sends test signals during the test process; an elastomer, for adjusting the pressure between the first set of contacts of the flexible circuit and the corresponding electrode terminals of the electronic device while being pressed together; and an alignment tool, for aligning the first set of contacts with the corresponding electrode terminals of the electronic device. The electrode terminals of the electronic device are located on the same surface of the electronic device and the flexible circuit is detachable from the contactor.

Abstract: A test system and method for relay connection and testing of a power transmission and distribution grid including a fixed connection block connected to the power transmission and distribution grid, and a mobile plug which connects the fixed connection block or a mobile test block with the relay when the mobile plug is inserted into the fixed connection block or the mobile test block. The mobile test block provides a connection to an external relay testing device when the mobile test plug is inserted into the mobile test block, the fixed connection block provides internal shorting that is activated when the mobile plug is not inserted into the fixed connection block and is deactivated when the mobile plug is inserted into the fixed connection block, and the fixed connection block, mobile plug, and the mobile test block provides an interaction between a power transmission and distribution grid side and a relay side. This allows a quick recovery when relays are damaged in a cyber-attack.

Abstract: There is provided an intermediate connection member provided between a first member having a plurality of first terminals and a second member having a plurality of second terminals to electrically connect the plurality of first terminals and the plurality of second terminals, respectively. The intermediate connection member includes: a block member including connection members configured to electrically connect the plurality of first terminals and the plurality of second terminals, respectively; a frame member having an insertion hole into which the block member is inserted; and an electronic component electrically connected to one of the connection members.

Abstract: An interactive core for use in making electronic cards has rear and front adhesive layers which surround a stiffening spacer which has an interior opening in which electronic components (e.g., a PCB, battery and display) are located along with thermosetting polymeric material. A battery contained within the interior opening can be activated from an off state to an on state via use of an initialization antenna which can also be configured to allow a CPU to be customized for personal use.

Abstract: A test assembly includes multiple circuit boards. Each board includes multiple pairs of contacts configurable to address the respective circuit board, an instrument, first and second headers at opposing edges of the respective board. Each pin of a first header electrically connects through the board to a corresponding pin of a second header. Each board includes first and second input/output (I/O) terminals at opposing edges of the respective board, the first I/O terminal electrically connects through the board to the second I/O terminal. A relay on the board permits the board's instrument to be activated. Each of the circuit boards mechanically and electrically connects to another circuit board through a jumper cable connecting the first header of one circuit board to the second header of another circuit board and through a conductive member electrically connecting the first I/O terminal of one board to the second I/O terminal of another board.

Abstract: A cartridge, including a cartridge frame, formations on the cartridge frame for mounting the cartridge frame in a fixed position to an apparatus frame, a contactor support structure, a contactor interface on the contactor support structure, a plurality of terminals, held by the contactor support structure, for contacting contacts on a device, and a plurality of conductors, held by the contactor support structure, connecting the interface to the terminals.

Abstract: The present disclosure relates to a control device with at least one touch-sensitive input surface that can be activated for haptic feedback with an electromagnetic actuator, where the actuator comprises an actuator coil and an armature that is activated by energizing the actuator coil. The control device is divided into at least two control assemblies at least one of which has a touch-sensitive input surface and an armature connected therewith. These at least two control assemblies are installed at a minimum spacing from each other on a common circuit board, which in turn is connected with a common carrier element, whereby the armatures protrude through the circuit board with play. On each carrier element, an actuator coil at a spacing x from the armature of the respective control assembly is installed. The present disclosure also refers to a process for manufacturing the control device.

Abstract: An integrated circuit assembly includes an integrated circuit package substrate and a conductive land pad disposed on a surface of the integrated circuit package substrate. The conductive land pad comprises a conductor portion, an isolated conductor portion, and an isolation portion disposed between the conductor portion and the isolated conductor portion. The isolated conductor portion may surround a first side of the conductor portion and a second side of the conductor portion. The isolated conductor portion may surround a portion of a perimeter of the conductor portion. The isolation portion may include a gap between the conductor portion and the isolated conductor portion. The gap may have a width smaller than a radius of an interconnect structure of a receiving structure.

Abstract: Crosstalk between probes in a vertical probe array is reduced by providing a grounded metal carrier disposed between the guide plates of the probe array. The metal carrier includes pockets that are laterally separated from each other by the metal carrier. Probes in different pockets are thereby electrically shielded from each other.

Abstract: Vertical probe heads having a space transformer laterally tiled into several sections are provided. This change relative to conventional approaches improves manufacturing yield. These probe heads can include metal ground planes, and in embodiments where the ground planes are provided as separate metal plates parallel to the guide plates, the metal plates can also be laterally tiled into several sections. Such tiling of metal plates improves manufacturing yield and alleviates thermal mismatch issues. Probes are not mechanically connected to the space transformer, which facilitates replacement of individual probes of an array.

Abstract: An integrated chip package assembly test system and method for testing a chip package assembly are described herein. In one example, an integrated circuit chip package test system includes a socket and a workpress. The socket is configured to receive a chip package assembly for testing in the test system. The workpress includes a plurality of pusher pins. The plurality of pusher pins have tips extending from a bottom surface of the workpress. Each of the plurality of pusher pins is configured to apply an independent and discrete force to the chip package assembly disposed in the socket.

Abstract: An integrated chip package assembly test system and method for testing a chip package assembly are described herein. In one example, an integrated circuit chip package test system includes a socket and a workpress. The socket is configured to receive a chip package assembly for testing in the test system. The workpress is positioned over the socket and has a bottom surface that is dynamically conformable to a multi-planar top surface topography of the chip package assembly.

Abstract: The disclosure relates to a loop bridge for looping through a number of electrical signals, comprising: a first electric module comprising a plurality of first electric connections, wherein the plurality of electrical signals are looped through the first electric module to a second electric module comprising a number of second electric connections; and a comb-shaped conducting element comprising a number of first prongs and a number of second prongs, wherein the first prongs are configured to be inserted into the first electric connections and the second prongs are configured to be inserted into the second electric connections, wherein the first prongs are connected to the second prongs in an electrically conductive manner, and wherein the first prongs and the second prongs are configured to be elastically deformed to be retained in a force-locking manner in the first and second electric connections, respectively.

Abstract: Aspects of the disclosure provide a chip package that includes a first die and a second die. The first die has a processing circuit and a first interface circuit. The second die is disposed in a proximity to the first die and coupled to the first die. The second die includes internal functional circuits, two or more second interface circuits with an identical configuration, and a switch circuit. A specific second interface circuit is electrically connected to the first interface circuit via wires. The switch circuit is configured to select the specific second interface circuit from the two or more second interface circuits, and couple the specific second interface circuit to the internal functional circuits on the second die.

Abstract: To provide a crystal orientation mark which can be formed easily and inexpensively, and which enables to perform high precision alignment and allows information other than crystal orientation to be included, even for a small diameter process substrate. A crystal orientation mark is drawn on the surface of the process substrate. The crystal orientation mark includes a marking region for crystal orientation detection, and a marking region for information. The marking region for crystal orientation detection is provided at two locations in an outer edge portion of the process substrate to be used for the alignment of the process substrate. The marking region for information is provided on a straight-line region connecting the marking regions for crystal orientation detection at the two locations, and includes a pattern for demonstrating predetermined information relating to the process substrate.

Abstract: A device includes a test pad on a chip. A first microbump has a first surface area that is less than a surface area of the test pad. A first conductive path couples the test pad to the first microbump. A second microbump has a second surface area that is less than the surface area of the test pad. A second conductive path couples the test pad to the second microbump.

Abstract: A test unit according to the present invention includes: a first contact probe contacting with an electrode provided on a front surface of one of contact targets, and contacting with an electrode of the other contact target; a second contact probe contacting with an electrode provided on a back surface of the one of contact targets and contacting with an electrode of a substrate; a first probe holder including a suction holder that sucks and holds the one of contact targets, and accommodating and holding therein the first contact probes; a second probe holder accommodating and holding therein the second contact probes; and a base portion, which is layered over the first probe holder and holds the other contact target at a side thereof layered over the first probe holder; and a gap is formed between the other contact target and the first probe holder.

Abstract: A semiconductor device includes a board, an electronic component, an evaluation component, a wiring, and a groove portion. The board includes a product area, a non-product area, and a boundary area between the product area and the non-product area. The electronic component is mounted in the product area. The evaluation component is mounted in the non-product area. The wiring electrically connects the electronic component and the evaluation component. The groove portion is formed in the boundary area of the board so as to overlap at least a part of the wiring in a plan view. The non-product area is surrounded by the groove portion and at least a portion of sides of the board.

Abstract: A method of testing an integrated circuit of a device is described. Air is allowed through a fluid line to modify a size of a volume defined between the first and second components of an actuator to move a contactor support structure relative to the apparatus and urge terminals on the contactor support structure against contacts on the device. Air is automatically released from the fluid line through a pressure relief valve when a pressure of the air in the fluid line reaches a predetermined value. The holder is moved relative to the apparatus frame to disengage the terminals from the contacts while maintaining the first and second components of the actuator in a substantially stationary relationship with one another. A connecting arrangement is provided including first and second connecting pieces with complementary interengaging formations that restricts movement of the contactor substrate relative to the distribution board substrate in a tangential direction.

Abstract: The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein a first microelectronic device having through-silicon vias may be stacked with a second microelectronic device and used in a bumpless build-up layer package.

Abstract: An electronic circuit has at least one first printed circuit board extending in a first plane, and at least one second printed circuit board extending in a second plane that extends in parallel to, and outside of, the first plane, and also has at least one first connector device, in electrical contact with the first printed circuit board, and a second connector device, in electrical contact with the second printed circuit board and arranged on a second printed circuit board side facing away from the first printed circuit board, both connector devices being designed together to receive an associated plug-in board and to electrically contact this plug-in board using both printed circuit boards, the first connector device being arranged, at least in part, on a second plane side facing away from the first printed circuit board.

Abstract: A probe insertion auxiliary and a method of probe insertion are provided. A light source illuminates holes on a lower die to make the position of the holes clear for an operator. The probe insertion auxiliary includes a bottom and a clamp pair disposed on the bottom. The clamp pair has two clamp parts. The two clamp parts define a slit for disposing a probe chassis. Furthermore, the two clamp parts and the bottom form a space. A light source is disposed inside the space for illuminating the holes.

Abstract: A method of manufacturing a light-emitting device includes a hole forming process for forming a through-hole that continues from a front surface to a back surface of a mounting substrate, a pattern forming process for continuously forming a circuit pattern on an inner surface of the through-hole in the mounting substrate, from an end portion of the through-hole on the front surface of the mounting substrate to a mounting portion of a light-emitting element, and on a periphery of the through-hole on the back surface of the mounting substrate, a mounting process for mounting the light-emitting element on the mounting portion, and a hot pressing process in that an inorganic material softened by heating is placed on the surface of the mounting substrate and is advanced into the through-hole while sealing the light-emitting element by pressing and bonding the inorganic material to the surface of the mounting substrate.

Abstract: Electrical components may be soldered to a printed circuit. The printed circuit may have an edge with an opening. Printed circuit contacts in the opening may be configured to form electrical connections with mating contacts on a flexible printed circuit or other external structure. A tester may test the electrical components by conveying signals through the contacts. Following testing, the external structure may be removed from the opening. The opening may then be filled with dielectric to isolate the printed circuit contacts. A printed circuit may have traces that extend under a ground on a surface of the printed circuit, may have edge test points formed from contacts that are cut in half when removing portions of the printed circuit, or may have through-mold vias that are formed through encapsulant over the electrical components.

Abstract: Methods and apparatus for testing unsingulated integrated circuits on a wafer include adapting a wafer prober for use with full-wafer-contacter disposed on the wafer. Some embodiments include placing wafer on a chuck of the prober, aligning the wafer to a full-wafer contacter incorporated in the wafer prober; removably attaching the wafer to the full wafer contacter, separating the wafer from the chuck, and making electrical contact to one or more integrated circuits of the wafer by making physical contact with a surface of the full-wafer contacter that faces away from the wafer.

Abstract: An electromechanical assembly includes a socket housing having a cavity for seating an integrated circuit and a first plurality of electrical contacts in the cavity to electrically connect an integrated circuit seated in the socket housing with a circuit board upon which the electromechanical assembly is mounted. The socket housing has a supporting body on a different plane than a bottom surface of the cavity. The socket housing has a second plurality of electrical contacts that form a first row across the supporting body and a third plurality of electrical contacts that form a second row across the supporting body. The socket housing has alignment elements. The electromechanical assembly also includes a card edge connector having slots that accept the alignment elements of the socket housing, a fourth plurality of electrical contacts that form a third row, and a fifth plurality of electrical contacts that form a fourth row.

Abstract: A testing apparatus includes a base mounted on a motherboard, an inserting unit mounted on the base, a movable unit secured to the inserting unit, and a driving device mounted between the movable unit and the base. The movable unit is driven to move by the driving device, thereby enabling the inserting unit to move to enable the expansion card to be inserted into the motherboard. The movable unit is driven to move by the driving device, thereby enabling the inserting unit to move to enable the expansion card to move out of the motherboard.

Abstract: A flexible stack package includes a first package and a second package. Each of the first and second packages includes a flexible layer, a chip embedded in the flexible layer, and a contact portion disposed on the chip to penetrate the flexible layer and exposed at a surface of the flexible layer. Each of the first and second packages includes a fixing portion and a wing portion. A first adhesion part is disposed between the fixing portion of the first package and the fixing portion of the second package to combine the first package with the second package. A first stretchable interconnector electrically connects or couples the contact portion of the first package to the contact portion of the second package.

Abstract: According to various embodiments, a method for processing a substrate may include: forming a dielectric layer over the substrate, the dielectric layer may include a plurality of test regions; forming an electrically conductive layer over the dielectric layer to contact the dielectric layer in the plurality of test regions; simultaneously electrically examining the dielectric layer in the plurality of test regions, wherein portions of the electrically conductive layer contacting the dielectric layer in the plurality of test regions are electrically conductively connected with each other by an electrically conductive material; and separating the electrically conductive layer into portions of the electrically conductive layer contacting the dielectric layer in the plurality of test regions from each other.

Abstract: Miniaturization and high-performance of a semiconductor device are promoted, which has a package on package (POP) structure in which a plurality of semiconductor packages is stacked in a multistage manner. A testing conductive pad for determining the quality of a conduction state of a microcomputer chip and a memory chip is arranged outside a conductive pad for external input/output and thereby the route of a wire that couples the microcomputer chip and the memory chip to the testing conductive pad is reduced in length. Further, the wire that couples the microcomputer chip and the memory chip to the testing conductive pad is coupled to a pad in the outer row among conductive pads in two rows to be coupled to the microcomputer chip.

Abstract: A method of testing a semiconductor device includes forming a test circuit over a semiconductor substrate. The test circuit includes a plurality of interconnects electrically connected to a set of device structures supported by the semiconductor substrate. A test, such as a gate stress or leakage current test, of each device structure is conducted with the test circuit. The plurality of interconnects are removed after conducting the test.

Abstract: A wafer seal ring may be formed on a first and/or a second wafer. One or both of the first and/or second wafers may have one or more dies formed thereon. The wafer seal ring may be formed to surround the dies of a corresponding wafer. One or more die seal rings may be formed around the one or more dies. The wafer seal ring may be formed to a height that may be approximately equal to a height of one or more die seal rings formed on the first and/or second wafer. The wafer seal ring may be formed to provide for eutectic or fusion bonding processes. The first and second wafers may be bonded together to form a seal ring structure between the first and second wafers. The seal ring structure may provide a hermetic seal between the first and second wafers.

Abstract: A cartridge, including a cartridge frame, formations on the cartridge frame for mounting the cartridge frame in a fixed position to an apparatus frame, a contactor support structure, a contactor interface on the contactor support structure, a plurality of terminals, held by the contactor support structure, for contacting contacts on a device, and a plurality of conductors, held by the contactor support structure, connecting the interface to the terminals.

Abstract: A wired circuit board includes a wire, and a terminal formed continuously to the wire to be electrically connected to an electronic element at one surface thereof in a thickness direction of the wired circuit board. The terminal includes, at the one surface thereof in the thickness direction, a projecting portion projecting toward one side thereof in the thickness direction, and a covering layer covering one end portion of the projecting portion in the thickness direction.

Abstract: An electronic assembly including a substrate, an electronic component, a fixture, and a housing. The substrate includes a first contact array. The electronic component includes a second contact array. The fixture includes an opening adapted to position the electronic component on the substrate and to connect the second contact array to the first contact array when the fixture is aligned at a first position on the substrate. The housing is adapted to hold the substrate populated with the electronic component. The housing includes a first conductive pathway adapted to connect from an external surface at the housing to the substrate in a serial continuous conductive path when the fixture is aligned at the first position on the substrate. The electronic assembly includes a sensing device connected to the continuous conductive path to detect the integrity of the electronic assembly.

Abstract: A bridging arrangement for coupling a first terminal to a second terminal includes a plurality of particles of a first type forming at least one path between the first terminal and the second terminal, wherein the particles of the first type are attached to each other; a plurality of particles of a second type arranged in a vicinity of a contact region between a first particle of the first type and a second particle of the first type, wherein at least a portion of the plurality of particles of the second type is attached to the first particle of the first type and the second particle of the first type.

Abstract: A semiconductor apparatus may include a semiconductor chip, and the semiconductor chip may include a first pad, a second pad, and a bump. The first pad may be configured to receive a signal from an external device, and the second pad may include first and second metal layers electrically isolated from each other. The bump may be stacked over the second pad, and may be configured to receive a signal from a controller chip.

Abstract: An electronic device includes an electronic component having terminals including a set of first terminals and a set of second terminals, a protective package embedding the electronic component, leads exposed from the protective package including a set of first leads and a set of second leads, for each first lead a first electrical connection inside the protection package between the first lead and a corresponding one of the first terminals, and for each second lead electrical connections inside the protective package each one between the second lead and a corresponding one of the second terminals. For each second lead the electronic component includes test structures, each being coupled between a corresponding one of the second terminals connected to the second lead and a corresponding test one of the first terminals connected to a test one of the first leads.

Abstract: An assembly for testing performance of a component includes a rotatable turret having component handling heads each of which can hold a component and a rotatable head assembly that includes a rotatable head having one or more nests. Each nest has an electrical contact and can receive a component that electrically connects to the nest's electrical contact. Each nest can hold a component that remains electrically connected to the electrical contact, as the head rotates. The rotatable head is adjacent to the turret to pass a component directly from a component handling head on the turret to a nest on the head. A processor is in electrical communication with the electrical contact(s) of the nests such that the processor can send command signals to a component held in a nest and receive response signals from the component. The processor determines the performance of the component from the response signals.

Abstract: A test structure including an array of microbumps electrically connecting a chip and a substrate, wherein a width of each microbump of the array of microbumps is equal to or less than about 50 microns (?m). The test structure further includes an interconnect structure connected to the array of microbumps. The test structure further includes an array of test pads around a periphery of the array of microbumps, wherein a test pad of the array of test pads is connected to a corresponding microbump of the array of microbumps through the interconnect structure. A width of the test pad is greater than a width of the corresponding microbump, and the test pad is adapted to be covered after circuit probing by a passivation material to prevent particle and corrosion issues.

Abstract: [Subject Matter] To provide a printed wiring board in which no warping occurs even if interlayer insulation layers without core material are laminated on a core substrate. [Solution(s)] To lower the thermal expansion coefficient (CTE) to 20˜40 ppm, inorganic particles are added to core substrate 30 formed by impregnating glass-cloth core material with glass-epoxy resin. Furthermore, thickness (a) of core substrate 30 is set at 0.2 mm, thickness (b) of upper-surface-side first interlayer insulation layer (50A) at 0.1 mm, and thickness (c) of lower-surface-side second interlayer insulation layer (50B) at 0.1 mm. In setting so, using thin core substrate 30 and interlayer insulation layers (50A, 50B) without core material, it is thought that warping does not occur in the printed wiring board.