Abstract: A semiconductor device assembly can include a first semiconductor device and an interposer. The interposer can include a substrate and through vias in which individual vias include an exposed portion and an embedded portion, the exposed portions projecting from one or both of the first surface and the second surface of the substrate, and the embedded portions extending through at least a portion of the substrate. The interposer can include one or more test pads, a first electrical contact, and a second electrical contact. The semiconductor device assembly can include a controller positioned on an opposite side of the interposer from the first semiconductor device and operably coupled to the interposer via connection to the second electrical contact.

Abstract: A film type package includes: a base film having first and second sides; a driver integrated circuit mounted on the base film; first connection pads disposed on a first area of the base film that is adjacent to the first side of the base film, and configured to be connected to a first external circuit; second connection pads disposed on a second area of the base film that is adjacent to the second side of the base film, and configured to be connected to a second external circuit; first signal lines disposed on the base film, and connecting the driver integrated circuit and the first connection pads; second signal lines disposed on the base film, and connecting the driver integrated circuit and the second connection pads; and a plurality of test lines extending from the driver integrated circuit to the first side of the base film.

Abstract: An integrated circuit component includes a semiconductor substrate, conductive pads, a passivation layer and conductive vias. The semiconductor substrate has an active surface. The conductive pads are located on the active surface of the semiconductor substrate and electrically connected to the semiconductor substrate, and the conductive pads each have a contact region and a testing region, where in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region. The passivation layer is located on the semiconductor substrate, where the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer. The conductive vias are respectively located on the contact regions of the conductive pads.

Abstract: A method of testing semiconductor devices includes placing a plurality of semiconductor devices in a carrier assembly and performing at least one testing operation on the plurality of semiconductor devices while they remain inside the carrier assembly.

Abstract: In a case where a semiconductor chip is mounted over a first package, 80 pads are coupled to 80 terminals of the package, and in a case where the semiconductor chip is mounted over a second package, 100 pads are coupled to 100 terminals of the second package. An internal circuit of the semiconductor chip operates as a microcomputer with 80 terminals in a case where electrodes are insulated from each other and operates as a microcomputer with 100 terminals in a case where the electrodes are shorted therebetween by an end part of a bonding wire. Therefore, a dedicated pad for setting the number of terminals of the packages is no longer required.

Abstract: A test pad structure may include a plurality of test pads and a plurality of connection leads. A plurality of the test pads may be sequentially arranged from a wiring pattern on a substrate and arranged in rows parallel with one another. The plurality of the test pads may include a first group of test pads having at least one pad arranged in a first row and a second group of test pads having at least two pads. A plurality of the connection leads may extend from end portions of the wiring pattern to be connected to the plurality of test pads. A plurality of the connection leads may include at least one inner lead passing between the at least two pads of the second group of the test pads arranged in a second row closest to the first group of the test pads. The at least one inner lead may be connected to at least one pad of the at least two pads of the second group of the test pads arranged in a third row next to the second row.

Abstract: A serial attached small computer system interface (SCSI) (SAS) interface output signal detecting apparatus includes an SAS female connector, an SAS male connector, and two subminiature version A (SMA) connectors. Each of the SAS female and male connectors includes first and second groups of data pins and a group of power pins. The power pins of the SAS female connector are connected to the power pins of the SAS male connector. The SMA connectors are connected to two data output pins of the second or first group of data pins of the SAS female connector in response to the first group of data pins of the SAS female connector being connected to the first group of data pins of the SAS male connector or the second group of data pins of the SAS female connector being connected to the second group of data pins of the SAS male connector.

Abstract: A method of topside only dual-side testing of an electronic assembly includes providing a singulated through substrate via (TSV) die flip chip attached to a die support including a package substrate. The TSVs on the TSV die extend from its frontside to contactable TSV tips on its bottomside. The TSVs on the frontside of the TSV die are coupled to embedded topside substrate pads on a top surface of the ML substrate. The die support includes lateral coupling paths between at least a portion of the embedded topside substrate pads and lateral topside pads on a topside surface of the die support lateral to the die area. The contactable TSV tips are contacted with probes to provide a first topside connection to the TSVs, and the lateral topside pads are contacted with probes to provide a second topside connection. Dual-side testing across the electronic assembly is performed using the first and second topside connections.