Abstract: A method for detecting defects in a semiconductor device including singulating a die having a substrate including a circuit region and an outer border, a plurality of detecting devices disposed over the substrate and located between the circuit region and the outer border, a first probe pad and a second probe pad electrically connected to two ends of each detecting device, and a seal ring located between the outer border of the die and the detecting devices. The method further includes probing the first probe pad and the second probe pad to determine a connection status of the detecting device, and recognizing a defect when the connection status of the detecting device indicates an open circuit.

Abstract: This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.

Abstract: A probe card device includes a printed circuit board (PCB), a space transformer, and a high-speed flexible printed circuit (FPC). The PCB includes a plurality of first connecting bodies coupled to a tester, and a plurality of second connecting bodies. The space transformer includes a plurality of connecting bodies disposed on a first surface of the space transformer and coupled to the plurality of second connecting bodies of the printed circuit board, a plurality of general contact pads disposed on a second surface of the space transformer and contacted with a plurality of first probes, and a plurality of high-speed contact pads disposed on the second surface of the space transformer and contacted with a plurality of second probes. The high-speed FPC has a first connecting terminal coupled to the tester, and a second connecting terminal coupled to the plurality of high-speed contact pads.

Abstract: An integrated circuit device, a semiconductor substrate, and a test system including the integrated circuit device are disclosed. The integrated circuit device includes a power terminal configured to receive a source voltage, a power via connected to the power terminal and passing through at least one of a number of layers, a number of inductive vias arranged apart from the power via and passing through at least one of the number of layers, a number of wirings connected to ends of at least some of the number of inductive vias and configured to form a coil wound in toroidal form together with the number of inductive vias, around the power via, and a test terminal configured to output an induced voltage in the coil externally of the integrated circuit device, in response to the supply of the source voltage.

Abstract: The present application discloses a method for fabricating a semiconductor device. The method includes providing a substrate, forming a circuit layer on the substrate and including a functional block on the substrate, and a test pad on the substrate and distal from the functional block, forming a through semiconductor via physically and electrically coupled to the test pad, and forming a redistribution structure on the circuit layer and including a first conductive portion over the functional block and electrically coupled to the functional block, and a second conductive portion over the test pad and electrically coupled to the test pad through the through semiconductor via.

Abstract: A semiconductor apparatus includes a data input buffer configured to generate write data by receiving data that is input through a data input/output unit during a write operation section and configured to generate an output level detection signal by detecting a voltage level of the data I/O unit during a read operation section.

Abstract: This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a circuit layer positioned on the substrate and including a functional block positioned on the substrate, and a test pad positioned on the substrate and distal from the functional block, a redistribution structure positioned on the circuit layer and including a first conductive portion positioned over the functional block and electrically coupled to the functional block, and a second conductive portion positioned over the test pad and electrically coupled to the test pad, and a through semiconductor via physically and electrically coupled to the test pad.

Abstract: A cartridge, including a cartridge frame, formations on the cartridge frame for mounting the cartridge frame in a fixed position to an apparatus frame, a contactor support structure, a contactor interface on the contactor support structure, a plurality of terminals, held by the contactor support structure, for contacting contacts on a device, and a plurality of conductors, held by the contactor support structure, connecting the interface to the terminals.

Abstract: Apparatuses, systems and methods associated with integrated circuit packages with integrated test circuitry for testing of a channel between dies are disclosed herein. In embodiments, an integrated circuit (IC) package may include a first die, a second die, and a channel that couples the first die to the second die. The first die may include a transmitter, test circuitry coupled between the transmitter and the channel, wherein the test circuitry is to control charge and discharge of the channel, and a receiver coupled to the channel. The receiver may determine a voltage of the channel during charge and discharge of the channel, and output an indication of the voltage. Other embodiments may be described and/or claimed.

Abstract: A through-silicon via (TSV) detecting circuit, a detecting method, and an integrated circuit having the same are disclosed. The TSV detecting circuit includes: an input circuit including a first switching circuit, the first switching circuit comprising a control terminal coupled to a first detection control signal, a first terminal coupled to a first power signal, and a second terminal coupled to a first terminal of a TSV, wherein the first switching circuit is configured to be turned on in response to the first detection control signal to transmit a first power signal to the first terminal of the TSV; and a comparison circuit comprising a first input coupled to a second terminal of the TSV, and a second input coupled to a reference signal, wherein the comparison circuit is configured to compare a signal of the second terminal of the TSV and the reference signal.

Abstract: Provided a method including applying a Fourier Transform to an AC current waveform measured to perform conversion thereof to a frequency domain; adjusting entire phase components of frequency spectra obtained as a result of the Fourier Transform, such that a phase component of an AC power supply frequency becomes zero; and applying an inverse Fourier Transform to the frequency spectra with the entire phase components thereof adjusted to obtain a current waveform in a time domain.

Abstract: A memory test method for being implemented by storing corresponding test result data and test parameter data into memory chips when a burn-in test, a high temperature test, a low temperature test, and a normal temperature test are performed on the memory chips. A memory test method for being implemented by storing the corresponding test result data and the test parameter data into the memory chips after the memory chips finish the burn-in test, the high temperature test, the low temperature test, and the normal temperature test. The memory chips can internally store the test result data and the test parameter data after finishing tests through the memory test method of the present disclosure so that relevant personnel can read data to easily trace back test history of the memory chips.

Abstract: A method of testing a semiconductor device may include preparing a semiconductor substrate in which the semiconductor substrate includes a test element group including first and second test circuits, measuring first and second leakage currents in the first and second test circuits, respectively, and calculating leakage components by comparing the first and second leakage currents. Each of the first and second test circuits may include an active region, which is an upper portion of the semiconductor substrate, a gate electrode, which is configured to cross the active region and to extend in a first direction, and an active contact, which is on the active region, is spaced apart from the gate electrode, and extends in the first direction. The second test circuit may further include a first gate contact that is connected to the gate electrode and overlaps the active region in a vertical direction perpendicular to the substrate.

Abstract: This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.

Abstract: A device includes a test pad on a chip. A first microbump has a first surface area that is less than a surface area of the test pad. A first conductive path couples the test pad to the first microbump. A second microbump has a second surface area that is less than the surface area of the test pad. A second conductive path couples the test pad to the second microbump.

Abstract: A method includes training an artificial neural network with training data that comprises a sets of design parameter values for design parameters for circuit traces in a high speed communication link, determining an output formula that relates a sets of design parameters to a corresponding output parameter for the circuit traces in response to training the artificial neural network, running the output formula using a second set of design parameter values to obtain a corresponding set of output parameters for the circuit traces, determining that the corresponding set of output parameters differ from a set of modeled output parameters by less than a predefined percentage, and fabricating a circuit trace in a printed circuit board based upon the output formula in response to determining that the corresponding set of output parameters differ from the set of modeled output parameters by less than the predefined percentage.

Abstract: A method for detecting voids in a metal line of a semiconductor device die includes: scanning an electron beam upon a selected location on the die containing the metal line; determine gray levels in an image produced by collected electrons of the electron beam backscattered from the selected location on the die; and identifying one or more voids in the metal line based on differences between the gray levels in the image.

Abstract: This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.

Abstract: A Deep Belief Network (DBN) feature extraction-based analogue circuit fault diagnosis method comprises the following steps: a time-domain response signal of a tested analogue circuit is acquired, where the acquired time-domain response signal is an output voltage signal of the tested analogue circuit; DBN-based feature extraction is performed on the acquired voltage signal, wherein learning rates of restricted Boltzmann machines in a DBN are optimized and acquired by virtue of a quantum-behaved particle swarm optimization (QPSO); a support vector machine (SVM)-based fault diagnosis model is constructed, wherein a penalty factor and a width factor of an SVM are optimized and acquired by virtue of the QPSO; and feature data of test data are input into the SVM-based fault diagnosis model, and a fault diagnosis result is output, where the feature data of the test data is generated by performing the DBN-based feature extraction on the test data.

Abstract: The present disclosure provides a method for characterizing ohmic contact electrode performance of a semiconductor device. The method comprises: preparing two sets of testing patterns on a semiconductor device; testing resistance values of the two sets of testing patterns respectively; calculating a sheet resistance of an ohmic contact area according to the obtained resistance values; and evaluating the ohmic contact electrode performance of the semiconductor device according to the sheet resistance of the ohmic contact electrode.

Abstract: A multi-chip module includes a first semiconductor component including a first set of connections having a first pitch dimension and at least a second set of connections having a second pitch dimension, wherein the first pitch dimension is smaller than the second pitch dimension. The multi-chip module further includes a second semiconductor component interconnected with the first set of connections of the first semiconductor component. The multi-chip module further includes at least a third semiconductor component interconnected with the second set of connections of the first semiconductor component and wherein a surface of the third semiconductor component is adhered to a surface of the second semiconductor component, wherein the surfaces at least partially overlap one another.

Abstract: A device includes a test pad on a chip. A first microbump has a first surface area that is less than a surface area of the test pad. A first conductive path couples the test pad to the first microbump. A second microbump has a second surface area that is less than the surface area of the test pad. A second conductive path couples the test pad to the second microbump.

Abstract: This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.

Abstract: A device for pressing an electronic component with different downward forces includes a first downward-pressure generating device, a depressing head, a second downward-pressure generating device and a depressing piston. The first downward-pressure generating device has the depressing head to apply a first downward pressure to the test socket and a portion of the electronic component. The second downward-pressure generating device has the depressing piston to apply a second downward pressure downward to another portion on the electronic component, so that the electronic component can couple electrically with a plurality of probe of the test socket. Thereupon, at least two downward-pressure generating devices are included to provide at least two different downward pressures to the electronic component solely or simultaneously to the electronic component and the testing equipment, such that specific downward-pressure requirements by precision electronic components can be fulfilled.

Abstract: Apparatuses and methods for temperature and process corner sensitive control of power gated domains are described. An example apparatus includes an internal circuit; a power supply line; and a power gating control circuit which responds, at least in part, to a first change from a first state to a second state of a control signal to initiate supplying a power supply voltage from the power supply line to the internal circuit, and continue supplying the power supply voltage from the power supply line to internal circuit for at least a timeout period from a second change from the second state to the first state of the control signal, in which the timeout period represent temperature dependency.

Abstract: Embodiments are directed to a method Embodiments are directed to a test structure of a fin-type field effect transistor (FinFET). The test structure includes a first conducting layer electrically coupled to a dummy gate of the FinFET, and a second conducting layer electrically coupled to a substrate of the FinFET. The test structure further includes a third conducting layer electrically coupled to the dummy gate of the FinFET, and a first region of the FinFET at least partially bound by the first conducting layer and the second conducting layer. The test structure further includes a second region of the FinFET at least partially bound by the second conducting layer and the third conducting layer, wherein the first region comprises a first dielectric having a first dimension, and wherein the second region comprises a second dielectric having a second dimension greater than the first dimension.

Abstract: A diagnostic system includes a location extractor, a file generator, and a chip diagnostic tool. The location extractor is arranged to extract at least a coordinate of at least one component in an intellectual property design layout of an integrated circuit design layout according to at least one tagging text labeling the at least one component in the intellectual property design layout. The file generator is arranged to generate a format file according to the at least coordinate. The chip diagnostic tool is arranged to scan a physical intellectual property circuit in a physical integrated circuit to determine a defect component in the physical intellectual property circuit according to the format file. The physical intellectual property circuit corresponds to the intellectual property design layout, and the physical integrated circuit corresponds to the integrated circuit design layout.

Abstract: This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.

Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

Abstract: A chip is provided, where the chip is formed by packaging at least two dies, and the at least two dies form at least one die group. The die group includes a first die and a second die. A first processing unit and n groups of ports are disposed on the first die, and a second processing unit and m groups of ports are disposed on the second die. The first processing unit is configured to: switch at least one group of first type ports in the n groups of ports from input to output and switch a second type port that is in the m groups of ports and that is coupled to each group of the first type ports from output to input.

Abstract: This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.

Abstract: A semiconductor device includes: a semiconductor element; a first bonding pad formed on a surface of the semiconductor element; a test pad formed on the surface of the semiconductor element separately from the first bonding pad and configured to be visually distinguishable from the first bonding pad; and a first bonding member connected to the first bonding pad and used for external electrical connection.

Abstract: An embodiment device package includes first die and one or more redistribution layers (RDLs) electrically connected to the first die. The one or more RDLs extend laterally past edges of the first die. The device package further includes one or more second dies bonded to a first surface of the one or more RDLs and a connector element on the first surface of the one or more RDLs. The connector element has a vertical dimension greater than the one or more second dies. A package substrate is bonded to the one or more RDLs using the connector element, wherein the one or more second dies is disposed between the first die and the package substrate.

Abstract: This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.

Abstract: To improve the reliability of a semiconductor device. A chip mounting portion TAB5 is arranged to be shifted to the +x direction side. Further, a gate electrode pad of a semiconductor chip CHP1 (LV) and a pad of a semiconductor chip CHP3 are electrically coupled by a wire W1a and a wire W1b through a relay lead RL1. Likewise, a gate electrode pad of a semiconductor chip CHP1 (LW) and the pad of the semiconductor chip CHP3 are electrically coupled by a wire W1c and a wire W1d through a relay lead RL2. At this time, the structures of parts of the relay leads RL1 and RL2, which are exposed from a sealing body MR are different from the structures of respective parts exposed from the sealing body MR, of a plurality of leads LD1 and LD2 which function as external terminals.

Abstract: The invention relates to a tester apparatus of the kind including a portable supporting structure for removably holding and testing a substrate carrying a microelectronic circuit. An interface on the stationary structure is connected to the first interface when the portable structure is held by the stationary structure and is disconnected from the first interface when the portable supporting structure is removed from the stationary structure. An electrical tester is connected through the interfaces so that signals may be transmitted between the electrical tester and the microelectronic circuit to test the microelectronic circuit.

Abstract: A design-for-test (DFT) architecture for testing a three dimensional (3D) integrated circuit, may comprise a two dimensional (2D) silicon layer n?1 and a 2D silicon layer n connected together with a through silicon via (TSV) having a first side and a second side; scannable latch circuits on said first side and said second side of said TSV, wherein said scannable latch circuits: control flow of data between said layer n?1 and said layer n and allow said TSV to be verified; allow launch and capture clocks to be applied with variable delay in order to perform an alternating current delay fault test between said layer n?1 and said layer n; and have a quiescent state supply current (IDDq) test function built in which allows selection of an input load for a unidirectional signal connection between said layer n?1 and said layer n.

Abstract: A test structure for electron beam inspection and a method for defect determination using electron beam inspection are provided. The test structure for electron beam inspection includes a semiconductor substrate, at least two conductive regions disposed on the semiconductor substrate, a connection structure disposed on the two conductive regions, and a cap dielectric layer disposed on the connection structure. The method for defect determination using the electron beam inspection includes the following steps. An electron beam inspection is preformed to a test structure with an instant detector and a lock-in amplifier. Signals received by the detector within a period of time are amplified by the lock-in amplifier. A defect in the test structure is determined by monitoring the signals received by the detector and amplified by the lock-in amplifier. The inspection accuracy is improved by the test structure and the method for defect determination in the present invention.

Abstract: A test control port (TCP) includes a state machine SM, an instruction register IR, data registers DRs, a gating circuit and a TDO MX. The SM inputs TCI signals and outputs control signals to the IR and to the DR. During instruction or data scans, the IR or DRs are enabled to input data from TDI and output data to the TDO MX and the top surface TDO signal. The bottom surface TCI inputs may be coupled to the top surface TCO signals via the gating circuit. The top surface TDI signal may be coupled to the bottom surface TDO signal via TDO MX. This allows concatenating or daisy-chaining the IR and DR of a TCP of a lower die with an IR and DR of a TCP of a die stacked on top of the lower die.

Abstract: This disclosure relates generally to an electrical circuit and method. A capacitive element can be configured to be coupled in series with an electronic package component. A path resistance can be electrically coupled to the capacitive element. A driver can be configured to electrically charge the capacitive element. A voltage detector can be coupled to the capacitive element and configured to identify a condition of the electronic package component based on a measured voltage of the capacitive element.

Abstract: A method may include interleaving, by an optical device, a set of bits of a first channel with a set of bits of a second channel. The first channel may include first forward error correction (FEC) data associated with the set of bits of the first channel and the second channel may include second FEC data associated with the set of bits of the second channel. The method may further include transmitting first information via the first channel and second information via the second channel. The first information may include a portion of the set of bits of the first channel, a portion of the set of bits of the second channel, and the first FEC data. The second information may include another portion of the set of bits of the first channel, another portion of the set of bits of the second channel, and the second FEC data.

Abstract: Systems and methods for determining a capacitance on a device-under-test (“DUT”). An example implementation includes a voltage signal generator that generates a voltage signal alternating between a high voltage and a low voltage at regular time intervals. The voltage signal generator causes a DUT current to flow in the DUT. The DUT current comprises a leakage current and a capacitance measurement current in response to the voltage signal. A current signal generator receives the DUT current from the DUT. The current signal generator generates a cancellation current signal alternating between high and low values at the regular time intervals of the voltage signal such that the cancellation current signal cancels the leakage current through the DUT. A signal measurement circuit receives the capacitance measurement current remaining after the leakage current is canceled to generate an output voltage having an output voltage value used to determine a capacitance of the DUT.

Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

Abstract: A system for programming integrated circuit (IC) dies formed on a wafer includes an optical transmitter that outputs a digital test program as an optical signal. At least one optical sensor (e.g., photodiode) is formed with the IC dies on the wafer. The optical sensor detects and receives the optical signal. A processor formed on the wafer converts the optical signal to the digital test program and the digital test program is stored in memory on the wafer in association with one of the IC dies. The optical transmitter does not physically contact the dies, but can flood an entire surface of the wafer with the optical signal so that all of the IC dies are concurrently programmed with the digital test program.

Abstract: A design-for-test (DFT) architecture for testing a three dimensional (3D) integrated circuit, may comprise a two dimensional (2D) silicon layer n?1 and a 2D silicon layer n connected together with a through silicon via (TSV) having a first side and a second side; scannable latch circuits on said first side and said second side of said TSV, wherein said scannable latch circuits: control flow of data between said layer n?1 and said layer n and allow said TSV to be verified; allow launch and capture clocks to be applied with variable delay in order to perform an alternating current delay fault test between said layer n?1 and said layer n; and have a quiescent state supply current (IDDq) test function built in which allows selection of an input load for a unidirectional signal connection between said layer n?1 and said layer n.

Abstract: Embodiments relate to sensor device configurations. In one embodiment, a sensor device comprises a bias magnet, a field sensor die, a first set of one or more magnetic field sensor elements, a second set of one or more magnetic field sensor elements, a memory, and circuitry. The sensor device is configured to combine the sensed magnitudes from each of the magnetic field sensor elements of the first set to obtain a first set output, trim the sensed magnitudes from each of the one or more magnetic field sensor elements of the second set with one of the set of trim values to obtain a second set output, and combine the second set output with the first set output to provide an output signal.

Abstract: This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.

Abstract: This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.

Abstract: An apparatus includes circuits, a field line configured to generate a magnetic field based on an input, a sensing module configured to determine a parameter of each circuit, and a magnetic field direction determination module configured to determine an angular orientation of the apparatus relative to an external magnetic field based on the parameter. Each circuit includes multiple magnetic tunnel junctions. Each magnetic tunnel junction includes a storage layer having a storage magnetization direction and a sense layer having a sense magnetization direction configured based on the magnetic field. Each magnetic tunnel junction is configured such that the sense magnetization direction and a resistance of the magnetic tunnel junction vary based on the external magnetic field. The parameter varies based on the resistances of the multiple magnetic tunnel junctions. The magnetic field direction determination module is implemented in at least one of a memory or a processing device.