Abstract: In some examples, apparatus comprises a multiplexer (MUX) adapted to be coupled to a set of battery cells and configured to provide a voltage of a different battery cell in the set of battery cells based on a MUX control signal. Apparatus comprises a comparator coupled to the MUX and configured to compare a MUX output signal to a threshold voltage to provide a comparator output signal. Apparatus comprises a digital control circuit configured to provide the MUX control signal to the MUX, to store the comparator output signal, and to use a logic AND gate to provide an AND gate output signal based on the stored comparator output signal.

Abstract: An assembled battery monitoring device in the present disclosure includes: an excitation signal processor generates a excitation signal by processing an in-phase signal of an orthogonal reference signal generated by a signal generator; a current exciter generates an excitation current based on the excitation signal according to voltage signals, and energizes a battery cell; and an impedance measurer measures an AC impedance of the battery cell based on the excitation current measured by the current measurer and a voltage of the battery cell measured by the voltage measurer.

Abstract: A method for monitoring an online state of a bonding wire of an Insulated Gate Bipolar Translator (IGBT) module comprises the following steps: Step 1, constructing a full bridge inverter circuit and an online measuring circuit and connecting two input ends of the online measuring circuit to a collecting electrode and an emitting electrode of an IGBT power module of the full bridge inverter circuit to realize a connection of the full bridge inverter circuit and the online measuring circuit; Step 2, establishing a three-dimensional data model of a healthy IGBT; Step 3, establishing a three-dimensional data model of the IGBT with a broken bonding wire; Step 4, optimizing a least squares support vector machine by adopting a genetic algorithm; and Step 5, estimating states of the three-dimensional data models obtained in the Step 2 and the Step 3 by utilizing the optimized least squares support vector machine.

Abstract: The disclosure relates to an RFIC apparatus, and more particularly, to an RFIC circuit having a test circuit, a test apparatus, and a test method thereof. Further, the disclosure relates to a method for estimating or determining a DC gain using a test apparatus and an RF circuit in a DC/AC test stage, and detecting defects of the RF circuit based on the estimated or determined DC gain.

Abstract: A testkey includes two switching circuits and two compensation circuits. The first switching circuit transmits a test signal to a first DUT when the first DUT is being tested and functions as high impedance when the first DUT is not being tested. The second switching circuit transmits the test signal to a second DUT when the second DUT is being tested and functions as high impedance when the second DUT is not being tested. When the first DUT is not being tested and the second DUT is being tested, the first compensation circuit provides first compensation current for reducing the leakage current of the first switching circuit. When the first DUT is being tested and the second DUT is not being tested, the second compensation circuit provides second compensation current for reducing the leakage current of the second switching circuit.

Abstract: In an embodiment, a method for testing a functional integrity of a transistor component, the method includes causing a first change of a charge state of an internal capacitance between control terminals of the transistor component; determining a capacitance value of the internal capacitance based on the first change of the charge state; causing a second change of the charge state of the internal capacitance; and evaluating a resistance value of an internal resistance between the control terminals based on the determined capacitance value and the second change of the charge state.

Abstract: A test verification circuit is described herein for verifying proper operation of a tested circuit, such as a voltage hazard warning circuit, using an N-channel MOSFET configured for switching ON and OFF the test verification circuit during a power outage, and a voltage source that provides an input voltage to the N-channel MOSFET from a conserved power supply. The N-channel MOSFET provides temporary power from a conserved power supply to the test verification circuit upon activation by a user during a power outage, and the test verification circuit determines whether the tested circuit has been de-energized, remains energized, or there remains inadequate power to complete the test.

Abstract: Aspects of the present application are directed to an automated test equipment (ATE) and methods for operating the same for testing high-power electronic components. The inventor has recognized and appreciated an ATE that provides both high-power alternating-current (AC) and direct-current (DC) testing in a single test system can lead to high throughput testing for high-power components with reduced system hardware complexity and cost. Aspects of the present application provide a synchronized inductor switch module and both a high-precision digitizer and a high-speed digitizer for capturing DC and AC characteristics of a high-power transistor.

Abstract: RF (Radio Frequency, typically 500 MHz to 18 GHz) microstrip transistor test fixture which includes impedance transforming microstrip sections to pre-match the device (DUT) and wideband bidirectional signal couplers able to detect forward and reflected power waves and feed into an amplitude and phase measuring signal analyzer (such as a vector network analyzer VNA). Impedance pre-matching in the fixture allows reaching impedances (tuning) down to below 1? and power-match the power transistors (DUT), whereas the tuners alone can barely reach impedances of 5? at the DUT reference plane. Placing the couplers on transforming sections close to the DUT also allows for detection of the travelling signal waves with the smallest possible disturbance.

Abstract: The invention relates to a monitoring unit configured for monitoring a power converter of a wind turbine, the monitoring unit comprising: electric connection means configured for connecting the monitoring unit to one or more electric converter components, a cold area comprising a data communication interface, and one or more hot areas dedicated to obtain measurements from the one or more electric converter components.

Abstract: A driver circuit associated with a power electronic system is disclosed. The driver circuit comprises a gate driver circuit configured to drive a switching circuit comprising a plurality of switches in parallel, each switch comprising a respective source bondwire. The driver circuit further comprises a bondwire fault detection circuit comprising a gate charge estimation circuit configured to measure a parameter of the switching circuit comprising a gate charge of the switching circuit or a parameter indicative of the gate charge associated with the switching circuit. The bondwire fault detection circuit further comprises a detection circuit configured to detect a fault associated with at least one source bondwire of the switching circuit, based on the measured parameter of the switching circuit.

Abstract: A method for providing a miniature vector magnetometer includes embedding a micron-sized diamond nitrogen-vacancy (DNV) crystal into a bonding material. The bonding material including the embedded micron-sized DNV crystal is cured to form a micro-DNV sensor. A micro-DNV assembly is formed by integrating the micro-DNV sensor with a micro-radio-frequency (RF) source, a micron-sized light source, a reference bias magnet, and one or more micro-photo detectors. The micro-DNV assembly is operable to perform vector magnetometry when positioned in an external magnetic field.

Abstract: An apparatus provides precision measurement of voltage drop across a semiconductor switching element of a subsea device.

Abstract: The invention regards an method for estimating the end of lifetime for a power semiconductor device, such as an IGBT power module, comprising the steps of; establishing the temperature of the power semiconductor device, determining the voltage drop over the power semiconductor device for at least one predetermined current where the current is applied when the power semiconductor device is not in operation, wherein the end of lifetime is established dependent on the change in a plurality of determined voltage drops.

Abstract: In a semiconductor device, two series connections are arranged to be connected between respective split emitter electrodes and a gate electrode with Zener diode units connected in series to respective resistors, with the cathode sides thereof directed to the gate electrode side. The numbers of the Zener diodes in the Zener diode units in the respective series connections are different between the respective Zener diode units. Thus, a semiconductor device can be provided which is capable of detecting an open failure of a bonding wire regardless of the number of a plurality of the bonding wires connected in parallel, by a simple electrical test to make it possible to reliably sort out a semiconductor device with a wire open failure at an early stage.

Abstract: In an impedance measurement system, a reference impedance (2) to be measured is periodically connected and disconnected by means of switch (3) in parallel to the unknown impedance (1) to be measured. The thus generated amplitude modulation of the measurement current is demodulated, and the amplitude of the demodulated signal is indicative of the reference impedance to be measured. Using a low frequency modulation of the reference impedance enables to measure the impedance of the reference impedance without disconnecting the unknown impedance.

Abstract: A voltage detection circuit comprises a reference resistor including a terminal for receiving a first voltage; a reference transistor including a control terminal for receiving a second voltage; a comparator, including a first input terminal for receiving a converted voltage and a second input terminal for receiving the second voltage, for generating an output voltage; and a voltage dropping circuit series, comprising a plurality of voltage dropping circuits connected in a series, for converting an input voltage into the converted voltage; wherein the comparator indicates whether the input voltage matches a specific multiple of a voltage difference between the first voltage and the second voltage, and the specific multiple relates to a number of the plurality of voltage dropping circuits.

Abstract: In one general aspect, an apparatus can include an energy storage device configured to store energy during an unclamped inductive switching test of a target device, and a switch device configured to shunt at least a portion of energy away from the target device in response to the target device changing from a breakdown state to a failure state.

Abstract: A circuit structure of a test-key and a test method thereof are provided. The circuit structure comprises a plurality of transistors, a first conductive contact, a plurality of second conductive contacts and a plurality of third conductive contacts. The transistors are arranged in a matrix. The first conductive contact is electrically connected to one source/drain of each transistor in each column of the matrix. Each second conductive contact is electrically connected to the other source/drain of each transistor in a corresponding column of the matrix. Each third conductive contact is electrically connected to the gate of each transistor in a corresponding row of the matrix. In the method, a plurality of driving pulses are provided to the third conductive contacts in sequence, and a plurality of output signals are read from the second conductive contacts to perform an element-character analyzing operation when a row of the transistors is turned on.

Abstract: Photo-field-effect transistor devices and associated methods are disclosed in which a photogate, consisting of a quantum dot sensitizing layer, transfers photoelectrons to a semiconductor channel across a charge-separating (type-II) heterointerface, producing a sustained primary and secondary flow of carriers between source and drain electrodes. The light-absorbing photogate thus modulates the flow of current along the channel, forming a photo-field effect transistor.

Abstract: A test circuit includes a first test circuit. The first test circuit includes a first light-emitting diode (LED) and a first resistor. An anode of the first LED is connected to a power supply. A cathode of the first LED is connected to a collector of a bipolar junction transistor (BJT) through the first resistor. An emitter of the BJT is grounded. A base of the BJT is connected to the power supply. A type of the BJT can be determined according to status of the first LED.

Abstract: An assembly including an insulated gate bipolar transistor (IGBT) is provided. The IGBT is coupled with a gate driver for receiving a gating signal to drive the IGBT and providing a feedback signal of the IGBT which indicates a change of a collector-emitter voltage of the IGBT. The assembly further includes a failure mode detection unit for determining whether the IGBT is faulted based on a timing sequence of the gating signal and feedback signal. The failure mode detection unit is capable of differentiating fault types including a gate driver fault, a failed turn-on fault, a short-circuit fault, a turn-on over-voltage fault and a turn-off over-voltage fault. Accordingly, an IGBT failure mode detection method is also provided.

Abstract: Circuits for performing four terminal measurement point (IMP) testing of devices under test (DUT) is provided. The DUT and the circuit is to be defined on a semiconductor chip. The circuit includes a DUT having a first terminal and a second terminal, where the first terminal of the DUT is connectable to a first terminal measurement point and a third terminal measurement point, and the second terminal of the DUT is connectable to a second terminal measurement point and a fourth terminal measurement point. A first transistor is provided to select access to the first terminal measurement point, a second transistor is provided to select access to the third terminal measurement point, a third transistor is provided to select access to the second terminal measurement point; and a fourth transistor is provided to select access to the fourth terminal measurement point.

Abstract: An object is to provide a measuring method with high reproducibility in a bias-temperature stress test of a transistor in which an oxide semiconductor is used for a semiconductor layer. Provided is a measuring method of a transistor, which includes the steps of disposing a transistor in which an oxide semiconductor is used for a semiconductor layer in a measurement room having a light-blocking property, introducing dry air, nitrogen, or argon into the measurement room, and applying a predetermined voltage to a gate electrode of the transistor in the measurement room kept under an atmosphere where the dew point is greater than or equal to ?110° C. and less than or equal to ?60° C., whereby the amount of change in threshold voltage over time is measured.

Abstract: A test apparatus that tests a device under test, including a power supply section that supplies the device under test with power, a comparing section that detects a characteristic value indicating a state of the device under test and compares the characteristic value to a predetermined threshold value, a cutoff section that cuts off the power supplied from the power supply section to the device under test, based on a result of the comparison by the comparing section, and a control section that changes at least one of the threshold value of the comparing section and a detection timing at which the characteristic value is detected.

Abstract: A method for testing trap density in a gate dielectric layer of a semiconductor device having no substrate contact is provided in the invention. A source and a drain of the device are bilateral symmetric, and probes and cables of a test instrument connecting to the source and the drain are bilateral symmetric. Firstly, bias settings at the gate, the source and the drain are controlled so that the device is under an initial state that an inversion layer is not formed and traps in the gate dielectric layer impose no confining effects on charges.

Abstract: A method of manufacturing a silicon carbide (SiC) bipolar junction transistor (BJT) and a SiC BJT are provided. The SiC BJT comprises an emitter region, a base region and a collector region. The collector region is arranged on a substrate having an off-axis orientation of about 4 degrees or lower. Further, a defect termination layer (DTL) is arranged between the substrate and the collector region. A thickness and a doping level of the DTL are configured to terminate basal plane dislocations in the DTL and reduce the growth of defects from the DTL to the collector region. At least some of the embodiments are advantageous in that SiC BJTs with improved stability are provided. Further, a method of evaluating the degradation performance of a SiC BJT is provided.

Abstract: Provided is a low-cost and high-efficient system for measuring reliability of an electronic device. According to the present invention, a single input power source for applying power to an input terminal of a plurality of electronic device samples and a single output power source for applying power to an output terminal of the plurality of electronic device samples are provided. Further, an input switch having first switches of which the number corresponds to the number of the plurality of electronic device samples, the input switch being installed between the input power source and the input terminal so that the first switches are selectively switched to apply input power; and an output switch having second switches of which the number corresponds to the number of the plurality of electronic device samples, the output switch being installed between the output power source and the output terminal so that the second switches are selectively switched to apply output power are provided.

Abstract: A system for testing the existing protection schemes of a power converter. The system simulates the voltage regulator producing a voltage level below an under-voltage threshold. The system simulates the voltage regulator producing a voltage level above an over-voltage threshold. The system simulates a short in the power converter pulling down the input bus. The system simulates a short in the power converter pulling down the output bus. The system measures the system responses to these simulations against responses of a properly operating system and determines if the power converter's protection schemes are operating correctly.

Abstract: A semiconductor apparatus (IPD) includes a set value storage unit that stores a set value determined based on an initial characteristic value of the IPD, and a detector that detects characteristic degradation of the IPD based on a characteristic value of the IPD at given timing and the set value stored in the set value storage unit. Further, a method of detecting characteristic degradation of a semiconductor apparatus (IPD) includes storing a set value determined based on an initial characteristic value of the IPD, and detecting characteristic degradation of the IPD based on a characteristic value of the IPD at given timing and the stored set value.

Abstract: A method of manufacturing a silicon carbide (SiC) bipolar junction transistor (BJT) and a SiC BJT are provided. The SiC BJT comprises an emitter region, a base region and a collector region. The collector region is arranged on a substrate having an off-axis orientation of about 4 degrees or lower. Further, a defect termination layer (DTL) is arranged between the substrate and the collector region. A thickness and a doping level of the DTL are configured to terminate basal plane dislocations in the DTL and reduce the growth of defects from the DTL to the collector region. At least some of the embodiments are advantageous in that SiC BJTs with improved stability are provided. Further, a method of evaluating the degradation performance of a SiC BJT is provided.

Abstract: Systems, methods and devices which utilize Spread Spectrum Time Domain Reflectometry (SSTDR) techniques to measure degradation of electronic components are provided. Such measurements may be implemented while the components “live” or otherwise functioning within an overall system. In one embodiment, monitoring a power converter in a high power system is accomplished. In this embodiment, degradation of components within the power converter (e.g. metal-oxide-semiconductor field-effect transistors (MOSFETs), capacitors, insulated-gate bipolar transistors (IGBTs), and the like) may be monitored by processing data from reflections of an SSTDR signal to determine changes in impedance, capacitance, or any other changes that may be characteristic of components degrading. For example, an aging MOSFET may experience an increase of drain to source resistance which adds additional resistance to a current path within a power converter.

Abstract: In a semiconductor device, two series connections are arranged to be connected between respective split emitter electrodes and a gate electrode with Zener diode units connected in series to respective resistors, with the cathode sides thereof directed to the gate electrode side. The numbers of the Zener diodes in the Zener diode units in the respective series connections are different between the respective Zener diode units. Thus, a semiconductor device can be provided which is capable of detecting an open failure of a bonding wire regardless of the number of a plurality of the bonding wires connected in parallel, by a simple electrical test to make it possible to reliably sort out a semiconductor device with a wire open failure at an early stage.

Abstract: A wafer test method of a power switch wherein a main IGBT and a current detecting IGBT that detects a current value of the main IGBT are integrally formed on the same semiconductor substrate is such that there is provided resistance means that causes an emitter current of the current detecting IGBT to flow through an emitter terminal of the main IGBT, the main IGBT and current detecting IGBT are energized simultaneously, thereby applying a constant current to a common collector terminal of the main IGBT and current detecting IGBT, and a current ratio (main current/detected current) between a main current of the main IGBT and a detected current of the current detecting IGBT is calculated from the current flowing through the current detecting IGBT, obtained from the voltage across the resistance means, and the constant current.

Abstract: Provided is a power cycle test apparatus that eliminates the need to measure a thermal resistance in a power cycle test and that pursues power saving in the evaluation of IGBT reliability by exactly applying a required thermal stress through the automatic adjustment of a stress current. The power cycle test apparatus performs a power cycle test for an IGBT to be tested by applying a thermal stress to the IGBT to be tested through the intermittent application of a stress current thereto. The apparatus applies the stress current to the IGBT to be tested and thereafter applies a current for measurement to the IGBT to be tested to measure a collector-emitter voltage of the IGBT to be tested. The apparatus further obtains a junction temperature of the IGBT to be tested from the measured collector-emitter voltage and a temperature coefficient of the IGBT to be tested.

Abstract: A method of assembling a testing apparatus for a full-power converter assembly includes coupling an electric power supply apparatus to an electric power grid. The method also includes coupling a direct current (DC) generation apparatus to the electric power supply apparatus. The method further includes coupling an electric power grid simulation device to the DC generation apparatus. The method also includes coupling a full-power converter assembly test connection to the electric power grid simulation device.

Abstract: A voltage detection device including a multiplexer provided with a plurality of input channels connected to respective battery cells and an output channel connected to an analog-to-digital (AD) converter. The multiplexer is further provided with an additional input channel that is connected to a voltage source that supplies a fault detection voltage. A multiplexer controller is triggered by an input trigger signal to instruct the multiplexer to sequentially connect the input channels and the additional input channel to the output channel according to a predetermined voltage detection sequence. An abnormality detector determines that there exists an abnormality in the multiplexer controller on the basis of an output of the AD converter when the AD converter detects the fault detection voltage at a timing different from a normal timing defined by the voltage detection sequence. This enables the voltage detection device to self-diagnose the multiplexer controller.

Abstract: A stacked semiconductor device includes a first semiconductor device equipped with a first semiconductor chip 14 having a transistor circuit and protection diodes, and a second semiconductor device equipped with a second semiconductor chip 24 having a transistor circuit and protection diodes, and stacked on the first semiconductor device via a connection portion, wherein a power supply line connected to the first and second semiconductor chips is used in common, and a forward ON voltage of the protection diodes of the first semiconductor chip is set higher than a forward ON voltage of the protection diodes of the second semiconductor chip 24. When a connection test is executed, the forward ON voltage of the protection diodes of the first semiconductor chip or the second semiconductor chip is detected and then normal/open is judged.

Abstract: According to one aspect, an integrated magnetic particle measurement device for detecting a presence or absence of magnetic particles in a sample volume includes at least one sensor cell having a differential sensor pair. An active sensor oscillator frequency is responsive to one or more magnetic particles situated within a sample volume. The sensor cell is configured to be operative in the absence of an externally applied magnetic field. A frequency measurement circuit provides as a time-multiplexed output a first count representative of the active sensor oscillator frequency and a second count representative of the reference sensor oscillator frequency. A calculated difference between the first count and the second count is indicative of a presence or an absence of one or more magnetic particles within the sample volume. An integrated magnetic particle measurement system array and a method for detecting one or more magnetic particles are also described.

Abstract: This invention provides a high voltage thyristor valve multi-injection test method, it can meet one way valve and double valve operation test and over current test requirements. It has high equivalence and good flexibility. It includes FACTS double way thyristor valve and normal direct current thyristor valve operation tests and over current test. This method is novel, flexible, can carry out many different test and their mixture test and including the high voltage thyristor valve different tests.

Abstract: A test circuit includes a first test circuit. The first test circuit includes a first light-emitting diode (LED) and a first resistor. An anode of the first LED is connected to a power supply. A cathode of the first LED is connected to a collector of a bipolar junction transistor (BJT) through the first resistor. An emitter of the BJT is grounded. A base of the BJT is connected to the power supply. A type of the BJT can be determined according to status of the first LED.

Abstract: An electrical circuit device includes a semiconductor component which has power terminals and a control terminal electrically insulated from the power terminals, for applying a control voltage, and a control terminal contact surface for contacting the control terminal for measuring the electrical behavior of the semiconductor component. A connection device is provided, via which the control terminal is electrically connectable to a series device, the connection device being transferable from a nonconductive state into a conductive state, in which the control terminal is connected to the series device.

Abstract: Systems and methods for adjusting threshold voltage. A threshold voltage of a transistor of an integrated circuit is measured. A bias voltage, which when applied to a body well of the transistor corrects a difference between the threshold voltage and a desired threshold voltage for the transistor, is determined. The bias voltage is encoded into non-volatile storage on the integrated circuit. The non-volatile storage can be digital and/or analog.

Abstract: A system is used with a plurality of modules, each module requiring galvanic isolation from the other modules. Galvanic isolators are employed, each having an input and an output, the output galvanically isolated from the input, the output responsive to the input according to a response characteristic of the isolator. Each module has, a respective first isolator and a respective second isolator. The input of each respective first isolator and each respective second isolator for each module is disposed controllably to receive an activation signal from the module indicative of a module fault to be annunciated or to receive a test signal from the module, the test signal being smaller than the activation signal. The outputs of the respective first isolators are aggregated to a first node and the outputs of the respective second isolators are aggregated to a second node.

Abstract: A circuit and method are provided for detecting a power of a signal amplified in a power amplifier. A diode and a voltage bias source are used to shift a voltage of the signal taken at a base of an amplifying transistor of the power amplifier, to generate a positive signal. The positive signal is provided to a base input of an emitter follower exhibiting high input impedance to generate a power detector output which follows the positive signal.

Abstract: Systems and methods for adjusting threshold voltage. A threshold voltage of a transistor of an integrated circuit is measured. A bias voltage, which when applied to a body well of the transistor corrects a difference between the threshold voltage and a desired threshold voltage for the transistor, is determined. The bias voltage is encoded into non-volatile storage on the integrated circuit. The non-volatile storage can be digital and/or analog.

Abstract: To prevent an excessive current from flowing through a device under test. A test apparatus that tests a device under test, comprising a power supply section that generates a power supply voltage to be supplied to the device under test; an inductive load section that is provided in a path leading from the power supply section to the device under test; a first semiconductor switch that is provided in the path leading from the inductive load section to the device under test and is connected in parallel with the device under test; and a control section that turns the first semiconductor switch ON when supply of the power supply voltage to the device under test is stopped.

Abstract: A semiconductor wafer having IGBT elements and transistors formed on a surface thereof is prepared. Electron beams are emitted all over the surface of the semiconductor wafer. Recombination centers are formed in the IGBT elements and the transistors. ON voltages of the transistors are measured by a measurement device, and lifetimes defined in the IGBT elements and the transistors are recovered by a prescribed annealing treatment. When the lifetimes are recovered, a control device controls an annealing treatment amount in the annealing treatment based on the measured ON voltages of the transistors such that ON voltages of the IGBT elements are each equal to a desired ON voltage. Variations in the ON voltages of a plurality of IGBT elements obtained from the semiconductor wafer are reduced.

Abstract: A voltage detection device including a multiplexer provided with a plurality of input channels connected to respective battery cells and an output channel connected to an analog-to-digital (AD) converter. The multiplexer is further provided with an additional input channel that is connected to a voltage source that supplies a fault detection voltage. A multiplexer controller is triggered by an input trigger signal to instruct the multiplexer to sequentially connect the input channels and the additional input channel to the output channel according to a predetermined voltage detection sequence. An abnormality detector determines that there exists an abnormality in the multiplexer controller on the basis of an output of the AD converter when the AD converter detects the fault detection voltage at a timing different from a normal timing defined by the voltage detection sequence. This enables the voltage detection device to self-diagnose the multiplexer controller.

Abstract: A method of manufacturing a silicon carbide (SiC) bipolar junction transistor (BJT) and a SiC BJT are provided. The SiC BJT comprises an emitter region, a base region and a collector region. The collector region is arranged on a substrate having an off-axis orientation of about 4 degrees or lower. Further, a defect termination layer (DTL) is arranged between the substrate and the collector region. A thickness and a doping level of the DTL are configured to terminate basal plane dislocations in the DTL and reduce the growth of defects from the DTL to the collector region. At least some of the embodiments are advantageous in that SiC BJTs with improved stability are provided. Further, a method of evaluating the degradation performance of a SiC BJT is provided.