Cmos Patents (Class 326/121)
  • Patent number: 11967954
    Abstract: A class of complex logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. At least one input to an individual multi-input majority gate is a fixed input. Other inputs are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node, which provides a majority function of the inputs. The summing node is coupled to a CMOS logic. Leakage through the capacitors is configured such that capacitors of a majority gate have substantially equal leakage, and this leakage has a I-V behavior which is symmetric. As such, reset device(s) on the summing node are not used. The non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels, which reduces the high leakage problem faced from majority gates that use linear input capacitors.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: April 23, 2024
    Assignee: KEPLER COMPUTING INC.
    Inventors: Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Darshak Doshi, Rajeev Kumar Dokania, Sasikanth Manipatruni
  • Patent number: 11923848
    Abstract: A class of complex logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. At least one input to an individual multi-input majority gate is a fixed input. Other inputs are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node, which provides a majority function of the inputs. The summing node is coupled to a CMOS logic. Leakage through the capacitors is configured such that capacitors of a majority gate have substantially equal leakage, and this leakage has a I-V behavior which is symmetric. As such, reset device(s) on the summing node are not used. The non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels, which reduces the high leakage problem faced from majority gates that use linear input capacitors.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: March 5, 2024
    Assignee: KEPLER COMPUTING INC.
    Inventors: Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Darshak Doshi, Rajeev Kumar Dokania, Sasikanth Manipatruni
  • Patent number: 11901900
    Abstract: An integrated circuit includes an input pad and a Schmitt trigger coupled to the input pad. The Schmitt trigger includes a main PMOS branch that charges an intermediate node of the Schmitt trigger responsive to voltage transitions at the input node. The Schmitt trigger includes a charging assistance circuit that helps to rapidly charge the intermediate node of the Schmitt trigger. The charging assistance circuit includes a parallel PMOS branch in parallel with the main PMOS branch.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: February 13, 2024
    Assignee: STMicroelectronics International N.V.
    Inventors: Kailash Kumar, Manoj Kumar
  • Patent number: 11764765
    Abstract: A receiver circuit may include a first stage and a second stage. The first stage may include a first inverter circuit to generate a first signal based on an input signal and a second inverter circuit to generate a second signal based on the input signal. The second stage may determine a logic state of the input signal by combining the first signal generated by the first inverter circuit and the second signal generated by the second inverter circuit.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: September 19, 2023
    Assignee: Synopsys, Inc.
    Inventors: Rahul Gupta, Nitin Bansal, Akhil Thotli, Manoj Kumar Reddy Puli
  • Patent number: 11688733
    Abstract: An apparatus and configuring scheme where a paraelectric capacitive input circuit can be programmed to perform different logic functions by adjusting the switching threshold of the paraelectric capacitive input circuit. Digital inputs are received by respective capacitors on first terminals of those capacitors. The second terminals of the capacitors are connected to a summing node. A pull-up and pull-down device are coupled to the summing node. The pull-up and pull-down devices are controlled separately. During a reset phase, the pull-up and/or pull-down devices are turned on or off in a sequence, and inputs to the capacitors are set to condition the voltage on node nl. As such, a threshold for the capacitive input circuit is set. After the reset phase, an evaluation phase follows. In the evaluation phase, the output of the capacitive input circuit is determined based on the inputs and the logic function configured during the reset phase.
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: June 27, 2023
    Assignee: Kepler Computing Inc.
    Inventors: Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Sasikanth Manipatruni
  • Patent number: 11658662
    Abstract: Methods, systems, and devices for leakage current reduction in electronic devices are described. Electronic devices may be susceptible to leakage currents when operating in a first mode, such as an inactive (e.g., a standby) mode. To mitigate leakage current, an electronic device may include transistors coupled in cascode configuration where a gate of a drain-side transistor in the cascode configuration is configured to be biased by an adjustable (e.g., a dynamic) control signal. When the transistors are inactive (e.g., “off”), the control signal may be adjusted to prevent leakage associated with the inactive transistors. Further, a source-side transistor in the cascode configuration may be configured to have a high threshold voltage (e.g., relative to the drain-side transistor).
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: May 23, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Hiroshi Akamatsu, Ki-Jun Nam, John David Porter
  • Patent number: 11502691
    Abstract: An adder uses with first and second majority gates. For a 1-bit adder, output from a 3-input majority gate is inverted and input two times to a 5-input majority gate. Other inputs to the 5-input majority gate are the same as those of the 3-input majority gate. The output of the 5-input majority gate is a sum while the output of the 3-input majority gate is the carry. Multiple 1-bit adders are concatenated to form an N-bit adder. The input signals to the majority gates can be analog, digital, or a combination of them, which are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a non-linear polar capacitor. The second terminal of the capacitor provides the output of the logic gate.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: November 15, 2022
    Assignee: Kepler Computing Inc.
    Inventors: Sasikanth Manipatruni, Yuan-Sheng Fang, Robert Menezes, Rajeev Kumar Dokania, Gaurav Thareja, Ramamoorthy Ramesh, Amrita Mathuriya
  • Patent number: 11463077
    Abstract: A comparator includes an input stage having a differential input and an output, wherein the voltage at the output is in response to the voltage at the input. The comparator further includes a current limiter for limiting the current flow through the input stage, wherein the current flow through the input stage is in response to the voltage at the input.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: October 4, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Dinesh Jain
  • Patent number: 11394387
    Abstract: A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. Input signals in the form of digital signals are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node which provides a majority function of the inputs. The majority node is then coupled driver circuitry which can be any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. In the multi-input majority or minority gates, the non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels. Bringing the majority output close to rail-to-rail voltage eliminates the high leakage problem faced from majority gates formed using linear input capacitors.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: July 19, 2022
    Assignee: Kepler Computing Inc.
    Inventors: Sasikanth Manipatruni, Rafael Rios, Neal Reynolds, Ikenna Odinaka, Robert Menezes, Rajeev Kumar Dokania, Ramamoorthy Ramesh, Amrita Mathuriya
  • Patent number: 11303280
    Abstract: A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. In one example, a sequential circuit includes pass-gates and inverters, but without a feedback mechanism or memory element. In another example, a sequential uses load capacitors (e.g., capacitors coupled to a storage node and a reference supply). The load capacitors are implemented using ferroelectric material, paraelectric material, or linear dielectric. In one example, a sequential uses minority, majority, or threshold gates with ferroelectric or paraelectric capacitors. In one example, a sequential circuit uses minority, majority, or threshold gates configured as NAND gates.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: April 12, 2022
    Assignee: Kepler Computing Inc.
    Inventors: Amrita Mathuriya, Ikenna Odinaka, Rajeev Kumar Dokania, Rafael Rios, Sasikanth Manipatruni
  • Patent number: 11303274
    Abstract: Sub-threshold current reduction circuit (SCRC) switches and related apparatuses and methods are disclosed. An apparatus includes a first set of SCRC switches and a second set of SCRC switches electrically connected between power supply lines and power reception lines. The first set of SCRC switches is configured to electrically connect the power supply lines to the power reception lines in the first operational mode and the second operational mode. The second set of SCRC switches is configured to electrically connect the power supply lines to the power reception lines in the first operational mode and electrically isolate the power supply lines from the power reception lines in the second operational mode. Activation of the first set of SCRC switches is staggered in time with activation of the second set of SCRC switches. The second set of SCRC switches is spaced among the first set of SCRC switches.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: April 12, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Go Takashima
  • Patent number: 11176985
    Abstract: Apparatuses and methods related to power domain boundary protection in memory. A number of embodiments can include using a voltage detector to monitor a floating power supply voltage used to power a number of logic components while a memory device operates in a reduced power mode, and responsive to the voltage detector detecting that the floating power supply voltage reaches a threshold value while the memory device is in the reduced power mode, providing a control signal to protection logic to prevent a floating output signal driven from one or more of the logic components from being provided across a power domain boundary to one or more of a different number of logic components.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: November 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Ki-Jun Nam, Hiroshi Akamatsu, Takamasa Suzuki, Yasushi Matsubara
  • Patent number: 11081167
    Abstract: Systems and methods for reducing the energy per bit of memory cell sensing operations, such as memory read operations, by dynamically adjusting the body effect of data latch transistors during the sensing operations are described. A significant component of the energy required to perform the memory cell sensing operations may correspond with the parasitic currents through low threshold voltage (VT) transistors of data latches within sense amplifier circuits. In order to reduce the energy per bit of the memory cell sensing operations while using a reduced supply voltage for the data latches, the body effect of a select number of the low VT transistors within the data latches may be dynamically adjusted such that the body effect is minimized or nonexistent during the latching of new data into the data latches and then increased after the new data has been latched within the data latches.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: August 3, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hiroki Yabe, Koichiro Hayashi
  • Patent number: 11069683
    Abstract: A SEU tolerant structure has two logic sections that generate two output signals that are complementary such that a fault which affects one section cannot affect the other section. Adjacent NMOS regions or adjacent PMOS regions contain no logic inversions in the combinational logic or if logic inversions in the combinational logic are present where all gates following the inversion are SEU hard by design. The circuits can be realized using one of a Complex CMOS gate, pass transistor logic, Multiplexor logic, AND-OR logic or OR-AND logic.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: July 20, 2021
    Assignee: ICs LLC
    Inventors: Sterling Whitaker, Gary Maki
  • Patent number: 11070206
    Abstract: A logic circuit includes an inverter that outputs from an output terminal a signal created by inverting the logic of a signal input into an input terminal, a first transistor that is connected to the input terminal in such a way as to maintain an OFF state, and a second transistor that is connected to the output terminal in such a way as to maintain an OFF state.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: July 20, 2021
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Tetsuo Oomori
  • Patent number: 10943040
    Abstract: Methods, systems and computer program products for improved placement of a clock gating latch are provided. Aspects include identifying a clock gating latch that is designated to control a local clock buffer. Aspects also include determining a plurality of data latches that are designated to be controlled by the local clock buffer. Aspects also include determining positions of the plurality of data latches within a layout. Aspects also include determining a position of the clock gating latch within the layout based on the positions of the plurality of data latches within the layout.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: March 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jesse Surprise, Gerald Strevig, III, Shawn Kollesar, Adam Matheny
  • Patent number: 10932342
    Abstract: Systems and methods for operating light emitting diodes (LEDs) circuits are provided. Aspects include a plurality of light emitting diodes (LEDs) arranged in a plurality of segments, wherein the plurality of segments comprise a first segment and a second segment, and the plurality of segments are connected in series between a rectified alternating current (AC) power source and ground and a control circuit configured to operate the first bypass switch, the second bypass switch, and the third bypass switch; and wherein the control circuit is further configured to determine a rectified voltage of the rectified AC power source and operate the third switch to turn off when the rectified voltage drops below a first threshold.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: February 23, 2021
    Assignee: GOODRICH CORPORATION
    Inventor: Rajkumar Sengodan
  • Patent number: 10924093
    Abstract: A circuit includes a plurality of voltage supply terminals including a lowest voltage supply terminal, an N-type finFET, and a current path electrically coupled to the lowest voltage supply terminal, where the N-type finFET transistor is located in the current path. The N-type finFET transistor includes at least one semiconductor fin, a gate structure made of a gate material located over the at least one fin, an end structure of the gate material located over an end of the at least one fin, a source electrode, and a drain electrode. The at least one fin is located over a well region, and the end structure is electrically tied to the well region, in which the well region is not electrically tied to the lowest voltage supply terminal.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: February 16, 2021
    Assignee: NXP USA, Inc.
    Inventor: Hector Sanchez
  • Patent number: 10892757
    Abstract: A metal oxide semiconductor (MOS) transistor has a source terminal, a drain terminal, a gate terminal and a body terminal. The source terminal is connected to receive a supply voltage and the body terminal is connected to receive a reverse body bias voltage. A photovoltaic circuit has a first terminal connected to the source terminal of the MOS transistor and a second terminal connected to the body terminal of the MOS transistor. The photovoltaic circuit converts received photons from the environment to generate the reverse body bias voltage.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: January 12, 2021
    Assignee: STMicroelectronics (Research & Development) Limited
    Inventor: Filip Kaklin
  • Patent number: 10837999
    Abstract: Facilitating fault detection of a system using a test input including a linear combination of inputs of the system is presented herein. A test signal component generates, via a test procedure, a test input signal including a first linear combination of at least two input signals of the system, and applies the test input signal to the system during a phase of respective phases of the test procedure; and a fault detection component detects a fault of the system based on a test output signal corresponding to the test input signal and a second linear combination of respective output signals of the system corresponding to the at least two input signals.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: November 17, 2020
    Assignee: INVENSENSE, INC.
    Inventors: Omid Oliaei, Adolfo Giambastiani
  • Patent number: 10804903
    Abstract: A circuit stacking multiple asynchronous circuit components, specifically Multi-Threshold NULL Convention Logic (MTNCL) circuit components, with an overall power supply equal to the multiples of the original VDD.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: October 13, 2020
    Inventors: Jia Di, Andrew Lloyd Suchanek, Zhong Chen, Matthew Leftwich
  • Patent number: 10790808
    Abstract: A passable latch circuit and variable delay chains built with one or more passable latch circuits are disclosed. The passable latch circuit has a dynamic latch including a first P-transistor, a first N-transistor, a second P-transistor, a second N-transistor and a clock input circuitry. The passable latch circuit further includes a control switch connected between the gates of the second P-transistor and the second N-transistor. The control switch has an on state and an off state, and the passable latch circuit is configured to have different delays by controlling the state of the control switch.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: September 29, 2020
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventor: Fenghao Mu
  • Patent number: 10783304
    Abstract: The present disclosure relates to a method for electronic design. Embodiments may include displaying, at a graphical user interface, at least a portion of a cover trace or an assertion counter-example associated with an electronic design. Embodiments may also include allowing, at the graphical user interface, a user to analyze the cover trace or the assertion counter-example during a debugging session. Embodiments may further include identifying a dead-end state during the analysis and converting one or more constraints used in the debugging session to soft constraints. Embodiments may further include identifying at least one trace, based upon, at least in part, the soft constraints and displaying at least one unsatisfied constraint associated with the identified trace at the graphical user interface.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: September 22, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Thiago Radicchi Roque, Stefan Staber, Chung-Wah Norris Ip
  • Patent number: 10776545
    Abstract: A method includes identifying a timing path in a transistor level from a graph diagram; calculating a plurality of aging costs associated with the timing path based on a plurality of forms of a DC vector; identifying a first form, associated with a first aging cost of the aging costs, from the forms; and identifying a second form, associated with a second aging cost less than the first aging cost, from the forms.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ravi Babu Pittu, Li-Chung Hsu, Sung-Yen Yeh, Chung-Hsing Wang
  • Patent number: 10615780
    Abstract: In certain aspects, a clock generation circuit couples to a first clock having a first duty cycle and a second clock having the first duty cycle. The second clock lags the first clock by 90 degrees in phase. The clock generation circuit is configured to couple the output terminal to a ground when the first clock and the second clock both are at logic high and decouple the output terminal from the ground when at least one of the first clock and the second clock is at logic low and couple a supply voltage to the output terminal only when the first clock is at logic low and decouple the supply voltage from the output terminal when the first clock is at logic high. The clock generation circuit generates clock signals having a second duty cycle.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: April 7, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Animesh Paul, Xinhua Chen
  • Patent number: 10574228
    Abstract: The signal multiplexer 1 inputs two selection signals CLK<1>, CLK<2> that sequentially reach significant levels, inputs two input signals IN<1>, IN<2>, and outputs, from an output terminal 14, a signal OUT that depends on an m-th input signal IN<m> of the two input signals when an m-th selection signal CLK<m> of the two selection signals is at the significant level. The signal multiplexer 1 includes a resistance unit 20 and two drive units 301, 302. Each of the drive units 30m includes a driving switch 31m, a selecting switch 32m, and a potential stabilizing switch 33m. When one of the selecting switch 32m and the potential stabilizing switch 33m in each of the drive units 30m is in a closed state, the other is in an open state.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: February 25, 2020
    Assignee: THINE ELECTRONICS, INC.
    Inventors: Yusuke Fujita, Satoshi Miura, Shunichi Kubo
  • Patent number: 10548190
    Abstract: The present concepts relate to a negative rail generator that temporarily self-generates a negative voltage rail to increase the voltage difference across a light emitting diode (LED) to be greater than the positive source voltage that is available. As such, the voltage difference provides sufficient headroom to exceed the minimum forward voltage required to conduct the LED with constant current. In one example, the negative rail generator may include a capacitor, a diode clamp, and a transistor. The negative rail generator and the LED may be operated in synchronization by a common PWM signal. The negative voltage rail can be generated without adding a switched-mode power supply (SMPS) or a charge pump.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: January 28, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Stefan J. Kristjansson
  • Patent number: 10454479
    Abstract: An inverter includes a first system voltage terminal, a second system voltage terminal, an output terminal, a plurality of P-type transistors, a plurality of N-type transistors, and a voltage drop impedance element. The first system voltage terminal receives a first voltage, and the second system voltage terminal receives a second voltage. The plurality of P-type transistors are coupled in series between the first system voltage terminal and the output terminal. The plurality of N-type transistors are coupled in series between the output terminal and the second system voltage terminal. The voltage drop impedance element is coupled in parallel with a first N-type transistor of the plurality of N-type transistors, and the impedance of the voltage drop impedance element is smaller than the impedance of the first N-type transistor when the first N-type transistor is turned off.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: October 22, 2019
    Assignee: RichWave Technology Corp.
    Inventors: Chih-Sheng Chen, Tien-Yun Peng
  • Patent number: 10447270
    Abstract: A combinational logic circuit includes input circuitry to receive a first input signal that transitions between upper and lower voltages of a first voltage domain, and to generate, in response to the transitions of the first input signal, a first localized signal that transitions between upper and lower voltages of a second voltage domain. The combinational logic circuit additionally includes output circuitry to generate a first output signal that transitions between the upper and lower supply voltages of the first voltage domain based at least in part on the transitions of the first localized signal.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: October 15, 2019
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, John Eric Linstadt
  • Patent number: 10424379
    Abstract: A polarization-based logic gate includes a transistor having a drain and a polarizable material layer having at least two polarization states, the polarization state representing a first logic value, and a resistive element having a first terminal coupled to the drain and a second terminal. A plurality of input/output terminals connected to the transistor and second terminal of the resistive element so as to apply voltages to selected input/output terminals, including a sensing voltage representing a second logic value, with a resulting drain current of the transistor at least partially flowing through the resistive element and representing a result of a logic operation between the first logic value and the second logic value.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: September 24, 2019
    Assignee: NaMLab gGmbH
    Inventors: Stefan Slesazeck, Halid Mulaosmanovic, Evelyn Breyer
  • Patent number: 10347631
    Abstract: A complementary thin film transistor includes an N-type metal oxide thin film transistor and a P-type metal oxide thin film transistor. A method of manufacturing a complementary thin film transistor is also provided. The method includes forming a complementary thin film transistor including an N-type metal oxide thin film transistor and a P-type metal oxide thin film transistor. An array substrate including the complementary thin film transistor and a display device including the array substrate are further provided.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: July 9, 2019
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Wei Qin
  • Patent number: 10283963
    Abstract: In general, the subject matter described in this disclosure can be embodied in a system that implements power supply protection. The system includes first circuitry, second circuitry, a first power supply that is configured to power the first circuitry, and a second power supply that is configured to power the first circuitry and the second circuitry. The system also includes a power supply sensor including an input that is connected to the first power supply, and an output. The system also includes a hysteresis buffer including an input that is connected to the output of the power supply sensor, and an output that is connected to the first circuitry in a configuration that transitions the first circuitry to a protected state as a result of the hysteresis buffer transitioning output states.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: May 7, 2019
    Assignee: Teledyne LeCroy, Inc.
    Inventors: Juan P. Mena, Philippe Convers
  • Patent number: 10262985
    Abstract: A block of logic gates has MOS transistors whose body terminals are connected with a body voltage rail and whose source terminals are connected with a logic reference voltage rail. The logic reference voltage rail is connected to the body voltage rail via a resistor. The resistor creates a negative feedback loop for leakage currents that stabilizes a reverse body bias voltage and reduces the influence of temperature, voltage, and process variations. The block may be NMOS, PMOS, or CMOS. In the case of CMOS, there are two body voltage rails, powered by a voltage source, two logic reference voltage rails, and two resistors. The reverse body bias voltages over the two resistors may be stabilized by decoupling capacitors. The two resistors may be trimmable. The resistors may be calibrated such that leakage currents are at a minimum value and the logic gates can switch just fast enough.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: April 16, 2019
    Assignee: Perceptia IP Pty Ltd
    Inventors: Timothy Robins, Julian Jenkins
  • Patent number: 10256802
    Abstract: In an example, an input buffer includes: first buffer circuit having an output, a first voltage control node, and a second voltage control node; a first transistor having a gate coupled to the output of the first buffer circuit, a drain, and a source; a second buffer circuit having an input coupled to a reference voltage and an output coupled to the source of the first transistor; and a first current source having a reference output coupled to the drain of the first transistor, a first output coupled to the first voltage control node of the first buffer circuit, and a second output coupled to the second voltage control node of the second buffer circuit.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: April 9, 2019
    Assignee: XILINX, INC.
    Inventor: Bruno Miguel Vaz
  • Patent number: 10249756
    Abstract: A semiconductor device includes a memory circuit and a logic circuit. The memory circuit includes a word line, a bit line, a common line and a memory transistor having a gate coupled to the word line, a drain coupled to the bit line and a source coupled to the common line. The logic circuit includes a field effect transistor (FET) having a gate, a drain and a source. The memory transistor has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a first insulating layer and a first ferroelectric (FE) material layer. The FET has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a second insulating layer and a second FE material layer.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: April 2, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Chi Tu, Jen-Sheng Yang, Sheng-Hung Shih, Tong-Chern Ong, Wen-Ting Chu
  • Patent number: 10224929
    Abstract: A power semiconductor drive circuit includes a parallel circuit connected to a gate of a power semiconductor element and constituted by two transistors for setting gate resistance of the power semiconductor element; a gate voltage monitoring circuit connected to the gate of the power semiconductor element and the parallel circuit, wherein a monitoring voltage is set in the gate voltage monitoring circuit to monitor a gate voltage of the power semiconductor element; a signal delay circuit to delay an output signal of the gate voltage monitoring circuit; and a gate control circuit to change the magnitude of combined resistance of the parallel circuit based on an output signal output from the signal delay circuit.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: March 5, 2019
    Assignee: Rohm Co., Ltd.
    Inventors: Yuji Ishimatsu, Motohiro Ando
  • Patent number: 10200025
    Abstract: Some embodiments include apparatus and methods using a first latch to receive an input signal at a gate of a transistor of the first latch and compare the input signal with a reference signal to provide a first output signal at an output node of the first latch, and a second latch coupled to the output node of the first latch, the second latch including a complementary metal-oxide semiconductor (CMOS) inverter to generate a second output signal at an output node of the second latch based on the first output signal. The second output signal has a signal swing greater than a signal swing of the first output signal.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: February 5, 2019
    Assignee: Intel Corporation
    Inventors: Hemesh Yasotharan, Raymond K Tang, James Guthrie
  • Patent number: 10193544
    Abstract: Embodiments include a power conversion circuit comprising first and second semiconductor switches, and a drive circuit configured to create a period of operational overlap for the first and second switches by setting a gate voltage of the first switch to an intermediate value above a threshold voltage of the first switch, during turn-on and turn-off operations of the second switch. Embodiments also include a method of operating first and second semiconductor devices, comprising: reducing a gate voltage of the first device to an intermediate value above a threshold voltage while the second device is off; turning off the first device after the second device is on; increasing the gate voltage of the first device to the intermediate value while the second device is on; and fully turning on the first device after the second device is off.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: January 29, 2019
    Assignee: Ford Global Technologies, LLC
    Inventors: Krishna Prasad Bhat, Chingchi Chen
  • Patent number: 10164094
    Abstract: A semiconductor device includes a memory circuit and a logic circuit. The memory circuit includes a word line, a bit line, a common line and a memory transistor having a gate coupled to the word line, a drain coupled to the bit line and a source coupled to the common line. The logic circuit includes a field effect transistor (FET) having a gate, a drain and a source. The memory transistor has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a first insulating layer and a first ferroelectric (FE) material layer. The FET has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a second insulating layer and a second FE material layer.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Chi Tu, Jen-Sheng Yang, Sheng-Hung Shih, Tong-Chern Ong, Wen-Ting Chu
  • Patent number: 10164768
    Abstract: In certain aspects, a circuit includes a dynamic differential logic gate having first and second outputs, and a first static differential logic gate having first and second outputs, and first and second inputs coupled to the first and second outputs, respectively, of the dynamic differential logic gate. The dynamic differential logic gate is configured to receive a clock signal and to preset both the first and second outputs of the dynamic differential logic gate to a first preset value during a first phase of the clock signal. The first static differential logic gate is configured to preset both the first and second outputs of the first static differential logic gate to a second preset value when the first preset value is input to both the first and second inputs of the first static differential logic gate.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: December 25, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Ravindraraj Ramaraju, Rakesh Vattikonda, Samrat Sinharoy, De Lu, Bo Pang
  • Patent number: 10153368
    Abstract: A system of unipolar digital logic. Ferroelectric field effect transistors having channels of a first polarity, are combined, in circuits, with simple field effect transistors having channels of the same polarity, to form logic gates and/or memory cells.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: December 11, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ryan M. Hatcher, Rwik Sengupta, Chris Bowen
  • Patent number: 10033388
    Abstract: An integrated circuit enables the selection of a circuit. According to one implementation, a plurality of redundant circuits provide a predetermined function and a voltage sensor may be coupled to receive a reference voltage. A selection circuit may be coupled to the voltage sensor and the reference voltage, wherein the selection circuit selects one of the plurality of redundant circuits to be implemented in the integrated circuit based upon a detected voltage of the reference voltage of the reference voltage.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: July 24, 2018
    Assignee: XILINX, INC.
    Inventors: Mini Rawat, Pierre Maillard, Michael J. Hart
  • Patent number: 10020809
    Abstract: The present disclosure relates to integrated level translator and latch circuits and, more particularly, to an integrated level translator and latch circuits for fence architectures in SRAM cells. The integrated level translator and latch for input signals includes a first clock (CLKS) and a second clock (CLKH). The first clock (CLKS) is used as a precharge and evaluation clock with its timing being critical for forward edge and the second clock (CLKH) is a latch clock.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: July 10, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Venkatraghavan Bringivijayaraghavan
  • Patent number: 10014048
    Abstract: A dual interlocked storage cell (DICE) latch may be provided. A semiconductor device may be provided. The semiconductor device may include a DICE latch.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: July 3, 2018
    Assignee: SK hynix Inc.
    Inventor: Dong Uc Ko
  • Patent number: 10014219
    Abstract: A semiconductor device includes a structure on a substrate and a plurality of gate-all-around devices on the structure. The structure includes a plurality of sacrificial layers and a plurality of active layers alternately stacked on one another. The sacrificial layers have different widths and the active layers have different widths to form multiple stepped layers on the substrate. The gate-all-around devices are on respective ones the multiple stepped layers.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: July 3, 2018
    Assignees: Samsung Electronics Co., Ltd., Seoul National University R & DB Foundation
    Inventors: Min-Chul Sun, Byung-Gook Park
  • Patent number: 10003339
    Abstract: A GPIO interface circuit compatible with output of MIPI signals, comprises a first CMOS signal output module (10), an LVDS signal output module (30), a second CMOS signal output module (20). When an MIPI output enable input of the LVDS signal output module (30) is enabled and output enable inputs of the first and second CMOS signal output modules (10, 20) are both disabled, a first and second pull-down modules (40, 50) are in active state accordingly, and the LVDS signal output module (30) outputs a current signal to the first or second pull-down module (40, 50) to ensure voltage of the first or second signal output be a preset voltage, which can achieve MIPI HS Mode output.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: June 19, 2018
    Assignee: GUANGDONG GOWIN SEMICONDUCTOR CORPORATION, LTD.
    Inventors: Jinghui Zhu, Bin Gao, Chienkuang Chen
  • Patent number: 9997227
    Abstract: Described is an apparatus which comprises: a first power domain having a first inverter to be powered by a first switchable positive supply and a first switchable negative supply; and a second power domain having a second inverter including p-type and n-type FE-FETs, the second inverter having an input coupled to an output of the first inverter.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: June 12, 2018
    Assignee: Intel Corporation
    Inventors: Daniel H. Morris, Uygar E. Avci, Ian A. Young
  • Patent number: 9997208
    Abstract: A circuit including an output node and a cross-coupled pair of semiconductor devices configured to provide, at the output node, an output signal in a second voltage domain based on an input signal in a first voltage domain is described herein. The circuit further includes a pull-up assist circuit coupled to the output node; and a look-ahead circuit coupled to the pull-up assist circuit, wherein the look-ahead circuit is configured to cause the pull-up assist circuit to assist in increasing a voltage level at the output node when there is a decrease in a voltage level of an inverted output signal in the second voltage domain from a high voltage level of the second voltage domain to a low voltage level of the second voltage domain.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: June 12, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Chulmin Jung, Po-Hung Chen, Fahad Ahmed, Changho Jung, Sei Seung Yoon, David Li
  • Patent number: 9979398
    Abstract: A buffer circuit includes a buffer group including an odd number of cascade buffers, where the buffers may be different from each other; a PMOS transistor and an NMOS transistor; where a source of the PMOS transistor is coupled to a power source, a drain thereof is connected to an output terminal of the buffer group, and a gate thereof is connected to an input terminal of the buffer group; a source of the NMOS transistor is coupled to ground, a drain thereof is connected to the output terminal of the buffer group, and a gate thereof is connected to the input terminal of the buffer group.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: May 22, 2018
    Assignee: CAPITAL MICROELECTRONICS CO., LTD.
    Inventor: Rifeng Mai
  • Patent number: 9960768
    Abstract: An integrated circuit (IC) includes at least one unit cell. The at least one unit cell includes a first bit circuit configured to process a first bit signal, a second bit circuit configured to process a second bit signal, a first well spaced apart from boundaries of the at least one unit cell and biased to a first voltage, and a second well biased to a second voltage that is different from the first voltage. Each of the first and second bit circuits includes at least one transistor from among a plurality of transistors disposed in the first well.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: May 1, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dal-Hee Lee, Jae-Woo Seo, Min-Ho Park