Abstract: A logic gate includes a first driver to receive an input signal, and to control a connection between a first power source and a first node in correspondence with the input signal, a second driver coupled to the first node and a second power source, and to control a voltage of the first node, a third driver to control a connection between an output terminal and the first power source in correspondence with the voltage of the first node, a control transistor to control a connection between the third driver and the second power source, a fourth driver to control a connection between a gate electrode of the control transistor and the second power source, and a second capacitor between a first electrode of the control transistor and the gate electrode of the control transistor, wherein the transistors are a same type of MOS transistor.

Abstract: An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric (GD1) in comparison with other transistors (T2) on the same integrated circuit arrangement (10). As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions (D1, S1) of the tunnel field effect transistor.

Abstract: A method and a structure provide a space efficient integrated circuit using standard cells and power gating by switch cells. The standard cells may be tapless, i.e., not provided a substrate connection to a power supply or ground rail by a tap within the cell. The substrate connection for these standard cells may be provided by the switch cells or by specialized tap cells. The tapless standard cells may include only a context-sensitive rail, which may be configured to be a virtual ground rail by a power gating connection to a switch cell or by a direct connection to a power supply or ground rail.

Abstract: Provided is a voltage detection circuit that outputs a detection result when a voltage to be measured exceeds a predetermined voltage or falls below the predetermined voltage at a speed higher than that of a conventional case. The voltage detection circuit according to the present invention includes an input buffer that outputs a detection voltage to be input as an input voltage, and a voltage detection section that accelerates a rising of the input voltage in a transient state where the input voltage exceeds a predetermined threshold value, and accelerates a dropping of the input voltage in a transient state where the input voltage falls below the predetermined threshold value. The voltage detection circuit accelerates a change in the input voltage to output the detection result from an output buffer at high speed.

Abstract: A power efficient multiplexer. In accordance with a first embodiment of the present invention, a power efficient multiplexer comprises a transmission gate structure for selectively passing one of a plurality of input signals and a stacked inverter circuit for inverting the one of a plurality of input signals. Both the stacked inverter and the transmission gate provide beneficial reductions in static power consumption in comparison to conventional multiplexer designs.

Abstract: A semiconductor integrated circuit comprises logic cones having a structure in which substrates thereof are isolated from each other and substrate potentials can be controlled, and a potential switching section for supplying a substrate voltage from any of a first substrate bias supply potential and a second substrate bias supply potential to the logic cone. A signal output by a logic cone previous to a logic cone whose substrate potential is controlled is input as a trigger signal to the substrate supply potential switching section.

Abstract: The present invention is directed to a circuit and a method that features selectively isolating a logic device from a source of power implementing a counter circuit to transmit a signal to a voltage control device to isolate a source of power from a logic device, coupled to a plurality of switching elements, with the voltage control device being coupled to allocate power to the logic device in response to activation of one of said plurality of switching elements. The logic device is typically a programmable logic device. In one embodiment, the voltage control device is a field effect transistor. In another embodiment the voltage control device is a voltage regulator.

Abstract: A power gated semiconductor integrated circuit comprises: (1) logic circuit to be power gated, said logic circuit having a virtual ground rail; (2) footer device disposed between said virtual ground rail and a ground rail for reducing power consumption of said logic circuit; and (3) virtual rail voltage clamp disposed electrically in parallel with said footer device for limiting the voltage at the virtual ground rail, the virtual rail voltage clamp comprising at least one NFET. A total of Nf NFETs are connected to the virtual ground rail of the integrated circuit for use as both virtual rail voltage clamps and footer devices. A quantity of Nmax-VC NFETs are scanned and perform the function of voltage clamps and the remaining (Nf?Nmax-VC) NFETs perform power gating. Manufacturing variability immunity and tuning of the variability immunity is achieved by adjusting the quantity Nmax-VC based upon testing of the manufactured integrated circuit.

Abstract: It is described a circuit and a method for transforming an input signal into a logical output. The circuit (100) comprises an inverter stage (120), connected in between the first conductor (101) and the second conductor (102). The inverter stage (120) includes a MOS switch (MP0), which comprises a first terminal being connected to the first conductor (101), a second terminal being connected to an output node (hyst), a gate terminal being connected to an input node (JN), and a back gate terminal. The circuit (100) further comprises a voltage divider (130), connected in between the first conductor (101) and the output node (hyst), wherein the voltage divider (130) provides a divider output node (bg) being connected to the back gate terminal. The circuit (100) represents an input cell having an improved hysteresis behavior over the total operating voltage range. This is achieved by adjusting the back gate voltage of the MOS switch (MP0) during a transition from an input level Low to an input level High.

Abstract: A low voltage Complementary Metal Oxide Semiconductor (CMOS) driver circuit for inductive loads is described. The circuit includes at least two first transistor devices, each first transistor device having a drain coupled to an inductive load, a respective second transistor device corresponding to each first transistor device having a drain coupled to a gate of the corresponding first transistor device, and a respective third transistor device corresponding to each first transistor device having a drain coupled to a source of the corresponding first transistor device. If a second transistor device corresponding to a first transistor device of the two first transistor devices is turned off, then a third transistor device corresponding to the remaining first transistor device is turned off, a gate of the first transistor device is floating and a drain-to-gate voltage at the first transistor device is reduced to below a predetermined supply voltage applied at a source of the respective second transistor device.

Abstract: Embodiments of the invention provide an interface circuit that is capable of reducing the power consumption, which may be increased by a shoot-through current, and provide an electronic device having such an interface circuit. In one embodiment, an interface circuit exchanges signals with another electronic device via a signal transmission line. The interface circuit includes a switch for pulling up the signal transmission line and a switch for pulling down the signal transmission line. While a pull-up or pull-down is performed, the interface circuit detects the potential level of the signal transmission line to determine whether the signal transmission line is pulled down or pulled up by the other electronic device. If the signal transmission line is not pulled down/pulled up by the other electronic device, the interface circuit exercises pull-down/pull-up control.

Abstract: A power gated semiconductor integrated circuit comprises: (1) logic circuit to be power gated, said logic circuit having a virtual ground rail; (2) footer device disposed between said virtual ground rail and a ground rail for reducing power consumption of said logic circuit; and (3) virtual rail voltage clamp disposed electrically in parallel with said footer device for limiting the voltage at the virtual ground rail, the virtual rail voltage clamp comprising at least one NFET. A total of Nf NFETs are connected to the virtual ground rail of the integrated circuit for use as both virtual rail voltage clamps and footer devices. A quantity of Nmax-VC NFETs are scanned and perform the function of voltage clamps and the remaining (Nf-Nmax-VC) NFETs perform power gating. Manufacturing variability immunity and tuning of the variability immunity is achieved by adjusting the quantity Nmax-VC based upon testing of the manufactured integrated circuit.

Abstract: A method and system for automatically detecting and optimally compensating a wide range of die leakage currents in dynamic circuits is presented. A self-adaptive keeper tracks the leakage and reduces the leakage effects by optimally controlled compensation current. The self-adaptive keeper utilizes a 2-stage embedded current mirror circuit, a dummy cell and a keeper transistor to compensate leakage current. The load impact of the self-adaptive keeper on the dynamic circuit components (for example, the impact on memory cells) is minimized by a dummy cell which detects and matches the instant leakage current. Amplification in the 2-stage embedded current mirror circuit provides an optimal current strength in the keeper transistor. The optimally amplified leakage current is utilized to compensate for a leakage induced voltage drop at the circuit's output. Thus, the self-adaptive keeper ensures the robustness of the circuit in real time and does not create any negative trade-off on read latency.

Abstract: An integrated circuit is provided having at least one terminal for coupling and/or decoupling of electric signals, particularly of digital signals, and having integrated reference potential means, assigned to the terminal, for providing an electric reference potential to the terminal. It is provided according to an embodiment of the invention that the reference potential means is switchable, particularly by an override process.

Abstract: A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series.

Abstract: A complementary pass-transistor logic includes input nodes provided with first complementary signals; intermediate nodes for outputting complementary intermediate signals; a logic network comprised of NMOS transistors, the network being connected between the input nodes and the intermediate nodes, and the conduction states of the transistors being controlled by second complementary input signals to output a logical operation result of the first and second input signals to the intermediate nodes; and inverters for inverting the intermediate signals and producing complementary output signals, wherein the NMOS transistors of the logic network are configured as a depletion-type NMOS.

Abstract: Techniques for employing multi-gate field effect transistors (FETS) in logic circuits formed from logic gates are provided. Double-gate transistors that conduct only when both transistor gates are active can be used to reduce the number of devices hitherto required in series or “stacked” portions of logic gates. Circuit area can be reduced and performance can be enhanced.

Abstract: A complementary output driver includes a driver input that receives an input signal which alternates between a first state and a second state. A first inverter has a first input and a first output. The first input is coupled to the driver input and the first output generates a complementary output signal that is the complement of a present state of the input signal. A second inverter has a second input and a second output. The second input is coupled to the first output of the first inverter and the second output generates an output signal that is the complement of the present state of the first output. A push-pull network has a push-pull input and a push-pull output. The push-pull input is coupled to the driver input and the push-pull output is coupled to the second output.

Abstract: An SOI structure semiconductor integrated circuit is disclosed that reduces the number of power supply wires setting substrate potential of a semiconductor element and reduces power consumption. With an SOI structure semiconductor integrated circuit, a first circuit block 51 does not include a critical path and a second circuit block 61 does include a critical path. First power supply wiring 28 supplies a first power supply and second power supply wiring 29 supplies a second power supply of a high-voltage compared to the first power supply. A wiring section 71 (P-channel first substrate power supply wiring and P-channel first power supply wiring) supplies the first power supply as a substrate power supply for P-channel elements of the first circuit block 51 and a source power supply.

Abstract: A switching model to create stable binary sequential devices comprised of one or more logic functions with feedback of which an output signal is uniquely related to an input signal is applied to possible binary logic functions. Static latches of commutative and non-commutative binary functions are designed by using the switching model. Latches can be realized by individually controlled gates sometimes with inverters. Optical and electro-optical latches are disclosed. The application of transmission gates to realize latches is also disclosed.

Abstract: A logic circuit consists of a first transistor network and a complementary second transistor network connected at a central node. The central node serves as a first logic output. Each of the transistor networks is also connected to a respective root. A third transistor network is connected between an intermediate node of one of the transistor networks and the network's respective root. For a homogeneous graft, the third transistor network has a complementary structure to the transistors between the intermediate node and the central node, is of the same transistor type as the given transistor network, and has inverted inputs relative to the transistors between the intermediate node and the central node. The third transistor network (the graft network) provides a second logic output to the logic circuit.

Abstract: The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors.

Abstract: A logic gate includes a first driver connected to a first power source, a first control transistor connected between a first node and a second power source to control a voltage of the first node, a second driver connected between a gate electrode of the first control transistor and the second power source, a third driver connected between the first power source and the second power source, a second control transistor connected between the third driver and the second power source, and having a first electrode connected to an output terminal, and a fourth driver arranged between a gate electrode of the second control transistor and the second power source, wherein the first control transistor, the second control transistor and each transistor of the first driver, the second driver, the third driver and the fourth driver are PMOS transistors.

Abstract: A stacked inverter delay chain. The stacked inverter delay chain includes a plurality of stacked inverter delay elements. A switch circuit is included and is coupled to the stacked inverter delay elements and configured to select at least one of the plurality of stacked inverter delay elements to create a delay signal path. The delay signal path has an amount of delay in accordance with a number of stacked inverter delay elements comprising the delay signal path. An input is coupled to a first stacked inverter delay element of the delay signal path to receive an input signal and an output is coupled to the switch circuit and is coupled to the delay signal path to receive a delayed version of the input signal after propagating through the delay signal path.

Abstract: A keeper device for dynamic logic includes a first keeper path statically coupled to a dynamic data path, the first keeper path configured to prevent false discharge of the dynamic data path during an evaluation thereof, and a second keeper path selectively coupled to the dynamic data path. The second keeper path is configured to maintain the dynamic data path at a nominal precharge level prior to an evaluation thereof, wherein the second keeper path is decoupled from the dynamic data path during the evaluation.

Abstract: Embodiments related to fast flip-flops are disclosed.

Abstract: A dynamic logic gate has an asymmetrical dual-gate PFET device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node during an evaluate phase of the clock. The front gate of the asymmetrical dual-gate PFET device is coupled to the clock signal and the back gate is coupled to the ground potential of the power supply. When the clock is a logic zero both the front gate and the back gate are biased ON and the dynamic node charges with maximum current. The clock signal transitions to a logic one during the evaluation phase of the clock turning OFF the front gate. The back gate remains ON and the asymmetrical dual-gate PFET device operates as a keeper device with a current level sufficient to counter leakage on the dynamic node.

Abstract: A semiconductor integrated circuit includes a CMOS controlled inverter consisting of series-connected PMOS and NMOS transistors. The source of the NMOS transistor is coupled to a ground line through an additional NMOS transistor for power gating of voltage VSS. The source of the PMOS transistor can be coupled to a power supply line through an additional PMOS transistor for power gating of voltage VDD. The inverter receives an input signal IN and its complementary version that has transitioned earlier than the input signal. In response to the input signal, the inverter produces an output signal. A NAND gate that receives the output signal and the complementary input signal controls the power gating NMOS transistor. A NOR gate that receives the output signal and the complementary input signal controls the power gating PMOS transistor.

Abstract: A synchronous output buffer circuit which effectively moves combinational logic associated with an output enable operation, boundary scan operation, and voltage translation to a pipe that leads into a pair of output registers that operate in response to the output clock signal. The output registers may be forced to asynchronously route an input signal to an output terminal during a reset mode and during a boundary scan mode. The output registers can include a safety circuit, which prevents pull-up and pull-down devices (which drive the output signal), from turning on at the same time.

Abstract: A circuit element comprising N paired complementary transistors. The transistors are connected to an upper (VDD) and lower voltage level (VSS), in such a way that the paired transistors operate in subthreshold. N input terminals (X1, X2 . . . XN) are connected to the respective paired transistors. Control terminals (BP, BN) are connected to control input nodes of the transistors. The circuit element provides the possibility of real time configuration between various logic functions with a minimum of transistors and wiring.

Abstract: A dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock controlled provides increased noise immunity in dynamic digital circuits. By clocking the pre-charge element with a signal having a reduced swing in the voltage direction that turns off the pre-charge element, the pre-charge element provides a small current that prevents the dynamic summing node of a gate from erroneously evaluating due to noise, and eliminates the need for a keeper device. Providing the reduced-swing asymmetric clock as a separate signal prevents performance degradation in the rest of the circuit. Specifically, the foot devices in the dynamic portion of the circuit are controlled with the full swing clock so that evaluation is not compromised by noise or slowed. Foot and pull-up devices in any static portion of the circuit are also controlled with the full-swing clock so that switching speed and leakage immunity are not affected.

Abstract: An integrated circuit having two or more power domains that include load circuits in different portions of the integrated circuit is disclosed. In order to conserve power, the circuits in one of the power domains are shut down by disconnecting the power source serving that domain. The load circuits in each power domain are buffered from the load circuits in other power domains by buffer cells. The buffer cells reduce leakage currents in the power domain that is shut down, by restricting data signals from the “live” power domain from reaching the shut-down power domain, and further by providing predetermined voltage signals to the load circuits in the shut-down power domain that are selected to minimize leakage currents in the inactive load circuits. The invention further provides a corresponding method for reducing power consumption in an integrated circuit having at least two power domains separated by a buffer cell.

Abstract: In one embodiment, NMOS transistors have their source coupled to a common source node such that the NMOS transistors conduct a leakage current if the common source node is grounded. To reduce this leakage current, the common source node is raised in potential. Similarly, PMOS transistors have their source coupled to a common source node such that the PMOS transistors conduct a leakage current if the common source node is charged to a power supply voltage VDD. To reduce this leakage current, the common source node is lowered in potential.

Abstract: A voltage level control device operable to control a voltage level supplied from a first voltage level source to circuitry, said circuitry being arranged between said first voltage level source and a second voltage level source, said first and second voltage level sources being operable to output different voltage levels; said voltage level control device comprising: a power transistor operable to be connected between said first voltage level source and said circuitry, said power transistor comprising a sleep signal input operable to receive a sleep signal; a switching device arranged in parallel with said power transistor and comprising a sleep signal input operable to receive a pseudo sleep signal; wherein said voltage level control device is operable in dependence upon said sleep signal and said pseudo sleep signal to output to said circuitry an output voltage said output voltage comprising one of three voltage levels, said three voltage levels lying between voltage levels output by said first and second v

Abstract: A selector circuit precisely outputs a signal selected from a plurality of signals. A latch circuit unit generates an internal selection control signal for controlling a selection operation of a selector circuit unit. When the levels of first and second data input signals do not match each other, the selector circuit unit maintains its selected state and does not perform a selecting operation based on the selection signal until the levels of the signals match each other in accordance with the internal selection control signal.

Abstract: A family of logic circuits, called gated diode logic circuits, is disclosed wherein small amplitude signals, typically a fraction of the supply voltage, can be sensed and amplified by applying a small amplitude signal to a gate of a gated diode in a sampling mode and changing a voltage of a source of the gated diode in an evaluation mode. One or more isolation devices may be connected between each small amplitude signal and a gate of the gated diode, wherein the isolation device passes the small amplitude signal to the gate of the gated diode in the sampling mode, and isolates the small amplitude signal from the gate in the evaluation mode for amplification and performing fast logic operations (logic functions). The disclosed gated diode logic circuits overcome the Vt variation problem in FETs by detecting and amplifying the small logic signals utilizing gated diodes that have relatively low Vt variation.

Abstract: An AND circuit is provided, which has a first differential pair including a first transistor and a second transistor, to which a first input differential signal is inputted, a second differential pair including a third transistor and a fourth transistor, to which a fixed bias is inputted, a third differential pair including a fifth transistor and a sixth transistor, to which a second input differential signal is inputted, and in which the first differential pair is connected to the fifth transistor and the second differential pair is connected to the sixth transistor, and an output terminal, which is connected to the first or second transistor and outputs an AND signal or a NAND signal of the first and second input differential signals.

Abstract: A method and apparatus for ensuring proper operation of a dynamic circuit is provided. A dynamic circuit instance has a plurality of outputs connected to a respective one of a plurality of leakage detector circuits. An output of each leakage detector circuit is connected with a respective one of a plurality of keeper circuits that reside at the dynamic circuit. Each of the plurality of keeper circuits has a unique size ratio with respect to a logic element size of the dynamic circuit.

Abstract: A power management circuit for logic cells. A logic cell is operated in normal or standby modes according to a power control signal. The logic cell includes an output terminal and a power input terminal. A switch is coupled between a power voltage, the power control signal and the power input terminal. That switch is turned off to disconnect the power voltage and the logic cell when the power control signal is at a predetermined level. This results in the logic cell operating in standby mode. A latch circuit is coupled between the power voltage and the output terminal to preserve the voltage level of the output terminal when the logic cell operates in standby mode.

Abstract: A differential switching circuit has a first transistor connected between a first output node and a common node and a second transistor connected between a second output node and the common node. A switching driver generates first and second driving signals in response to an input data signal so as to complementarily drive the first and second transistors. A voltage level of at least one of the first and second driving signals is maintained so as to cause at least one of the first and second transistors to operate in a saturation region regardless of a voltage variation of at least one of the first or second output nodes when the at least one of the first and second transistors is turned on. Output impedance of the device is enhanced because the first and second transistors operate in the saturation region.

Abstract: Embodiments of the present invention perform logical operations utilizing a symmetric logic circuit comprising two logic units. In a symmetric logic circuit, the circuit configuration used to process a first logic input in the first logic unit is the same as the circuit configuration used to process a second logic input in the second logic unit, and the circuit configuration used to process the second logic input in the first logic unit is the same as the circuit configuration used to process the first logic input in the second logic unit. The present invention may be used for logic circuits that perform a variety of logical operations, such as XOR, AND, NAND, OR, or NOR.

Abstract: A programmable, equalizing buffer is provided having feedback transistors used to vary the transfer function of the equalizing buffer, such that a low pass response of a transmission channel is substantially equalized. A zero in the buffer's transfer function is established by a conductive state of transistors caused by signal feedback. Multiple transistors establish increased flexibility for establishing the location of the zero, while a cascade of buffer stages provides a second order transfer function effective to cancel second order channel effects.

Abstract: A power gated semiconductor integrated circuit comprises: (1) logic circuit to be power gated, said logic circuit having a virtual ground rail; (2) footer device disposed between said virtual ground rail and a ground rail for reducing power consumption of said logic circuit; and (3) virtual rail voltage clamp disposed electrically in parallel with said footer device for limiting the voltage at the virtual ground rail, the virtual rail voltage clamp comprising at least one NFET. A total of Nf NFETs are connected to the virtual ground rail of the integrated circuit for use as both virtual rail voltage clamps and footer devices. A quantity of Nmax-VC NFETs are scanned and perform the function of voltage clamps and the remaining (Nf?Nmax-VC) NFETs perform power gating. Manufacturing variability immunity and tuning of the variability immunity is achieved by adjusting the quantity Nmax-VC based upon testing of the manufactured integrated circuit.

Abstract: One embodiment of the present invention provides a circuit which blocks a keeper from interfering with a dynamic node during an evaluation phase for a dynamic wide-NOR structure. The circuit contains a precharge device which is coupled to the dynamic node. The precharge device precharges the dynamic node during a precharge phase. The circuit also contains a plurality of parallel pull-down transistors which are coupled to the dynamic node. The pull-down transistors conditionally discharge the dynamic node during the evaluate phase. The keeper sustains a precharged value on the dynamic node, thereby preventing a false evaluation caused by a leakage current through the parallel pull-down transistors. In addition, the circuit contains a feedback gating device which is coupled between the keeper and the dynamic node. During the evaluation phase, the feedback gating device blocks the keeper, so that the parallel pull-down transistors can discharge the dynamic node without interference from the keeper.

Abstract: A semiconductor device having a plurality of cascaded IC's (14, 15, 16), wherein the matching impedance between a signal transmission path (12) connected to an external signal transmission path and an input-side or output-side IC (14, 16) is set at 50 ohms which is equal to the characteristics impedance of the external signal transmission path. The matching impedance between a internal signal transmission path (13) and an input-side or output-side IC or intermediate IC is set at 200 ohms which is higher than the 50 ohms. The semiconductor device reduces the current dissipation and can operate at a higher speed.

Abstract: The present invention relates to dynamic hardware logic of computer processors. In particular, it relates to a method and respective system for operating a dynamic logic circuit implementing some predetermined logic function with reduced charge sharing. In order to further reduce charge sharing it is proposed to provide a predetermined number of pre-engineered switching arrangements (24, 26, 28) implementing the same logic function with a different combinatorial distribution of input variables (A, B, C), wherein each arrangement is connected between said precharged node of higher potential and a lower potential.

Abstract: A method and apparatus for creating a modified dynamic flip-flop avoids the power waste created by prior art dynamic flip-flops by including a conditional pre-charge control circuit and method. When the modified dynamic flip-flop is in a holding mode, i.e., in the clock disable state, the modified dynamic flip-flop does not use power pre-charging and discharging the internal dynamic node every cycle.

Abstract: A number of different dynamic circuits having improved noise tolerance and a method for designing same are provided. The circuits include a power supply node and a precharge node. Keeper circuitry is connected to the nodes and has a current-voltage characteristic that exhibits a negative differential resistance property to improve noise tolerance of the circuits.

Abstract: Optimizing fly ash resistivity by controlling concentration of sulfur trioxide (SO3) in flue gas by the use of an algorithm.

Abstract: A dynamic logic gate with a conditional keeper, the conditional keeper comprising a pMOSFET pull-up that switches ON only after the dynamic logic gate completes an evaluation so as to avoid contention with the pull-down network. By sizing the conditional keeper to be stronger than the half-keeper, embodiments may realize a significant reduction in soft error rates that are latched.