Abstract: An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB.

Abstract: A memory coupled to a programmable logic device (PLD) is configured through the PLD's JTAG port. A soft core loaded into the PLD connects to the JTAG port and memory. An external programming host device connects to the JTAG port, sends instructions and data to and receives data from the memory via the JTAG port and soft core. A synchronization JTAG instruction is loaded, and a Shift Data state of the JTAG port state machine is used. The programming host device and soft core are synchronized, and a memory chip select is asserted. A memory instruction, such as READ, WRITE or ERASE is loaded into the memory. An RTI state of the state machine is used to wait for instruction completion and the chip select is deasserted. Another instruction is processed starting with using the Shift Data state. Alternatively, a PLD Shift Data Register is used in conjunction with the soft core.

Abstract: A re-programmable gate logic includes a plurality of non-volatile re-configurable resistance state-based memory circuits in parallel, wherein the circuits are re-configurable to implement or change a selected gate logic, and the plurality of non-volatile re-configurable resistance state-based memory circuits are each adapted to receive a logical input signal. An evaluation switch in series with the plurality of parallel non-volatile re-configurable resistance state-based memory circuits is configured to provide an output signal based on the programmed states of the memory circuits. A sensor is configured to receive the output signal and provide a logical output signal on the basis of the output signal and a reference signal provided to the sensor. The reconfigurable logic may be implemented based on using spin torque transfer (STT) magnetic tunnel junction (MTJ) magnetoresistance random access memory (MRAM) as the re-programmable memory elements. The logic configuration is retained without power.

Abstract: A system on chip (SoC) integrated circuit includes a plurality of computational blocks. A modular data transfer architecture interconnects the computational blocks for intra-chip communications. The computational blocks include an initiator block and a target block, with the initiator block originating a data communication having a global address associated with the target block. The modular data transfer architecture includes a first peripheral module having an initiator port connected to the initiator block to receive the data communication and a second peripheral module having a target port connected to the target block. A first port mapper within the first peripheral module maps the global address to a first peripheral module target port along a data path towards the second peripheral module. A second port mapper within the second peripheral module maps the global address to the target port connected to the target block.

Abstract: Circuitry for facilitating the use of the memory elements in the look-up tables (“LUTs”) of a field programmable gate array (“FPGA”) as user-accessible, distributed RAM. For example, a register associated with a LUT and that is not needed in the read data path in user RAM mode can be used to register data for writing in user RAM mode. As another example, an otherwise unneeded register associated with a LUT can be used to provide a synchronous read address signal for user RAM mode. Several other features are shown for similarly facilitating user RAM mode with minimal (if any) additional circuitry being required in the FPGA.

Abstract: A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m.times.N where m is the number of word width bits per memory chip and N is the number of memory chips.

Abstract: In a programmable logic device, some or all of the parallel interconnect resources are replaced by serial interconnect resources within the device. Some or all of the functional blocks on the device are supplemented with serial interfaces. Although this makes the functional blocks more complex, it allows a significant reduction in the area consumed by interconnect resources. This translates into a significant reduction in device power consumption. The serial interfaces may operate synchronously from a global device clock (such as a PLL). In some cases, serial interfaces that are provided in the input/output blocks for external signalling can be omitted because the serial interfaces in the functional blocks can take over the external serial interface function as well, although in those cases the serial interfaces in the functional blocks would have to be more complex because they would have to be able to operate asynchronously with external devices.

Abstract: An apparatus and method of reducing power consumption across a switch, such as an unprogrammed antifuse, is provided. The invention applies to antifuses, other switches such as transistor based switches, (e.g., FLASH, EEPROM and/or SRAM) and other devices exhibiting a leakage current, especially during a sleep or stand-by mode. During a sleep mode, such switches or other devices may be uncoupled from signals driving the switches, then terminals of each switch may be coupled to a common potential or allowed to float to a common potential thereby eliminating or reducing leakage currents through the switches.

Abstract: Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric of some embodiments provides the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component continually performs operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the configurable IC.

Abstract: A metal configurable I/O structure for an integrated circuit is disclosed. The metal configurable I/O structure may be configured for one of any of a plurality of I/O specifications. Preferably a common voltage reference and a common current reference is generated for provision to a plurality of I/O structures.

Abstract: In a first aspect, a semiconductor storage device, comprising: a metal line coupled to a gate of an access transistor, wherein the gate material is deposited substantially above the metal line. In a second aspect, a semiconductor storage device, comprising: a first port to write data to a storage element; and a second port to read a signal generated by the storage element; and a first metal line coupled to a gate of an access transistor coupled to the first port; and a second metal line coupled to a gate of an access transistor coupled to the second port; wherein, the gates of said access transistors are formed on a gate material deposited substantially above the metal of first and second metal lines.

Abstract: In one embodiment, the invention is an integrated circuit (IC) including an OTP memory and conditioning circuitry. The IC receives an externally-generated DC programming voltage signal that the conditioning circuitry transforms into a programming pulse signal for programming the OTP memory. The conditioning circuitry includes: (i) reset protection circuitry for holding the programming pulse signal low if the IC is powering up, (ii) an overvoltage protection circuit for substantially preventing the programming pulse voltage from exceeding predefined boundaries, and (iii) a conversion switch for controlling the programming pulse voltage. The programming pulse voltage is (i) substantially equivalent to the externally-generated DC voltage if an enable signal is on, and (ii) substantially equivalent to a reference voltage if the enable signal is off.

Abstract: A configurable interface for an integrated circuit is described. The integrated circuit includes a first core, where the first core is an application specific circuit version of a Peripheral Component Interconnect Express (“PCIe”) interface device. First configuration memory cells are associated with the first core, and the first configuration memory cells are for configuring the first core. The first configuration memory cells are programmable responsive to a first portion of a configuration bitstream, and the configuration bitstream is capable of including user-logic information for programming programmable logic of the integrated circuit.

Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g.

Abstract: A structured ASIC device includes highly flexible clock signal routing to peripheral IO circuitry of the device. A plurality of peripheral IO circuits are divided into subpluralities of adjacent ones of those circuits. Each subplurality has associated clock signal routing that is mask-programmable to supply any of a plurality of clock signals to any of the IO circuits in the subplurality. Core circuitry of the structured ASIC includes clock signal distribution circuitry, and that distribution circuitry can supply (via buffers associated with each subplurality) the same plurality of clock signals to the routing circuitry associated with all of the subpluralities.

Abstract: A semiconductor device with a packaging circuit portion connected to a semiconductor chip therein. The semiconductor chip includes a plurality of pad electrodes, and the packaging circuit portion includes wiring connected to the pad electrodes on the semiconductor chip, mounting terminals, and a first signal path for receiving a signal output from the predetermined one of the pad electrodes and transmitting the signal to other one of the pad electrodes. The first signal path includes delay elements comparable to delays in a second signal path extending from the predetermined one of the mounting terminals to the other one of the mounting terminals through the semiconductor chip, and is disposed on a feedback path for phase comparison for synchronizing the phase of an output signal from the second signal path to the phase of an input signal to the second signal path.

Abstract: An integrated circuit includes a plurality of tiles. Each tile includes a processor, a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles, and a switch memory that stores instruction streams that are able to operate independently for respective output ports of the switch.

Abstract: Some embodiments of the invention provide configurable via programmable gate array (“VPGA”) with several configurable circuits arranged in a configurable circuit arrangement. In some embodiments, the configurable circuit arrangement is a configurable circuit arrangement that includes numerous (e.g., 50, 100, etc.) configurable circuits that are arranged in several rows and columns. This circuit arrangement also includes several direct offset connections, where each particular direct offset connection connects two configurable circuits that are neither in the same column nor in the same row in the circuit arrangement. In some embodiments, at least some direct offset connections connect pairs of circuits that are separated in the circuit arrangement by more than one row and at least one column, or by more than one column and at least one row. At least some of the configurable circuits are via programmable (“VP”) configured circuits.

Abstract: Dynamically configurable routing logic coupled between physical I/O ports and special purpose I/O associated with functions within a panel ASIC is disclosed that provide different routing configurations between the physical I/O ports and the special purpose I/O. In one routing configuration, any special purpose output can be coupled to one or more physical I/O ports, providing flexibility to route any functional I/O to any physical I/O port. In a second routing configuration, any input signal on a physical I/O port can be coupled to one or more special purpose inputs. In a third routing configuration, the input signals on a number of physical I/O ports can be configured to independently assert a single special purpose input for interrupt triggering. The dynamically configurable nature of the routing logic allows routing to be changed on the fly.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC). The configurable IC includes first and second interconnect circuits. The first interconnect circuit has a set of input terminals, a set of output terminals, and several connection schemes for communicatively coupling the input terminal set to the output terminal set. During the operation of the IC, the second connection circuit supplies sets of configuration data to the first interconnect circuit at a particular rate for at least a particular time period. At least two supplied configuration data sets are different and configure the first interconnect circuit to use two different connection schemes that differently couple the input and output terminal sets.

Abstract: A programmable logic integrated circuit device adapted to enter a low-power mode is described. The integrated circuit device includes a programmable logic block, a first low-power mode control circuit programmed into a portion of the programmable logic block, a second low-power mode control circuit, and a low-power enable input coupled to the first low-power mode control circuit and the second low-power mode control circuit. This arrangement allows the programmable logic integrated circuit device to transition into and out of low-power mode in response to a single signal from system control logic, so that the system control logic can be designed without detailed understanding of the inner workings of the programmable logic integrated circuit device or its programmed design.

Abstract: A control circuit includes a crossbar array having input columns and output rows configured to store first stored data in the form of high or low resistance states. The input columns are connected to a common electrical input and the output rows are connected to a common summing circuit. The crossbar control circuit may be implemented in a control system to provide for adjustment of the control system to changes in environmental conditions.

Abstract: A programmable logic structure is disclosed employing input logic routing cell (ILRC) multiplexers and output logic routing cell (OLRC) multiplexers for making local connections between dedicated logic cells. In a simple programmable logic structure, a dedicated logic cell (DLC) is implemented in a programmable logic structure comprising multiple ILRC multiplexers for port A and multiple OLRC multiplexers for port B. In a multi-level programmable logic structure, multiple columns of dedicated logic cells is designed with columns of dedicated local cells adjacent to each other where each DLC column is used to implement a particular logic function. In a first embodiment, local connections can be made between dedicated logic cells, e.g. an OLRC in a first DLC at level L making local point-to-point connections to an ILRC in a second DLC at level L+1.

Abstract: Integrated circuits (ICs) having novel handshake logic are provided. An IC includes a ready multiplexer, an acknowledge demultiplexer, a C-element coupled to the ready multiplexer and the acknowledge demultiplexer, a logic gate, and a storage element (e.g., a latch). The logic gate has a first input coupled to a control output of the C-element, and a second input. The storage element includes a data multiplexer and a latch. The data multiplexer has M data inputs coupled to data inputs of the storage element, a select input coupled to the output of the logic gate, and a data output, M being an integer greater than one. The latch has a data input coupled to the data output of the first data multiplexer and an output coupled to an output of the storage element. The logic gate can be a logical AND gate with the second input coupled to a memory cell.

Abstract: Disclosed is a design structure for systems and methods of managing a set of programmable fuses on an integrated circuit.

Abstract: An integrated circuit device includes a first predriver that drives an N-type power MOS transistor of an external driver including the N-type power MOS transistor and a P-type power MOS transistor, a second predriver that drives the P-type power MOS transistor, a low-potential-side power supply pad, a first output pad, a second output pad, and a high-potential-side power supply pad. The low-potential-side power supply pad, the first output pad, the second output pad, and the high-potential-side power supply pad are disposed along a first direction. The first predriver is disposed in a second direction with respect to the low-potential-side power supply pad and the first output pad, the second direction being a direction that is perpendicular to the first direction, and the second predriver is disposed in the second direction with respect to the second output pad and the high-potential-side power supply pad.

Abstract: In one embodiment of the invention, a programmable logic device comprises configuration memory adapted to store configuration data and a plurality of programmable logic blocks. At least one programmable logic block includes a plurality of dual-slice logic blocks, each dual-slice logic block including first and second slices, each slice including at least two lookup tables (LUTs) and a register. The programmable logic block further includes control logic adapted for selecting control signals separately at a programmable block level, a dual-slice block level, and a register level, the control logic responsive to configuration data stored within the configuration memory.

Abstract: An integrated circuit is provided that contain n-channel and p-channel metal-oxide-semiconductor transistors having body terminals. Adjustable transistor body bias circuitry is provided on the integrated circuit that provides body bias voltages to the body terminals to minimize power consumption. The adjustable body bias circuitry can be controlled using programmable elements on the integrated circuit that are loaded with configuration data. The integrated circuit may be a programmable logic device integrated circuit containing programmable logic. The adjustable body bias circuitry can produce an adjustable negative body bias voltage for biasing n-channel metal-oxide-semiconductor transistors. The adjustable body bias circuitry contains a bandgap reference circuit, a charge pump circuit, and an adjustable voltage regulator.

Abstract: An integrated circuit apparatus includes a reconfigurable arithmetic operation device and a control device that generates mapping data defining a circuit configuration of the reconfigurable arithmetic operation device whose circuit configuration is changed while a given application is running and another application is newly implemented and run. The control device generates mapping data defining an intermediate configuration to shift from a circuit configuration defined by first mapping data to a configuration defined by final mapping data through the intermediate configuration.

Abstract: Method and apparatus for testing input/output circuits of an integrated circuit are described. An integrated circuit includes input/output circuits having input/output pads. The input/output pads are capable of being coupled together to a tester channel. The input/output circuits each are configurable via configuration circuitry to be in either a first mode or a second mode responsive to a select circuit of the configuration circuitry coupled to receive a first input for the first mode and a second input for the second mode. The select circuit is controlled responsive to a control select signal common to all or a portion of the select circuits of each of the input/output circuits.

Abstract: Some embodiments provide a method that outputs from a configurable IC a first set of data bits from a trace buffer. Each bit of the first set of data bits is simultaneously generated in the configurable circuits and, in some embodiments, multiple data bits of the first set of data bits do not reach the traced buffer simultaneously. The method also determines a set of relative delays for the first set of data bits and arranges the first set of data bits into a second set of data bits by compensating for the relative delays.

Abstract: A turning structure for routing channels in a field programmable gate array, comprising a first plurality of routing channels having a first direction and a second plurality of routing channels having a second direction. The first plurality of routing channels intersects the second plurality of routing channels to form a plurality of matrices of intersecting interconnect conductors in the routing channels. A first number of reprogrammable elements is disposed at intersections in at least one of the plurality of matrices, a second number of reprogrammable elements disposed at intersections in at least one of the plurality of matrices. The second number of reprogrammable elements is greater than the first number of reprogrammable elements, and a third number of reprogrammable elements disposed at intersections in at least one of the plurality of matrices. The third number of reprogrammable elements is greater than the second number of reprogrammable elements.

Abstract: A programmable logic device architecture providing efficient configurable functionality to allow the “tie-off” of logic region-wide control signals. This functionality is provided while maintaining the efficiency of region-wide signals, yet allows sufficient flexibility for effective use of register-packing and usage within the region. Methods are given for both sub-region and individual logic element tie-off granularity. In various embodiments, the tie-off logic may be used for logic wide signals used in PLDs having logic elements arranged in regions of logic, sometimes referred to in the industry as either Logic Array Blocks or Complex Logic Blocks.

Abstract: A driving waveform circuit includes a crossbar array having input columns and output rows wherein the crossbar array is configured to store data in the form of high or low resistance states, delay timing circuitry electrically connecting an input signal to the input columns of the crossbar array and configured to provide a relative delay timing between the input signal and each input column, and summation circuitry electrically connected to the output rows of the crossbar array for generating one or more output signals based on the stored resistance state data and the input signal. The driving waveform circuit is taught to be applied as inkjet printing drivers, micromirror drivers, robotic actuators, display device drivers, audio device drivers, computational device drivers, and counters.

Abstract: Methods and apparatus for novel routing structures and methods that improve fitting of user-defined functions onto programmable logic devices. In particular, second time fitting is improved. Exemplary structures and methods include allowing product terms to be expanded using inputs from more than one neighboring macrocell by providing multiple expansion and bypassing paths. Also, product term OR shifting prevents macrocell output stages from being buried and made inaccessible, and macrocell outputs are provided on expander word lines, increasing efficiency of those lines, as well as conserving routing resources. Expansion, bypassing, OR shifting, and expander word lines may terminate at logic array block boundaries or may continue beyond these boundaries to other logic array blocks.

Abstract: A technique that unfolds the nMOS-tree multiplexer to improve the propagation delay and/or active power consumption is provided. The main idea is to replicate the nMOS element of the downstream buffer, where each replica is driven by a signal that originates from earlier stages of the nMOS-tree multiplexer. This way, when passing high logic values, signals from earlier stages directly drive the downstream buffer improving the delay or the slope of the transition edge (with beneficial effects for power consumption). The passing of low logic values is still performed in the original way by the nMOS tree and the pMOS element of the downstream buffer.

Abstract: Some embodiments provide a circuit for accessing stored data in a configurable IC that includes several configurable circuits. The IC also includes several storage circuits. Each storage circuit has (1) several storage elements for storing data for the configurable circuits, and (2) output circuitry for outputting data stored in the storage elements. The output circuitry includes a first set of interconnects for receiving at least a first repeating periodic signal and for periodically outputting data from at least two storage elements to the configurable circuits.

Abstract: Apparatus and method aspects for power gating of an integrated circuit (IC) include providing at least one I/O power pad of an IC with a switch arrangement. The at least one I/O power pad is utilized to control a power signal transfer to at least a portion of the IC.

Abstract: Some embodiments of the invention provide a configurable IC that includes several configurable computational tiles and several memory tiles. These tiles are arranged in a particular tile arrangement. Each computational tile has a set of configurable logic circuits for configurably performing a plurality of computations and a set of configurable routing circuits. The routing circuits of the tiles configurably route signals between configurable logic circuits. The configurable IC also has several memory arrays for storing data on which the logic circuit perform computation. The memory arrays are embedded in the tile arrangement between two sets of memory tiles, where each set of memory tiles includes a set of routing circuits. In this IC, at least a first memory tile has the same set of configurable routing circuits as at least a second computational tile.

Abstract: A device includes a first crossbar array having first input columns and first output rows, wherein a plurality of the rows of the first crossbar array are configured to store first stored data in the form of high or low resistance states, and a second crossbar array having second input columns and second output rows, wherein a plurality of the rows of the second crossbar array are configured to store second stored data in the form of high or low resistance states. The second stored data is a complement of the first stored data and the first output rows are electrically connected to the second output rows. The device provides for data storage and comparison for computer processing, audio/speech recognition, and robotics applications.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes an interconnect circuit having a first set of input terminals and a set of output terminals. The interconnect circuit has several connection schemes for connecting the first input set to the output set. The IC also has a second set of input terminals for carrying a set of input signals, where at least several of the second set of input terminals overlap at least a plurality of the first set of input terminals. The IC further has a set of vias, where each via connects an input terminal in the first set with an input terminal in the second set. The interconnect circuit receives a control signal and based on this control signal connects the first input terminal set to the output set by using a particular one of the connection schemes.

Abstract: An FPGA is laid out as a plurality of repeatable tiles, wherein the tiles are disposed in columns that extend from one side of the die to another side of the die, and wherein each column includes tiles primarily of one type. Because substantially all die area of a column is due to tiles of a single type, the width of the tiles of each column can be optimized and is largely independent of the size of the other types of tiles on the die. The confines of each type of tile can therefore be set to match the size of the circuitry of the tile. Rather than providing a ring of input/output blocks (IOBs) around the die periphery, IOB tiles are disposed in columns only. Where more than two columns worth of IOBs is required, more than two columns of IOB tiles can be provided.

Abstract: A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect a first plurality of conductors to other multiple sets of conductors in a generally unrestricted fashion within respective interconnect resources constraints. The SN can be applied in a wide range of applications, in tandem or hierarchically, to provide a large switch network used in network, routers, and programmable logic circuits. The SN is used to connect a first set of conductors, through the SN, to multiple sets of conductors in a given logic circuit hierarchy whereby the conductors in each of the multiple sets are equivalent or exchangeable, which in term, by construction, makes the first set of conductors equivalent when used in the next level of circuit hierarchy. The SN is scalable for large sized sets of conductors and can be used hierarchically to enable programmable interconnections among large sized circuits.

Abstract: Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE-Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.

Abstract: A system including a plurality of programmable logic blocks, a plurality of special-purpose blocks, and a configurable high-speed mesh interconnect fabric operatively connecting the plurality of programmable logic blocks and the plurality of special-purpose blocks, where the configurable high-speed mesh interconnect fabric is configured to implement a plurality of interconnect pipeline buses spanning across the system.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes at least fifty configurable circuits arranged in an array having a plurality of rows and a plurality of columns. Each configurable circuit for configurably performing a set of operations. At least a first configurable circuit reconfigures at a first reconfiguration rate. The first configurable circuit performs a different operation each time the first configurable circuit is reconfigured. The reconfiguration of the first configurable circuit does not follow any sequential progression through the set of operations of the first configurable circuit.

Abstract: In one embodiment, a programmable logic device includes: a multiplexer adapted to select a compressed configuration bitstream from a plurality of external serial interface memories; a serial interface processor adapted to command the bitstream selection by the multiplexer; and a bitstream decompressor adapted to decompress the selected configuration bitstream into a decompressed configuration bitstream.

Abstract: Systems and methods are disclosed herein to provide improved non-volatile storage techniques for programmable logic devices. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of logic blocks, a plurality of input/output blocks, and a volatile memory to store data within the programmable logic device, with configuration memory adapted to store first configuration data for configuration of the logic blocks, the input/output blocks, and the volatile memory of the programmable logic device. The programmable logic device further includes a non-volatile memory adapted to store data provided from the volatile memory.

Abstract: An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines layout regions between adjacent ones of the data dependency comparator blocks in the rows. Tag assignment logic blocks are coupled to the data dependency comparator blocks to receive dependency information. The tag assignment logic blocks are positioned in one or more of the layout regions so as to be integrated with the data dependency comparator blocks to conserve area on the semiconductor chip and to spatially define a channel in and substantially orthogonal to one or more of the rows. Register file port multiplexer blocks are coupled to output lines of the tag assignment logic block adjacent to the orthogonal channel to receive tag information and to pass the tag information to address ports of a register file.

Abstract: A programmable logic device (PLD) includes electrically programmable fuses that may be programmed with an identifier of the PLD. The PLD also includes programmable tiles and an interface port that is coupled to a shift register and a subset of the programmable tiles. The interface port includes a control port and a first and second serial data signals. The shift register has a parallel input port to load the identifier from the set of electrically programmable fuses in response to a read command of the control port. The shift register serially shifts by one bit in response to a shift command of the control port, including shifting a bit from the subset of the programmable tiles to the shift register via the first serial data signal and shifting a bit from the shift register to the subset of the programmable tiles via the second serial data signal.