Abstract: The invention includes a design structure embodied in a computer readable medium for performing a method for inserting a scan chain into a VLSI circuit design. The scan chain structure, or structures, are included in the design structure for the VLSI circuit design. The scan chain structure includes a first flip-flop (L1) and a second flip-flop (L2) configured to operate the first flip-flop (L1) in normal mode operation, in scan mode operation, in initialization mode and in low leakage power mode operation. A buffer circuit is electrically connected between the scan-out output of the second flip-flop (L2) and the scan-in input of the first flip-flop (L1) for the next latch in the scan chain. Buffer circuit control elements control the first flip-flop (L1) to switch between scan mode or low power leakage mode. The switching occurs in only one clock cycle.

Abstract: A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits.

Abstract: Apparatus, systems, and methods disclosed herein may cause an event trigger state machine associated with a programmable on-chip logic analyzer (POCLA) to transition to a programmable state at a programmable number of occurrences of a programmable set of events associated with a first subset of signals on a first subset of input signal paths. States associated with a second subset of signals on a second subset of input signal paths may be stored at a time relative to a transition to the programmable state if a set of storage criteria have been met. Additional embodiments are disclosed and claimed.

Abstract: Disclosed is a method of minimizing clock uncertainty using a multi-level de-skewing technique. The method includes the steps of obtaining a chip wherein at least a portion of the chip has a regular array of buffers on multiple levels, the buffers being driven by first drivers and the first drivers being driven by second drivers; grouping the buffers in a first direction to create clusters with the same number of buffer inputs, wherein if there are not the same number of buffer inputs in each cluster, then adding dummy buffers to the cluster with a deficient number of buffer inputs; wiring outputs of the first drivers together in a second direction, wherein the first and second directions are orthogonal; and wiring outputs of the second together in the second direction.

Abstract: Circuits comprising asynchronous linear pipelines and one-phase pipelines, and methods of forming asynchronous linear pipeline circuits and converting them to one-phase pipeline circuits are provided. Additional circuits, systems and methods are disclosed.

Abstract: Method and apparatus for processing scalable content having a base layer and at least one enhancement layer is described. In one example, static logic having decoder logic and system monitor logic is provided. Programmable logic having a plurality of reconfigurable slots is also provided. The decoder logic includes a base layer processor for processing the base layer of the scalable content. The system monitor logic is configured to dynamically reconfigure at least one of the plurality of reconfigurable slots with at least one enhancement block for processing the at least one enhancement layer of the scalable content.

Abstract: A programmable integrated circuit performs an initial partial configuration of the programmable integrated circuit in response to receiving an activation signal. In this way, the programmable integrated circuit enables an initial functionality of the programmable integrated circuit. The programmable integrated circuit then performs a subsequent partial configuration of the programmable integrated circuit for enabling additional functionality of the programmable integrated circuit. In some embodiments, the programmable integrated circuit receives an input signal indicating a stimulus in an environment of the programmable integrated circuit and determines based on the input signal whether to perform the subsequent partial configuration of the programmable integrated circuit or generate a power down signal for powering down the programmable integrated circuit without performing the subsequent partial configuration.

Abstract: A semiconductor integrated circuit device and a fabrication method thereof are disclosed, for effective suppression of a temperature increase therein that is caused by heat generation of a semiconductor element. The semiconductor integrated circuit device includes a semiconductor element, a multi-layer wiring structure and a heat conduction part. The semiconductor element is formed on a support substrate. The multi-layer wiring structure is formed in an insulation film on the support substrate and includes at least one connection hole and at least one metal wiring layer. The heat conduction part is formed of the same conductive materials as the connection hole and the metal wiring layer and extends toward an upper layer side along a path different from a wiring path including a connection hole and a metal wiring for signal transmission.

Abstract: A programmable interconnect network for an array of logic cells. Said interconnect network has a plurality of switch boxes being connected in a tree structure and providing connections to its logic cells, switch boxes located at the lowest level of the tree structure are connected to logic cells; said interconnect network also has peripheral switch boxes, of which at least one is connected to an external logic. Also, an integrated circuit comprising an FP array of logic cells connected by the said programmable interconnect network and a mask programmable (MP) logic array.

Abstract: A logic cluster for a field programmable gate array integrated circuit device is disclosed. The cluster comprises a plurality of functional blocks and three levels of routing multiplexers. External signals enter the logic cluster primarily at the third level multiplexers with a few signals entering at the second level. Combinational outputs are fed back into the first and second level multiplexers while sequential outputs are fed back into the third level multiplexers. The logic function generators have permutable inputs with varying propagation delays. Routing signals between the first and second level multiplexers are grouped into speed classes and coupled to first level multiplexers associated with different logic function generators according to their speed class. Second and third level multiplexers are organized into groups such that routing signals between the second and third level multiplexers can be localized within the area occupied by the group.

Abstract: Message send and receive blocks are provided to emulation ICs and reconfigurable interconnect ICs of an emulation system to reduce the multiplexed transfer latency of critical emulation signals. Each of a corresponding pair of a message send block and a message receive block is provided with a signal state value inclusion schedule to control operation of the message send and receive blocks. The signal state inclusion schedule calls for some signals within a message to be sent more often than other signals within the message. In some embodiments a parity value is implemented as part the message and included in the signal state inclusion schedule.

Abstract: In the present invention, a decoupling capacitance circuit, a first output terminal and a second output terminal are provided. The decoupling capacitance circuit comprises a TDDB control circuit consisting of a first Tr and a second Tr, and a third Tr. Conductivity types of the first and second Trs are different from each other. A source of the first Tr is connected to a first power supply wiring, and a drain of the first Tr is connected to a gate of the second Tr. A source of the second Tr is connected to a second power supply wiring, and a drain of the second Tr is connected to a gate of the first Tr. The third and first Trs have the same conductivity type. A source and a drain of the third Tr are connected to the first power supply wiring, and a gate of the third Tr is connected to the drain of the second Tr. The first output terminal is connected to the drain of the first Tr, and the second output terminal is connected to the drain of the second Tr.

Abstract: An integrated circuit includes a programmable logic unit and an on-chip non-volatile memory. A JTAG port, TAP controller circuit, and program/erase control circuitry provide user access to the non-volatile memory for storage of user data. The non-volatile memory may also be used to store device data such as a serial number, product identification number, date code, or security data. Portions of the non-volatile memory may be made unavailable to the user once programmed, while other portions of the non-volatile may remain available for user access.

Abstract: An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks through buffers having a controllable ground connection NGND, at least some of the switches being a tie-off switch coupleable to one of a plurality of bitlines B, each bitline associated with column.

Abstract: A configurable circuit of the present invention includes a plurality of logic blocks (4), and a programmable bus which can program connections of plurality of logic blocks (4). The programmable bus includes a plurality of wires (11—x) arranged for each of signal transmission ranges corresponding to plurality of logic blocks (4), direct wire connection switch (711—x) which can program whether to directly connect or disconnect the wires between the adjacent signal transmission ranges, input selector (30—x) which can program a connection with any one of the plurality of wires, and programmable switch (40—x) which can program whether to make a connection with the wire corresponding to the adjacent signal transmission range for each of the plurality of wires. A plurality of programmable switches (40—x) are arranged for at least one of plurality of logic blocks (4).

Abstract: The present invention provides integrated circuits with improved logic cells. In one embodiment, an integrated circuit having a plurality of logic cells (LC) is provided, each LC comprising: a lookup table having a LUT output terminal; and, a first multiplexer; wherein, a first multiplexer input terminal is connected to of a first input terminal of the LC, a second multiplexer input terminal is connected to the LUT output terminal, a multiplexer output terminal is connected to a first output terminal of the LC, and a multiplexer select terminal is connected to a second input terminal of the LC so as to select which of the signals appearing at the first and second multiplexer input terminal to pass through; wherein, by coupling in chain the first input terminal of one LC to the first output terminal of another LC, a WLUT chain is formed.

Abstract: Spin torque magnetic logic devices that function as memory devices and that can be reconfigured or reprogrammed as desired. In some embodiments, the logic device is a single magnetic element, having a pinned layer, a free layer, and a barrier layer therebetween, or in other embodiments, the logic device has two magnetic elements in series. Two input currents can be applied through the element to configure or program the element. In use, logic input data, such as current, is passed through the programmed element, defining the resistance across the element and the resulting logic output. The magnetic logic device can be used for an all-function-in-one magnetic chip.

Abstract: Spin torque magnetic logic device having at least one input element and an output element. Current is applied through the input element(s), and the resulting resistance or voltage across the output element is measured. The input element(s) include a free layer and the output element includes a free layer that is electrically connected to the free layer of the input element. The free layers of the input element and the output element may be electrically connected via magnetostatic coupling, or may be physically coupled. In some embodiments, the output element may have more than one free layer.

Abstract: A semiconductor integrated circuit device 1 includes a plurality of basic cells 5 each having therein a logic transistor 2 that performs logical operations, and a power switching transistor 3 that can interrupt leakage current when the logic transistor 2 is not operated. The semiconductor integrated circuit device 1 further includes a wiring 6 that connects virtual power nodes 4 as the connection points between the logic transistors 2 and the power switching transistors 3, between individual basic cells 5a and 5b included in a plurality of basic cells 5. Here, a basic cell includes a power switching transistors 3 that can interrupt leakage current when the logic transistors 2 are not operated, in addition to the logic transistors 2. Thereby, switching transistors 3 can be disposed in the optimal positions of the cells 5, and basic cells 5 having a small restriction in disposition and wide scope of application can be provided.

Abstract: Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.

Abstract: A semiconductor integrated circuit (100) according to the present invention includes a plurality of reconfigurable cores (101) arranged separately from each other in a matrix, and a first group of register circuits (102) formed between a first and second reconfigurable cores included in the reconfigurable cores (101). Each of the reconfigurable cores (101) operates synchronously with clock signals and has a logic reconfiguration function, and includes a plurality of logic elements (201) that implements predetermined logic and programmable wiring (202 and 203) that interconnects the plurality of logic elements (201). The first group of register circuits (102) temporarily holds output from the first reconfigurable core and transfers the output to the second reconfigurable core.

Abstract: A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits.

Abstract: Disclosed is a programmable logic device (“PLD”) including at least one lookup table (“LUT”) based logic element (“LE”) of a first type and at least one LUT based LE of a second type. The first type of LE is different from the second type of LE. The term ‘different’ when used herein to describe the relationship of a first logic structure and/or its components to a second logic structure and/or its components indicates a difference in hardware design as opposed to a configuration difference or non-designed differences resulting, for example, from manufacturing variability. Additionally, a PLD can include at least one logic array block (“LAB”) of a first type having at least one LUT based LE and at least one LAB of a second type having at least one LUT based LE. The first type of LAB being different from the second type of LAB.

Abstract: A device includes an array of electrodes configured for attachment in or on the human head interconnected to control circuitry via a programmable crossbar signal processor having reconfigurable resistance states. In various embodiments the device may be used as a controller for a video game console, a robotic prosthesis, a portable electronic device, or a motor vehicle.

Abstract: An extensible three dimensional circuit includes an access layer and crossbar arrays overlying the access layer. The crossbar arrays are formed from tiled mini-arrays of crossing lines and electrically accessed by the access layer. The crossing lines comprise at least one bundle of traveling lines, the at least one bundle of traveling lines moving through the circuit both laterally and vertically. Programmable crosspoint devices are disposed between the crossing lines.

Abstract: A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m*N where m is the number of word width bits per memory chip and N is the number of memory chips.

Abstract: Embodiments generally describe techniques for an integrated circuit having a physical unclonable function (PUF). Example integrated circuits may include an input circuit having an input network, a configurable delay circuit having one or more configurable delay chains, and an output circuit having one or more arbiters, serially coupled together. Each delay chain may include a number of serially coupled configurable switching-delay elements adapted to receive, configurably propagate, and output two delayed signals. Each delay chain may be configured using configuration signals responsively output by the input network in response to challenges provided to the input network. The output circuit may further include an output network to generate combined output signals based on the signals output by the arbiters. Each of the input and/or output networks may comprise combinatorial logic, sequential logic, or another PUF, which may be of the same design. Other embodiments may be disclosed and claimed.

Abstract: An integrated circuit, such as a field programmable gate array or other configurable logic device, has an interconnect circuit selectively configurable to operate in a high-speed mode or in a low-power mode. The interconnect circuit is operable from a higher voltage supply or a lower voltage supply to change operating modes without reconfiguring data paths.

Abstract: Modifying a layout of an integrated circuit (IC) based on a function of an interconnect therein and a related circuit and design structure are disclosed. In one embodiment, a method includes identifying a function of an interconnect in the layout from data of the layout embodied in a computer readable medium; and modifying the layout to form another layout that accommodates the function of the interconnect. A design structure embodied in a machine readable medium used in a design process, according to one embodiment, may include a circuit including a high voltage interconnect positioned in a dielectric layer, the high voltage interconnect positioned such that no fill is above or below the high voltage interconnect.

Abstract: Provided is a logic gate device capable of performing multiple logic operations by using a single logic gate circuit. The multi-functional logic gate device includes a pull-up switching unit having input switches of a first group being respectively connected to multiple input terminals and selection switches of the first group connected to either a selection terminal or a logically inverted selection terminal, the pull-up switching unit electrically connecting the input switches of the first group in series or in parallel between a power source and an output terminal according to logic levels of the selection terminal and the inverted selection terminal.

Abstract: In one embodiment, the integrated circuit has a L-level permutable switching network (L-PSN) comprising L levels of intermediate conductors. The integrated circuit can be used in electronic devices, such as switching networks, routers, and programmable logic circuits, etc.

Abstract: A programmable device operates at high speed while reducing power consumption. The programmable device includes a plurality of processing tiles each including a configuration memory and a core logic unit, a configuration control unit for programming them, and a power control unit for cutting off a power supply depending on an operating state. The power supply of the core logic unit is cut off after saving the internal state of the core logic unit in the configuration memory, and power is supplied again to the core logic unit before the internal state is restored from the configuration memory to the core logic unit, thus saving power while maintaining the internal state.

Abstract: A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect a first plurality of conductors to other multiple sets of conductors in a generally unrestricted fashion within respective interconnect resources constraints. The SN can be applied in a wide range of applications, in tandem or hierarchically, to provide a large switch network used in network, routers, and programmable logic circuits. The SN is used to connect a first set of conductors, through the SN, to multiple sets of conductors in a given logic circuit hierarchy whereby the conductors in each of the multiple sets are equivalent or exchangeable, which in term, by construction, makes the first set of conductors equivalent when used in the next level of circuit hierarchy. The SN is scalable for large sized sets of conductors and can be used hierarchically to enable programmable interconnections among large sized circuits.

Abstract: Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.

Abstract: Methods for applications such as signal processing, analysis, and coding/decoding replace digital signal processing elements with analog components are implemented by combining soft logic gates and filters, permitting the functionality of complex finite state machines to be implemented.

Abstract: An integrated circuit includes an auto-bridging architecture including a first phases block that interfaces to a first user block having a first user signal domain. The first phases block converts the first user signal domain to a common signal domain. A second phases block coupled to the first phases block interfaces with a second user block having a second user signal domain. The second phases block converts the second user signal domain to the common signal domain so that the first user block cooperates with the second user block through the auto-bridging architecture of the IC.

Abstract: A method and apparatus involves operating a circuit having a test circuit interrupt input terminal (INTERRUPT), having a test circuit clock output terminal (DUT_CLK), and having first and second operational modes. In the first operational mode the circuit supplies a test circuit clock signal to the test circuit clock output terminal. The circuit responds to receipt of an occurrence of a test circuit interrupt at the test circuit interrupt input terminal by then operating in the second operational mode. In the second operational mode the circuit refrains from supplying the test circuit clock signal to the test circuit clock output terminal.

Abstract: A logic gate array is provided. The logic gate comprises a silicon substrate, a first logic gate layer on top of the silicon substrate, a second logic gate layer on top of the first logic gate layer, and a routing layer between the first and second logic gate layers for routing magnetic gates in the first and second logic gate layers, wherein the first logic gate layer, the second logic gate layer, and the routing layer are electrically connected by vias.

Abstract: A semiconductor integrated circuit has a voltage supply terminal; a first input terminal fed with a first input signal; an output terminal that outputs an output signal; a second input terminal fed with a second input signal; a first MOS transistor having one end connected to the voltage supply terminal and a gate electrode connected to the first input terminal; a second MOS transistor having one end connected to a first potential, an other end connected to the output terminal, and a gate electrode connected to the second input terminal; and a program element acting as a MOS transistor having one end connected to the other end of the second MOS transistor and an other end connected to a second potential higher than the first potential.

Abstract: A wiring design system for semiconductor integrated circuit which realizes a low power consumption in a grid-shaped clock wiring within a semiconductor integrated circuit is provided. A wiring design system 10 for semiconductor integrated circuit which designs the gird-shaped clock wiring for uniformly distributing the clock signals to the flip flop circuits arranged within the semiconductor integrated circuit, wherein, of the clock wiring lines forming the grid-shaped clock wiring, a clock wiring line having a smaller effect on the distribution operation of the clock signals in the grid-shaped clock wiring is selected and thinned out as a less necessary clock wiring line.

Abstract: An apparatus having a plurality of first circuits, second circuits, third circuits and fourth circuits is disclosed. The first circuits may be configured to generate a plurality of first signals in response to (i) a priority signal and (ii) a request signal. The second circuits may be configured to generate a plurality of second signals in response to the first signals. The third circuits may be configured to generate a plurality of enable signals in response to the second signals. The fourth circuits may be configured to generate collectively an output signal in response to (i) the enable signals and (ii) the request signal. A combination of the first circuits, the second circuits, the third circuits and the fourth circuits generally establishes a programmable priority encoder. The second signals may be generated independent of the enable signals.

Abstract: The invention in the simplest form is a programmable logic device comprising logic blocks configured substantially in a plane, external I/O endpoints, and embedded switched fabrics which provide non-contentious connection between the logic blocks and between logic blocks and I/O endpoints, the switch fabrics being offset from the plane of the logic blocks. The logic blocks are organized into logic groups, whereby a plurality of primary embedded switch fabrics are configurable for connecting logic blocks within logic groups, and at least one secondary switch fabric provides non-contentious connection between primary switch fabrics. The switch fabrics can employ non-blocking crossbar switches. A hierarchy of secondary switch fabrics can be included for providing non-contentions connection between both primary and other secondary switch fabrics.

Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g.

Abstract: An integrated circuit system comprising: providing a substrate; forming a main feature using a first non-cross-junction assist feature over the substrate; forming the main feature using a second non-cross-junction assist feature, adjacent a location of the first non-cross-junction feature, over the substrate; and forming an integrated circuit having the substrate with the main feature thereover.

Abstract: Some embodiments provide a circuit for accessing stored data in a configurable IC that includes several configurable circuits. The IC also includes several storage circuits. Each storage circuit has (1) several storage elements for storing data for the configurable circuits, and (2) output circuitry for outputting data stored in the storage elements. The output circuitry includes a first set of interconnects for receiving at least a first repeating periodic signal and for periodically outputting data from at least two storage elements to the configurable circuits.

Abstract: A microcontroller with analog/digital Programmable System On-a-Chip (PSoC) architecture including multiple digital PSoC blocks and multiple analog PSoC blocks in a communication array having a programmable interconnect structure. The single chip design is implemented by integration of programmable digital and analog circuit blocks that are able to communicate with each other. Robust analog and digital blocks that are flash memory programmable can be utilized to realize complex design applications that otherwise would require multiple chips and/or separate applications. The PSoC architecture includes a novel array having programmable digital blocks that can communicate with programmable analog blocks using a programmable interconnect structure. The programmable analog array contains a complement of Continuous Time (CT) blocks and a complement of Switched Capacitor (SC) blocks that can communicate together.

Abstract: A method of designing a wiring structure of an LSI is capable of reducing a capacitance variation ratio ?C/C or a resistance-by-capacitance variation ratio ?(RC)/(RC) of the wiring structure.

Abstract: A flip-flop for use in a field programmable gate array integrated circuit device is disclosed. The flip-flop comprises a data output terminal coupled to a first programmable routing element, a data input terminal coupled to a second programmable routing element, and a clock input terminal, wherein a signal appearing at the data output terminal in response to a signal applied to the clock input terminal has the opposite logical polarity with respect to the corresponding logical signal applied to the data input terminal.

Abstract: A programmable logic device having a Logic Element with an N-stage Look Up Table (LUT), dedicated hardware for performing a non-LUT logic function, and an over-ride element configured to selectively force a muxing stage within the N-stage LUT to select either one or more LUT configuration bit inputs or the output of the non-LUT logic function as the output of the LUT. In various embodiments, the non-LUT functions can include addition, subtraction, multiplication, division, digital signal processing, memory storage, etc.

Abstract: A semiconductor device includes multiple functional blocks, each having a predetermined function, and wiring regions on a substrate where a signal line is provided. The semiconductor device also includes multiple standard cells disposed in the wiring regions along the signal line, each of which operates with a substrate bias potential, and multiple contact cells disposed in the wiring region in parallel with the wiring direction of the signal line, each being associated with each of the multiple standard cells and providing the substrate bias potential to the associated standard cell.