Supply Voltage Level Shifting (i.e., Interface Between Devices Of A Same Logic Family With Different Operating Voltage Levels) Patents (Class 326/80)
  • Patent number: 11567516
    Abstract: A power management circuit includes an inverter circuit and a latch circuit. The inverter circuit is configured to receive a first control signal from an inverter input terminal and generate a second control signal at an inverter output terminal. The first control signal carries power status information of a first supply voltage. The latch circuit has a latch supply terminal, a first latch input terminal and a second latch input terminal. The latch supply terminal is coupled to a second supply voltage becoming ready before the first supply voltage. The first latch input terminal and the second latch input terminal are coupled to the inverter output terminal and the inverter input terminal respectively. The latch circuit is configured to generate a third control signal according to respective signal levels of the first control signal and the second control signal, and accordingly perform power control of an integrated circuit.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: January 31, 2023
    Assignee: M31 TECHNOLOGY CORPORATION
    Inventors: Ching-Hsiang Chang, Chih-Chieh Yao, Chun-Hsiang Lai
  • Patent number: 11362660
    Abstract: A circuit includes a level shifter circuit, an output circuit, an enable circuit, a first and a second feedback circuit. The level shifter circuit is coupled to a first voltage supply, and is configured to generate at least a first and a second signal responsive to at least the first enable signal or the first input signal. The output circuit is coupled to at least the level shifter circuit and the first voltage supply, and configured to receive the first and the second signal. The enable circuit is configured to generate a second enable signal responsive to the first enable signal. The first feedback circuit is configured to receive the first enable signal, the second enable signal and the first feedback signal. The second feedback circuit is configured to receive the first enable signal, the second enable signal and the second feedback signal.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: June 14, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lun Ou, Ji-Yung Lin, Yung-Chen Chien, Ruei-Wun Sun, Wei-Hsiang Ma, Jerry Chang Jui Kao, Shang-Chih Hsieh, Lee-Chung Lu
  • Patent number: 11309893
    Abstract: A drive circuit having a set-side level shift circuit and a reset-side level shift circuit each configured to shift a level of a set or reset signal, and output the level-shifted set or reset signal from a set-side or reset-side output node, a mask-signal generating circuit configured to output a mask signal in response to a change in a voltage at the set-side or reset-side output node, and a control circuit configured to output a drive signal to a power device. The mask signal is for a time period shorter than a time period during which the level-shifted set or reset signal is outputted. The drive signal remains at a same level while the control circuit is receiving the mask signal, and switches to a first level or a second level, for turning off or on the power device, in response to the control circuit receiving the level-shifted reset or set signal after receiving the mask signal.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: April 19, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Masashi Akahane
  • Patent number: 11277132
    Abstract: Disclosed is an electronic device. The electronic device includes an input node, an output node, a power node that transfers a voltage of a third level to the output node when a voltage of the input node is a first level, and a capacitor that transfers a change in the voltage of the input node to the output node through a coupling such that a voltage of the output node is adjusted to a fourth level, when the voltage of the input node changes from the first level to a second level.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: March 15, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soomin Lee, Sungjun Kim, Hyoungjoong Kim
  • Patent number: 11223352
    Abstract: A method for driving a load includes driving a load to an initial voltage within a voltage window, the voltage window based on an input voltage and an offset voltage, and driving the load to approximately the input voltage.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: January 11, 2022
    Assignee: MONTEREY RESEARCH, LLC
    Inventors: David G. Wright, Jason Faris Muriby, Erhan Hancioglu
  • Patent number: 11201616
    Abstract: A voltage tolerant interface circuit includes an input terminal and one or more low-voltage transistors for generating an output from the voltage tolerant interface circuit based on a voltage received at the input terminal. The voltage tolerant interface circuit also includes a blocking transistor coupled between a control terminal of at least one low-voltage transistor and the input terminal. In some implementations, the blocking transistor is configured to protect the control terminal of the low-voltage transistor by blocking the voltage received at the input terminal when the voltage exceeds a voltage tolerance of the low-voltage transistor. In other implementations, the low-voltage transistor receives a supply voltage higher than the voltage tolerance of the low-voltage transistor.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: December 14, 2021
    Assignee: EMPOWER SEMICONDUCTOR, INC.
    Inventor: Parag Oak
  • Patent number: 11070208
    Abstract: A voltage level shifter for an SRAM device includes a level shifter input and provides a second voltage level. A voltage input terminal receives a first signal at a first voltage level and an inverter having an input and an output with the voltage input terminal is connected to the inverter input. A first voltage selector selectively applies an intermediate voltage to the gate of a PMOS transistor in a first complementary pair when the voltage of a complementary level shift output voltage rises to a logical 1 and a second voltage selector applies the intermediate voltage to the gate of a PMOS transistor in a second complementary pair when the voltage of the level shift output voltage node rises to a logical 1. The PMOS transistor current is thereby reduced resulting in lower energy dissipation and supporting a larger voltage separation between the first and second voltage levels.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: July 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Sanjeev Kumar Jain
  • Patent number: 11057247
    Abstract: A transmitting device includes an output node, at least one driver circuit and transition equalization circuitry. The driver circuit drives an output data signal including a data transition onto the output node. The output of the transition equalization circuitry is coupled to the output node. The transition equalization circuitry begins to drive the output node at the data transition and ends driving of the output node a pre-determined delay after beginning to drive the output node. The transition equalization circuitry drives the output node by injecting current onto the output node if the data transition is a positive transition, and sinking current from the output node if the data transition is a negative transition.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: July 6, 2021
    Assignee: Rambus Inc.
    Inventor: Yikui Jen Dong
  • Patent number: 11023632
    Abstract: A logic element includes a logic block, a supply voltage input, switchable power gates and a gate selector. The logic block implements a logic function on input data to obtain at least one output data signal. The switchable power gates transfer a supply voltage from the supply voltage input to the logic block in accordance with respective gate control signals. At least two of the power gates have different respective electrical properties. The gate selector switches on differing ones of the power gates in accordance with gate selection data.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: June 1, 2021
    Assignee: Bar-IIan University
    Inventors: Itamar Levi, Osnat Keren, Alexander Fish
  • Patent number: 10985737
    Abstract: A DC-coupled buffer is provided with two switch transistors controlled by a delayed version of an output signal for the DC-coupled buffer. A first one of the switch transistors functions to cut off a current discharged into ground that would otherwise flow while an input signal for the DC-coupled buffer is discharged. A remaining second one of the switch transistors functions to increase the operating speed of the DC-coupled buffer.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: April 20, 2021
    Assignee: QUALCOMM Incorporated
    Inventor: Tongyu Song
  • Patent number: 10904964
    Abstract: A driver circuit for controlling brightness of a set of light-emitting diodes. The driver circuit includes a switch unit for providing n first control signals, a lighting control unit for sending a second signal, a control circuit unit coupled to the switch unit and the lighting control unit and used to send a third control signal according to the n first control signal and the second control signal, an optical coupler for generating a fourth control signal according to the third control signal, and a power control unit for enabling the light-emitting diodes according to the fourth control signal. The n first control signals and the second control signal are both adjustable.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: January 26, 2021
    Assignee: LEEDARSON AMERICA INC.
    Inventor: Yongchuan Li
  • Patent number: 10848154
    Abstract: A level shifter includes a current mirror configured to receive an input signal in response to a first power voltage and generate an output signal by mirroring a current corresponding to a second power voltage based on a level of the input signal, a first adjusting circuit coupled to an output terminal of the current mirror and configured to adjust a voltage level of the output terminal of the current mirror in response to a bias voltage, and a second adjusting circuit coupled to a power voltage terminal which receives the second power voltage in parallel to the current mirror and configured to adjust the voltage level of the output terminal of the current mirror.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: November 24, 2020
    Assignee: SK hynix Inc.
    Inventor: Seung Ho Lee
  • Patent number: 10840857
    Abstract: A transimpedance amplifier (TIA) device. The device includes a photodiode coupled to a differential TIA with a first and second TIA, which is followed by a Level Shifting/Differential Amplifier (LS/DA). The photodiode is coupled between a first and a second input terminal of the first and second TIAs, respectively. The LS/DA can be coupled to a first and second output terminal of the first and second TIAs, respectively. The TIA device includes a semiconductor substrate comprising a plurality of CMOS cells, which can be configured using 28 nm process technology to the first and second TIAs. Each of the CMOS cells can include a deep n-type well region. The second TIA can be configured using a plurality CMOS cells such that the second input terminal is operable at any positive voltage level with respect to an applied voltage to a deep n-well for each of the plurality of second CMOS cells.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: November 17, 2020
    Assignee: INPHI CORPORATION
    Inventors: Rahul Shringarpure, Tom Peter Edward Broekaert, Gaurav Mahajan
  • Patent number: 10840910
    Abstract: Apparatuses and methods for level shifting in a semiconductor device are described. An example apparatus includes: a splitter circuit that operates on a first voltage potential to produce a first signal having a first polarity and a second signal having a second polarity that is substantially opposite to the first polarity; an one-shot pulse circuit that operates on the first voltage potential to produce a first one-shot pulse signal responsive to the first signal and a second one-shot pulse signal responsive to the second signal; and a logic circuit configured to operate on a second voltage potential to produce a third signal responsive to the first and second one-shot pulse signals, the second voltage potential being different from the first voltage potential.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Katsuhiro Kitagawa
  • Patent number: 10812078
    Abstract: A level shifter includes a current mirror configured to receive an input signal in response to a first power voltage and generate an output signal by mirroring a current corresponding to a second power voltage based on a level of the input signal, a first adjusting circuit coupled to an output terminal of the current mirror and configured to adjust a voltage level of the output terminal of the current mirror in response to a bias voltage, and a second adjusting circuit coupled to a power voltage terminal which receives the second power voltage in parallel to the current mirror and configured to adjust the voltage level of the output terminal of the current mirror.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: October 20, 2020
    Assignee: SK hynix Inc.
    Inventor: Seung Ho Lee
  • Patent number: 10778227
    Abstract: A level shifting circuit includes a shift circuit configured to output first and second voltage signals according to level signals, and an input circuit configured to carry out inversion and delay operations on input level signals to obtain first, second, third, and fourth level signals. Rising edge of the first level signal is earlier than falling edge of the second level signal by a first preset time. Falling edge of first level signal is later than rising edge of the second level signal by a second preset time; the third level signal is obtain by delaying the first level signal by a third preset time, and the fourth level signal is obtain by delaying the second level signal by a fourth preset time; the first preset time is longer than the third preset time, and the second preset time is longer than the fourth preset time.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: September 15, 2020
    Assignee: SMARTER MICROELECTRONICS (SHANGHAI) CO., LTD.
    Inventors: Jun Ma, Xin Wang, Jiangtao Yi
  • Patent number: 10727834
    Abstract: A direct-coupled level shifter to level shift a ground referenced input logic signal to an output logic signal that can have either a positive or negative reference. The level shifter includes two level shift drivers, each of which includes a positive level shift driver and a negative level shift driver. The positive level shift drivers operate when the reference of the latch is above ground and turn off when the reference is below ground. Similarly, the negative level shift drivers operate when the reference is below ground and turn off when the reference is above ground. The output logic signal is based on the output from the positive level shift driver receiving the input signal and the output from the negative level shift driver receiving an inverse of the input signal. The inverse of the output logic signal is based on the output from the positive level shift driver receiving an inverse of the input signal and the output from the negative level shift driver receiving the input signal.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: July 28, 2020
    Assignee: Efficient Power Conversion Corporation
    Inventors: Edward Lee, Ravi Ananth, Michael Chapman
  • Patent number: 10623217
    Abstract: A PAM signaling system utilizes multiple equalizers on each data lane of a serial data bus, each of the equalizers associated with a different signal eye of the serial data bus.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: April 14, 2020
    Assignee: NVIDIA Corp.
    Inventors: Walker Turner, William James Dally
  • Patent number: 10601614
    Abstract: Methods, systems, and apparatus to increase common-mode transient immunity in isolation devices is disclosed. An example apparatus includes a current mirror including an input terminal and an output terminal; a transistor including a gate terminal, a first current terminal, and a second current terminal, the gate terminal coupled to a reference voltage terminal, the first current terminal coupled to the input terminal of the current mirror, and the second current terminal coupled to an input node; a buffer including an input terminal and an output terminal, the input terminal of the buffer coupled to the output terminal of the current mirror; and a logic gate including an input terminal and an output terminal, the input terminal of the logic gate coupled to the output terminal of the buffer.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: March 24, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Zhidong Liu, James Michael Walden, Satish Kumar Vemuri
  • Patent number: 10547460
    Abstract: Exemplary features pertain to secure communications using Physical Unclonable Function (PUF) devices. Segments of a message to be encrypted are sequentially applied to a PUF device as a series of challenges to obtain a series of responses for generating a sequence of encryption keys, whereby a previous segment of the message is used to obtain a key for encrypting a subsequent segment of the message. The encrypted message is sent to a separate (receiving) device that employs a logical copy of the PUF device for decrypting the message. The logical copy of the PUF may be a lookup table or the like that maps all permissible challenges to corresponding responses for the PUF and may be generated in advance and stored in memory of the receiving device. The data to be encrypted may be further encoded to more fully exercise the PUF to enhance security. Decryption operations are also described.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: January 28, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Peiyuan Wang, Chando Park, Jimmy Jianan Kan, Seung Hyuk Kang
  • Patent number: 10530359
    Abstract: An output buffer circuit includes an output node, a P-type transistor, an N-type transistor, and a first variable resistor circuit provided in a signal path between a drain of one of the P-type transistor and the N-type transistor and the output node.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: January 7, 2020
    Assignee: Seiko Epson Corporation
    Inventor: Mitsuaki Sawada
  • Patent number: 10530617
    Abstract: A memory interface may include a transmitter that generates multi-level signals. The transmitter may employ channel equalization to improve the quality and robustness of the multi-level signals. The channel equalization may be controlled independently from the drive strength of the multi-level signals. For example, a first control signal may control the de-emphasis or pre-emphasis applied to a multi-level signal and a second control signal may control the drive strength of the multi-level signal. The first control signal may control a channel equalization driver circuit and the second control signal may control a driver circuit.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: January 7, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Feng Lin
  • Patent number: 10439661
    Abstract: A circuit includes a transmitter, a transmission line, and a receiver coupled to the transmitter through the transmission line, the transmission line used to transmit data at high-speed rates. At least one of the transmitter or receiver has associated therewith an unmatched termination, wherein either the transmitter or the receiver includes a finite impulse response (FIR) filter configured to cancel a reflected signal at a cancellation point situated at an input of the receiver, at an input of a driver, or at an output of the driver, the driver being coupled to an output of the transmitter, such that the reflected signal is substantially removed from the signal detected by the receiver.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: October 8, 2019
    Inventor: Payam Heydari
  • Patent number: 10418998
    Abstract: A level shifter circuit which includes a cross-coupled latch and a set-reset latch is introduced. The level shifter circuit includes a first input node, a second input node and a plurality of switches. The first input node and the second input node are configured to receive a first digital input signal and a second digital input signal, respectively. The plurality of switches are configured to be switched on or off according to at least one control signal to output a first output signal and a second output signal. The set-reset latch is coupled to the cross-coupled latch and includes a set input node, a reset input node and an output node. The set input node and the reset input node are configured to receive the first output signal and the second output signal of the cross-coupled latch, respectively. The output node outputs a level-shifted output signal according to the first output signal and the second output signal of the cross-coupled latch. A method adapted to a level shifter circuit is also introduced.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: September 17, 2019
    Assignee: Novatek Microelectronics Corp.
    Inventor: Yen-Cheng Cheng
  • Patent number: 10382962
    Abstract: A network authentication system with dynamic key generation that facilitates the establishment of both endpoint identity, as well as a secure communication channel using a dynamically-generated key between two end devices (potentially on separate local area networks). An interactive or non-interactive authentication protocol is used to establish the identity of the target end device, and dynamic key generation is used to establish a shared symmetric session key for creating an encrypted communication channel between the end devices.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: August 13, 2019
    Assignee: Analog Devices, Inc.
    Inventors: John J. Walsh, John Ross Wallrabenstein, Charles J. Timko
  • Patent number: 10367505
    Abstract: Disclosed herein is an low power output stage coupled between a supply node and a ground node, configured to drive an output, and controlled by first, second, and third control nodes. A current sinking circuit controlled by an input signal and configured to sink current from the first and second control nodes when the input signal transitions to a first logic level, thereby resulting in decoupling of the output stage from the ground node and sourcing of current to the output by the output stage. When the input signal transitions to a second logic level different than the first logic level, the current sinking circuit sinks current from a third control node, thereby resulting in decoupling of the output stage from the supply node and sinking of current from the output by the output stage.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: July 30, 2019
    Assignee: STMicroelectronics International N.V.
    Inventor: Prashant Singh
  • Patent number: 10361873
    Abstract: Various aspects of the disclosed technology relate to techniques of using control test points to enhance hardware security. The design-for-security circuitry reuses control test points, a part of design-for-test circuitry. The design-for-security circuitry comprises: identity verification circuitry; scrambler circuitry coupled; and test point circuitry. The test point circuitry comprises scan cells and logic gates The identify verification circuitry outputs an identity verification result to the scrambler circuitry to enable/disable control test points of the test point circuitry through the logic gates, and the scrambler circuitry outputs logic bits for loading the scan cells to activate/inactivate the control test points through the logic gates.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: July 23, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Nilanjan Mukherjee, Elham K. Moghaddam, Jerzy Tyszer, Justyna Zawada
  • Patent number: 10319362
    Abstract: The disclosure provides a level shifter. The level shifter includes a first logic block that receives an input signal and generates a primary pulsed input. A first transistor is coupled to the first logic block and a first node. A gate terminal of the first transistor receives the primary pulsed input. A latch is coupled to the first node and a second node. A second logic block receives the input signal and generates a secondary pulsed input. A second transistor is coupled between the second logic block and the second node. A gate terminal of the second transistor receives the secondary pulsed input.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: June 11, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ravikumar Pattipaka, Raja Sekhar Kanakamedala, Aravind Miriyala, Sandeep Kesrimal Oswal
  • Patent number: 10277212
    Abstract: A pulse generator includes a first inverter configured to inverse an input pulse and output a result, a second inverter configured to inverse the output of the first inverter and output a result, a clamp inverter configured to generate a clamping voltage by clamping the output of the second inverter and generate an output pulse through a source follower which operates according to the clamping voltage, and a temperature compensator configured to compensate for variations in the clamping voltage caused by temperature change.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: April 30, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Kinam Song, Wonhi Oh, Jinkyu Choi, Tae-sung Kwon, Seunghyun Hong
  • Patent number: 10277721
    Abstract: A puzzle-style modular electronic device is provided. The puzzle-style modular electronic device is activated based on detecting an interconnection of a plurality of block modules and determining whether the interconnection of the plurality of block modules matches an assembly orientation. Note that each of the plurality of block modules includes a processor, a memory, and at least one connection point through which the interconnection is established and that the interconnection of the plurality of block modules collectively forms the modular electronic device. Further, the puzzle-style modular electronic device authenticates a set of operations of the modular electronic device in response to the determining that the interconnection of the plurality of block modules matches the assembly orientation.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: April 30, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James P. Gilchrist, Michael E. Gildein, Rajaram B. Krishnamurthy, Moses J. Vaughan
  • Patent number: 10263619
    Abstract: An isolation cell clamps a signal passing from a first, powered-down power domain to a second, power-on power domain. To reduce leakage current, some of the circuits and devices are connected to a voltage supply of the first or “from” power domain, while other circuits and devices are connected to a voltage supply of the second or “to” power domain.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: April 16, 2019
    Assignee: NXP USA, INC.
    Inventors: Peidong Wang, Miaolin Tan, Zhe Ge
  • Patent number: 10218345
    Abstract: A high-side gate drive circuit includes pulse generating circuits that generate a first pulse synchronized with an input signal, and level shift circuits that shift a level of a reference voltage for the first pulse to a power supply voltage of a high-side switching element. The level shift circuits include MOSFETs to be driven by the first pulse. The high-side gate drive circuit includes a mask signal generating circuit that generates a mask signal that becomes a high level in a period in which source potential of the MOSFETs becomes a high level, and reshot circuits that input, when the first pulse is input into the level shift circuits during a mask period that is a period in which the mask signal is a high level, a second pulse into the level shift circuits after the mask period.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: February 26, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shinji Sakai, Hisashi Oda
  • Patent number: 10204676
    Abstract: A double data rate synchronous dynamic random access memory includes a control circuit and an output driving circuit. The control circuit provides a first voltage, a second voltage, a third voltage and a fourth voltage. The output driving circuit couples to the control circuit and includes a pull-up circuit, a pad and a pull-down circuit. When a voltage of the pad rises from the fourth voltage to the first voltage, a voltage between a drain and a source of a second driving transistor in the pull-down circuit is between the third voltage and the fourth voltage. When a voltage of the pad falls from the first voltage to the fourth voltage, a voltage between a drain and a source of a first driving transistor in the pull-up circuit is between the first voltage and the second voltage.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: February 12, 2019
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Li-Jun Gu, Ger-Chih Chou
  • Patent number: 10177753
    Abstract: An integrated circuit includes a control circuit, a first-in first-out circuit, and a serializer circuit. The control circuit generates parallel pulse-width modulation data in first parallel pulse-width modulation signals. The first-in first-out circuit stores the parallel pulse-width modulation data indicated by the first parallel pulse-width modulation signals. The first-in first-out circuit outputs the stored parallel pulse-width modulation data in second parallel pulse-width modulation signals. The serializer circuit converts the parallel pulse-width modulation data indicated by the second parallel pulse-width modulation signals to serial pulse-width modulation data in a serial pulse-width modulation signal.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: January 8, 2019
    Assignee: Altera Corporation
    Inventors: Lai Guan Tang, Kang Syn Ting
  • Patent number: 10175898
    Abstract: A semiconductor device includes a connector connectable to a host, a power supply circuit which includes an input portion that receives first power from the host via the connector, an output portion, and a switch that is connected to the input portion and the output portion and controls whether to supply the first power to the output portion, the power supply circuit generating second power and third power from the first power, a semiconductor memory which receives the second power from the output portion, and a controller which receives the third power from the output portion and controls the semiconductor memory. The power supply circuit turns off the switch and stops supply of power to the semiconductor memory and the controller when the second power exceeds a first value or when the third power exceeds a second value.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: January 8, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hajime Matsumoto, Toyokazu Eguchi, Hitoshi Yagisawa
  • Patent number: 10171082
    Abstract: A malfunction is prevented in a driving circuit. A driving circuit in which each of the set side level shift circuit and the reset side level shift circuit has an input transistor, a serial transistor unit which includes a first MOS transistor and a second MOS transistor which are connected in series, the first MOS transistors complementarily operate to each other, the driving circuit further has a set side buffer which compares a level of the set potential with a threshold value depending on the reference potential, and controls the reset side second MOS transistor, and a reset side buffer which compares a level of the reset potential with a threshold value depending on the reference potential, and controls the set side second MOS transistor.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: January 1, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Masashi Akahane
  • Patent number: 10110229
    Abstract: Systems and methods are related to selectively inverting circuit paths of an integrated circuit to reduce errors due to aging. An integrated circuit includes a first circuit path that receives an input signal and outputs a first output signal, a first selective inverter that receives the first output signal and outputs a first inverter output signal; and a second circuit path that receives the first selective inverter output signal and outputs a second output signal. In a first mode, the first selective inverter does not invert the first output signal and outputs the first output signal as the first selective inverter output signal. In a second mode, the first selective inverter inverts the first output signal and outputs an inverse of the first output signal as the first selective inverter output signal.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: October 23, 2018
    Assignee: Intel Corporation
    Inventor: Ker Yon Lau
  • Patent number: 10110231
    Abstract: A voltage translator translates an input signal to an output signal spanning a wide range of low voltages. An input buffer receives the input signal. A level shifter provides an output control signal. A gate control circuit provides gate control signals. An output buffer provides the output signal. The level shifter includes a pair of cross coupled P-type metal oxide silicon (PMOS) transistors each in series with an N-type metal oxide silicon (NMOS) transistor. A third NMOS transistor is coupled between an upper rail and a drain of one PMOS transistor; the gate of the third NMOS transistor is controlled by a first input control signal. A fourth NMOS transistor is coupled between the upper rail and a drain of the other PMOS transistor; the gate of the fourth NMOS transistor is controlled by a second input control signal.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: October 23, 2018
    Assignee: Texas Instruments Incorporated
    Inventor: Christopher Michael Graves
  • Patent number: 10084451
    Abstract: Techniques are disclosed for a level shifter configured to adjust current flow in response to measured current fluctuations due to common mode noise in the level shifter. For example, the level shifter includes a low-side control circuit configured to adjust a first current flowing into a first low-side terminal of an active high voltage level shifter device in response to a difference between the first low-side current and a second low-side current flowing into a second low-side terminal of an inactive high voltage level shifter device. The level shifter further includes a high-side receiver circuit configured to detect a difference between a first high-side current flowing into a first high-side terminal of the active high voltage level shifter device and a second high-side current flowing into a second high-side terminal of the inactive high voltage level shifter device.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: September 25, 2018
    Assignee: Infineon Technologies Austria AG
    Inventor: Martin Feldtkeller
  • Patent number: 10056149
    Abstract: Semiconductor memory devices and methods include a flash memory cell array fabricated in a well, with memory cells in the same column connected to each other in series and connected to a respective bit line. The memory devices also include a column decoder, a data register buffer unit, a row decoder, an erase control unit, and an input/output buffer unit. In one or more embodiments, the erase control unit applies voltages to the well to erase the memory cells in a manner that avoids breaking down p-n junctions formed by transistors fabricated in the well. In another embodiment, high voltage transistors are used to selectively isolate the bit lines from and couple the bit lines to a peripheral circuit in pairs so that each high voltage transistor is shared by two bit lines.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: August 21, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Shigekazu Yamada, Tomoharu Tanaka
  • Patent number: 9977886
    Abstract: An identity of an entity (120) is authenticated at an authentication device (110) using at least one authentication process. The result of the authentication is indicated. The authentication result identifies at least the identity of the entity (120) and the at least one authentication process used to authenticate the identity of the entity (120).
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: May 22, 2018
    Inventor: Paul Simmonds
  • Patent number: 9946858
    Abstract: An authentication system and device including physical unclonable function (PUF) and threshold cryptography comprising: a PUF device having a PUF input and a PUF output and constructed to generate, in response to the input of a challenge, an output value characteristic to the PUF and the challenge; and a processor having a processor input that is connected to the PUF output, and having a processor output connected to the PUF input, the processor configured to: control the issuance of challenges to the PUF input via the processor output, receive output from the PUF output, combine multiple received PUF output values each corresponding to a share of a private key or secret, and perform threshold cryptographic operations. The system and device may be configured so that shares are refreshable, and may be configured to perform staggered share refreshing.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: April 17, 2018
    Assignee: Analog Devices, Inc.
    Inventor: John Ross Wallrabenstein
  • Patent number: 9934845
    Abstract: A semiconductor device comprising a first supply voltage, a second supply voltage, different from the first supply voltage; and a switching circuit. The switching circuit comprises an input configured to receive an input signal corresponding to the first supply voltage and an output configured to output an output signal corresponding to the second supply voltage. The switching circuit is a combined latch with a built-in level shifter that provides latching functionality and level shifting functionality and a leakage path is cut-off when the switching circuit is providing latching functionality.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: April 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Campany Limited
    Inventors: Hao-I Yang, Cheng Hung Lee, Chi-Kai Hsieh, Fu-An Wu, Tsung-Hsien Huang
  • Patent number: 9831877
    Abstract: An integrated circuit (IC) includes a first circuit, a first well and a second circuit. The first circuit is disposed on a substrate and configured to shift a first bit signal between a first voltage logic level and a second logic voltage level. The first well is disposed in a cell on the substrate and biased to a first voltage. The first well is spaced apart from a first edge of the cell. The second well is disposed in the cell and biased to a second voltage. The second well is disposed to contact a second edge of the cell opposite to the first edge. The first circuit includes a plurality of transistors respectively disposed in the first and second wells.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: November 28, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dal-Hee Lee, Jae-Woo Seo
  • Patent number: 9780790
    Abstract: A r a level shifter circuit includes a first p-channel kick transistor connected directly across a first cross-coupled p-channel transistor, a second p-channel kick transistor connected directly across a second cross-coupled p-channel transistor, a first gate drive circuit coupled to the gate of the first p-channel kick transistor and configured to turn on first p-channel kick transistor to pull up the first output node in response to a rising edge of a signal at the input node, and a second gate drive circuit coupled to the gate of the second p-channel kick transistor and configured to turn on second p-channel kick transistor to pull up the second output node in response to a falling edge of a signal at the input node.
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: October 3, 2017
    Assignee: MICROSEMI SOC CORPORATION
    Inventor: Krishna Chaitanya Potluri
  • Patent number: 9755642
    Abstract: In view of the foregoing, an embodiment herein provides a low cost system. The system includes a bipolar array, a CMOS chip. The bipolar array includes one or more bipolar integrated circuits. The CMOS chip is programmed by a single level of metal. The bipolar array and the CMOS chip is mounted on a substrate using TAB polyamide. The TAB includes a polyamide film with one or more metal patterns chemically etched by programming three metal layers simultaneously to obtain one or more components. The one or more components are mounted in a package, and a small system can be realized. An external capacitor supplies an ac power source to the bipolar array. The bipolar array produces a rectified voltage and a lower voltage power for the enhanced gate array. An output of the enhanced gate array drives bipolar drivers of DC motor, stepper motor, BLDC motor, and LED assemblies.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: September 5, 2017
    Inventor: Shivaling Shrishail Mahant Shetti
  • Patent number: 9748958
    Abstract: A driver circuit and associated techniques include managing voltage driving an electronic device. An input signal having a first voltage level is received. Processes may perform level shifting of the first voltage level to a second voltage level. The second voltage level may be clamped, for instance, but a diode circuit. The second output voltage level may be programmable, as may be current and resistance levels of the driver circuit.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: August 29, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gregory J. Fredeman, Abraham Mathews, Donald W. Plass, Kenneth J. Reyer
  • Patent number: 9710006
    Abstract: An integrated circuit device can include at least a first body bias circuit configured to generate a first body bias voltage different from power supply voltages of the IC device; at least a first bias control circuit configured to set a first body bias node to a first power supply voltage, and subsequently enabling the first body bias node to be set to the first body bias voltage; and a plurality of first transistors having bodies connected to the first body bias node.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: July 18, 2017
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventor: Edward J. Boling
  • Patent number: RE47543
    Abstract: A host device is configured to read and write information from and into a card and to supply a supply voltage that belongs to a first voltage range or a second voltage range which is lower than the first voltage range, and issues a voltage identification command to the card. The voltage identification command includes a voltage range identification section, an error detection section, and a check pattern section. The voltage range identification section includes information indicating which one of the first voltage range and the second voltage range the supply voltage belongs. The error detection section has a pattern configured to enable the card which has received the voltage identification command to detect errors in the voltage identification command. The check pattern section has a preset pattern.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: July 30, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Akihisa Fujimoto
  • Patent number: RE48772
    Abstract: A host device is configured to read and write information from and into a card and to supply a supply voltage that belongs to a first voltage range or a second voltage range which is lower than the first voltage range, and issues a voltage identification command to the card. The voltage identification command includes a voltage range identification section, an error detection section, and a check pattern section. The voltage range identification section includes information indicating which one of the first voltage range and the second voltage range the supply voltage belongs. The error detection section has a pattern configured to enable the card which has received the voltage identification command to detect errors in the voltage identification command. The check pattern section has a preset pattern.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: October 12, 2021
    Assignee: KIOXIA CORPORATION
    Inventor: Akihisa Fujimoto