Abstract: A level shifter includes a low-level adjustment circuit, a comparator circuit, and a high-level adjustment circuit. The low-level adjustment circuit pulls down a level of one between a first input node and a second input node to a first low supply voltage. The comparator outputs a one having higher level between the level of the first input node and a second low supply voltage to a first output node, wherein the second low supply voltage is higher than the first low supply voltage. The high-level adjustment circuit selectively adjusts the level of the first output node according to the level of the first input node and the level of the second input node to generate an output signal.

Abstract: A gate driver includes: a signal generator configured to generate a gate signal, and output the gate signal to a first output terminal; and an inverted signal generator configured to generate an inverted gate signal based on the gate signal, and output the inverted gate signal to a second output terminal, wherein the inverted signal generator includes: a first transistor connected between a first node connected to the second output terminal and a first driving power supply terminal, and including a PMOS transistor; and a second transistor connected between the first node and a second driving power supply terminal, and including an NMOS transistor, and wherein a second node connected to the first output terminal is connected to a gate electrode of each of the first and second transistors.

Abstract: A shift register unit and a driving method thereof, a gate driving circuit, and a display device. The shift register unit includes: an input circuit, a first capacitor circuit, an output circuit, an output pull-down circuit, a coupling circuit, and an inverter circuit. The inverter circuit is coupled to an input control terminal, a first node, a second node, and a first level signal input terminal, and a second level signal input terminal; and used to control to connect or disconnect the second node and the first level signal input under the control of the input control terminal and the first level signal input terminal; also used to control to connect or disconnect the second node and the second level signal input terminal under the control of the first node and the second level signal input terminal.

Abstract: Systems and methods are provided for a level shifter. A level shifter includes a network of transistors configured to receive a signal at a first node in a first voltage domain and to generate a corresponding signal at a second node in a second voltage domain during a transition period of time. A self timing circuit is configured to receive an initiation signal based on the signal at the first node and to generate a voltage transition accelerator signal that is used to pull up the second node prior to the expiration of the transition period of time.

Abstract: A receiver circuit that includes a pair of pre-stage amplifier circuits and a post-stage amplifier circuit is introduced. A first pre-stage amplifier circuit includes a pair of first n-type transistors, and gate terminals of the first pair of the n-type transistors receive the input signal and the reference voltage signal, respectively. A second pre-stage amplifier circuit includes a pair of first p-type transistors, wherein gate terminals of the pair of the first p-type transistors receive the input signal and the reference voltage signal, respectively. The post-stage amplifier circuit outputs a post amplifying signal according to the first pre-stage amplifying signals and the second pre-stage amplifying signals. A memory device including the receiver circuit and an operation method thereof are also introduced.

Abstract: The present invention provides a shift register unit, a driving method, a driving circuit and a driving device. The shift register unit includes a first input circuit, a second input circuit, a control circuit and an output circuit; the first input circuit provides an input signal to a first node and provides a second voltage signal to a third node under control of a second clock signal; the second input circuit outputs a first voltage signal to the third node and controls a potential at a fourth node under control of a potential at the first node and an input control signal; the control circuit provides a first voltage signal to the first node under control of a potential at a fourth node. The present invention provides waveforms for operation of specific pixels.

Abstract: An integrated circuit includes a first set of devices, a set of metal layers and a header circuit. The first set of devices are configured to operate on a first supply voltage, and are located on a first layer of the integrated circuit. The set of metal layers are above the first layer, and includes a first metal layer and a second metal layer. The first metal layer extends in at least a first direction and a second direction. The header circuit is above the first set of devices. At least a portion of the header circuit is positioned between the first metal layer and the second metal layer. The header circuit is configured to provide the first supply voltage to the first set of devices, and is configured to be coupled to a first voltage supply having the first supply voltage.

Abstract: A method of generating multiple gating signals for a multi-gated input/output (I/O) system. The system includes an output level shifter and an output driver which are coupled in series between an output node of a core circuit and an external terminal of a corresponding system. The method includes: generating first and second gating signals having corresponding first and second waveforms, the first waveform transitioning from a non-enabling state to an enabling state before the second waveform transitions from the non-enabling state to the enabling state; receiving the first gating signal at the output level shifter; and receiving the second gating signal at the output driver.

Abstract: A device comprises, a first power source providing a first voltage, a second power source providing a second voltage less than the first voltage, a first bias voltage source providing a first bias voltage between the first voltage and the second voltage, a second bias voltage source providing a second bias voltage between the first voltage and the second voltage, the second bias voltage greater than or equal to the first bias voltage. The device also includes an output, a pull up network coupled in series between the first power source and the output pad including: a first gate coupled to the bias voltage source; and a second gate coupled to a signal that varies between first bias voltage and first power source. The device includes and a pull down network coupled between the output pad and second power source and including: a third gate coupled to the second bias voltage source; and a fourth gate coupled to a signal that varies between the second power source and the second bias voltage source.

Abstract: Networks, methods, and circuitries are provided that propagate an actuator signal to a plurality of devices in a respective plurality of voltage domains. The network includes a first signal path disposed between an actuator signal source and a first device. The first signal path includes a first point at which the actuator signal is in a first voltage domain. A second signal path is disposed between the actuator signal source and a second device. The second signal path includes a second point at which the actuator signal is in a second voltage domain. The first voltage domain is different from, and has a fixed relationship to, the second voltage domain. A multi-domain coupling circuitry is connected to the first point and the second point. The multi-domain coupling circuitry is configured to maintain the fixed relationship between the actuator signal at the first point and the second point.

Abstract: A level shifting circuit, the circuit comprising a VL input; an I/O VL; a VCC input; an I/O VCC; a first pull-up resistor disposed between the VL input and I/O VL; a second pull-up resistor disposed between the VCC input and I/O VCC; a first pull-up assist circuit comprising a first pull-up assist p-channel MOSFET having a source/body, drain, and gate, the source/body and drain being connected to VL and I/O VL; a second pull-up assist circuit comprising a second pull-up assist p-channel MOSFET having a source/body, drain, and gate, the source/body and drain being connected to VCC and I/O VCC, respectively; a pass-gate n-channel MOSFET in operative communication with I/O VL, I/O VCC, and VL, the pass-gate being configured to reduce the voltage level of a signal driven from I/O VCC to the voltage level of I/O VL; and a one-shot circuit configured to detect a I/O VL or I/O VCC transition from a low state to a high state, to produce a pulse in response thereto, and to communicate that pulse to the gates of the fi

Abstract: A level converter, a data processing method, and a display device are provided. The level converter is used for providing a direct current signal for image display and includes a storage circuit, a processing circuit, and a level conversion component. The level conversion component includes a plurality of level conversion circuits; the storage circuit is configured to store image data of an image to be displayed; the processing circuit is in signal connection with the storage circuit, and is configured to obtain control data corresponding to the image data of the image to be displayed according to the image data; and the level conversion component is in signal connection with the processing circuit, and is configured to control whether each of the plurality of level conversion circuits performs level conversion according to the control data, so as to generate the direct current signal.

Abstract: The present disclosure relates to a circuit for level shifting of a data voltage from a transmitter. The circuit comprises an inverter logic. The inverter logic comprises a first transistor and a second transistor. The first transistor is connected to a source voltage and the second transistor is connected to ground. A capacitor is connected to an input of the first transistor and configured to drive the first transistor. The capacitor is configured to charge to a charged voltage equivalent to a difference between the source voltage and the data voltage. The second transistor is configured to be driven by the data voltage, thereby level shifting a level of the data voltage to a level of the source voltage.

Abstract: An output driving circuit may include a pull-up-pull-down driver connected to a pad, a level shifter operating based on a first power voltage and a second power voltage that is greater than the first power voltage, level shifting a data signal to generate a first control signal, and applying the first control signal to the pull-up-pull-down driver, and a driver control logic operating based on the first power voltage, generating a second control signal based on the data signal, and applying the second control signal to the pull-up-pull-down driver.

Abstract: Systems, apparatuses, and methods for implementing dynamic control of a multi-region fabric are disclosed. A system includes at least one or more processing units, one or more memory devices, and a communication fabric coupled to the processing unit(s) and memory device(s). The system partitions the fabric into multiple regions based on different traffic types and/or periodicities of the clients connected to the regions. For example, the system partitions the fabric into a stutter region for predictable, periodic clients and a non-stutter region for unpredictable, non-periodic clients. The system power-gates the entirety of the fabric in response to detecting a low activity condition. After power-gating the entirety of the fabric, the system periodically wakes up one or more stutter regions while keeping the other non-stutter regions in power-gated mode. Each stutter region monitors stutter client(s) for activity and processes any requests before going back into power-gated mode.

Abstract: A memory device is provided. The memory device comprises at least one word line driver comprising a first and a second switching device, wherein the word line driver is configured to activate a word line electrically coupled to one or more memory cells included in a memory bank. The memory device additionally comprises a memory bank controller operatively coupled to the at least one word line driver. The memory bank controller is configured to provide a word line power supply (PH) signal, a word line ON control (GR) signal, and a word line OFF control (PHF) signal to the at least one word line driver, and to adjust a timing of the PH, the GR, and the PHF signals to reduce or to eliminate a non-conducting stress (NCS) condition, a time dependent temperature instability (TDDB) condition, or a combination thereof, of the first switching device, of the second switching device, or of a combination thereof.

Abstract: The present disclosure discloses a shift register, a driving method thereof, a gate drive circuit, an array substrate and a display device. With a signal control circuit, a branch control circuit, a cascade signal output circuit and at least two scan signal output circuits, each shift register can output at least two scan signals to correspond to different gate lines in a display panel. This can reduce the number of shift registers in a gate drive circuit and the space occupied by the gate drive circuit and can achieve an ultra-narrow frame design, as compared with an existing shift register that can only output one scan signal. Moreover, as signals of different output control node do not influence each other, the output stability can also be improved.

Abstract: Disclosed is a control circuit for protecting MOSFETs in I/O buffers or other devices from overvoltage damage, especially during power ramp up. The control circuit can perform additional functions. In one embodiment an integrated circuit (IC) includes input/output (I/O) buffers coupled to an output supply voltage terminal that is configured to receive an output supply voltage Vddio. Each of the I/O buffers has a bias voltage generator that is configured to generate a first bias voltage with a magnitude that depends on a control signal; an output stage that receives the first bias voltage, wherein the output stage is configured to drive an I/O pad based upon a data signal received at the I/O buffer. The IC also includes an I/O buffer controller coupled to the I/O buffers and configured to generate the control signal based upon a magnitude of the output supply voltage Vddio.

Abstract: A light emitting device and an element substrate which are capable of suppressing variations in luminance intensity of a light emitting element among pixels due to characteristic variations of a driving transistor without suppressing off-current of a switching transistor low and increasing storage capacity of a capacitor. A gate potential of a driving transistor is connected to a first scan line or a second scan line, and the driving transistor operates in a saturation region. A current controlling transistor which operates in a linear region is connected in series to the driving transistor. A video signal which transmits a light emission or non-emission of a pixel is input to the gate of the current controlling transistor through a switching transistor.

Abstract: A circuit includes a first inverter and a second inverter. The first inverter is coupled to an input terminal. The input terminal receives an input signal varying in a first voltage domain. The second inverter is coupled between the first inverter and an output terminal. The second inverter generates an output signal varying in a second voltage domain. The first inverter includes a first PMOS transistor and a first NMOS transistor. The first PMOS transistor is biased by a first input tracking signal generated from the input signal. The first input tracking signal varies in a third voltage domain. The first NMOS transistor is biased by a second input tracking signal generated from the input signal. The second input tracking signal varies in the second voltage domain.

Abstract: In a level shifter circuit that transmits a set signal and a reset signal input to input terminals of a high-side latch circuit, the source sides of high voltage transistors are connected to current negative feedback resistors, and transistors are connected in parallel to the current negative feedback resistors. Further included is a high-side voltage detection circuit that detects whether the voltage of a high-side power supply terminal is a high voltage. When a high voltage is detected, the transistors are turned OFF to make the drain currents that flow smaller, thereby making it possible to improve the trade-off between heat generation and propagation delay characteristics in the high voltage transistors.

Abstract: A single-ended data transmission system transmits a signal having a signal voltage that is referenced to a power supply voltage and that swings above and below the power supply voltage. The power supply voltage is coupled to a power supply rail that also serves as a signal return path. The signal voltage is derived from two signal supply voltages generated by a pair of charge pumps that draw substantially same amount of current from a power supply.

Abstract: A method of manufacturing a semiconductor device includes configuring a layout pattern; and forming conductive lines corresponding to the layout pattern on a substrate, wherein configuring the layout pattern includes: arranging pre-conductive patterns and post-conductive patterns for a first logic cell, a second logic cell, and a third logic cell; rearranging the pre-conductive patterns and the post-conductive patterns so that two conductive patterns that are adjacent to a boundary between two adjacent logic cells from among the first logic cell, the second logic cell, and the third logic cell are formed by different photolithography processes; and arranging conductive patterns for a dummy cell arranged between the second logic cell and the third logic cell.

Abstract: An improved level shifter is disclosed. The level shifter is able to achieve a switching time below 1 ns using a relatively low voltage for VDDL, such as 0.75 V. The improved level shifter comprises a coupling stage and a level-switching stage. A related method of level shifting is also disclosed.

Abstract: The present disclosure describes embodiments of a write assist circuit. The write assist circuit can include a boost circuit configured to output a first negative voltage at a first output terminal, and an adjustment circuit configured to couple the first negative voltage to a second negative voltage higher than the first negative voltage. The adjustment circuit can include a transistor, and a second output terminal electrically connected to the first output terminal. The transistor can include a first source/drain terminal, a second source/drain terminal, and a gate terminal. The first source/drain terminal can be electrically coupled to the second output terminal. The second source/drain terminal can be electrically connected to a voltage source. The gate terminal can be electrically connected to a ground voltage supply.

Abstract: To improve the efficiency of pressure detection, a driver applies a positive-phase signal to a capacitance element from an opposite side to a coupling point in a control device. Another driver applies a reverse-phase signal to another capacitance element from an opposite side to the coupling point. A control unit detects pressures applied to the capacitance elements based on a potential fluctuation at the coupling point.

Abstract: Various implementations described herein are directed to an integrated circuit having first devices arranged to operate as a latch. The first devices may include inner devices and outer devices. The integrated circuit may include second devices coupled to the first devices and arranged to operate as a level shifter. The second devices may include upper devices and lower devices. The lower devices may be cross-coupled to gates of the inner devices and the upper devices. The integrated circuit may include input signals applied to gates of the outer devices and the lower devices to thereby generate output signals from the outputs of the lower devices that are applied to the gates of the inner devices and the upper devices to activate latching of the output signals.

Abstract: Provided are a scan driving circuit and driving method thereof, array substrate and a display device. The scan driving circuit includes output ends at m stages, input circuits at m stages, and q shift register circuits. A first end of the input circuit at the i-th stage is connected to the output end at the (i?1)-th stage, and i is any integer greater than 1 and less than m+1. Any shift register circuits is respectively connected to k output ends, and second ends of k input circuits, and the k input circuits have a same combination of stage numbers as k output ends, all stage numbers in same combination of stage numbers have the same parity, and k is greater than 1 and less than m. The shift register circuit is configured to output a scanning signal to one output ends, and outputting the scanning signal to which output ends is indicated by an external control signal.

Abstract: Provided is an active matrix substrate (100) that includes multiple pixel TFTs (10), multiple gate wiring lines (GL) along which a scanning signal is supplied to the multiple pixel TFTs, multiple source wiring lines (SL) along which a display signal is supplied to the multiple pixel TFTs, a gate driver (20) that drives multiple gate wiring lines, and a source driver (30) that drives multiple source wiring lines. At least one of the gate driver and the source driver includes a current mirror circuit (70). The current mirror circuit is configured with two oxide semiconductor TFTs (71c and 72c) each of which includes an oxide semiconductor layer.

Abstract: The present application provides a level shifter comprising a first P-type transistor; a second P-type transistor; a third P-type transistor, coupled to the second P-type transistor; a fourth P-type transistor, coupled to the first P-type transistor; a first N-type transistor, coupled to the third P-type transistor; a second N-type transistor, coupled to the fourth P-type transistor; a third N-type transistor, coupled to the first N-type transistor; a fourth N-type transistor, coupled to the second N-type transistor; and an inverter, coupled between the third N-type transistor and the fourth N-type transistor, wherein an input terminal of the inverter receives an input signal of the level shifter.

Abstract: There is a need to provide a semiconductor device, a semiconductor system, and a semiconductor device manufacturing method capable of accurately monitoring a minimum operating voltage for a monitoring-targeted circuit. A monitor portion of a semiconductor system according to one embodiment includes a voltage monitor and a delay monitor. The voltage monitor is driven by power-supply voltage SVCC different from power-supply voltage VDD supplied to an internal circuit as a monitoring-targeted circuit and monitors power-supply voltage VDD. The delay monitor is driven by power-supply voltage VDD and monitors signal propagation time for a critical path in the internal circuit. The delay monitor is configured so that a largest on-resistance of on-resistances for a plurality of transistors configuring the delay monitor is smaller than a largest on-resistance of on-resistances for a plurality of transistors configuring the internal circuit.

Abstract: The present disclosure relates to a pixel driving circuit, a display device and a driving method. The pixel driving circuit is configured to control on and off of a pixel unit, and includes: a first control sub-circuit, a first output sub-circuit, a second control sub-circuit, a second output sub-circuit, a third control sub-circuit, and a fourth control sub-circuit. Specifically, the fourth control sub-circuit is configured, if turned on, to cause a voltage drop of the first level signal input at the first level signal input terminal and to output the first level signal with the voltage drop to the third control node, such that a voltage at the third control node is less than or equal to a voltage at the first control node, thereby maintaining the third control sub-circuit off.

Abstract: To suppress degradation of a transistor. A method for driving a liquid crystal display device has a first period and a second period. In the first period, a first transistor and a second transistor are alternately turned on and off repeatedly, and a third transistor and a fourth transistor are turned off. In the second period, the first transistor and the second transistor are turned off, and the third transistor and the fourth transistor are alternately turned on and off repeatedly. Accordingly, the time during which the transistor is on can be reduced, so that degradation of characteristics of the transistor can be suppressed.

Abstract: Systems, apparatuses, and methods for implementing dynamic control of a multi-region fabric are disclosed. A system includes at least one or more processing units, one or more memory devices, and a communication fabric coupled to the processing unit(s) and memory device(s). The system partitions the fabric into multiple regions based on different traffic types and/or periodicities of the clients connected to the regions. For example, the system partitions the fabric into a stutter region for predictable, periodic clients and a non-stutter region for unpredictable, non-periodic clients. The system power-gates the entirety of the fabric in response to detecting a low activity condition. After power-gating the entirety of the fabric, the system periodically wakes up one or more stutter regions while keeping the other non-stutter regions in power-gated mode. Each stutter region monitors stutter client(s) for activity and processes any requests before going back into power-gated mode.

Abstract: A signal outputting circuit including: an input line to which an input signal is inputted; a first current generating circuit connected to the input line, the first current generating circuit generating a first current having a magnitude corresponding to a level of a supplied power supply voltage; a second current generating circuit connected to the input line, the second current generating circuit generating a second current that turns ON and OFF in accordance with switching of a level of an output signal; a resistor element provided at the input line; and an outputting circuit that switches a logic level of the output signal in accordance with a level of voltage generated at the input line.

Abstract: A voltage doubler circuit supports operation in both a positive voltage boosting mode to positively boost voltage from a first node to a second node and a negative voltage boosting mode to negatively boost voltage from the second node to the first node. The voltage doubler circuit is formed by transistors of a same conductivity type that share a common bulk that is not tied to a source of any of the voltage doubler circuit transistors. A bias generator circuit is coupled to receive a first voltage from the first node and second voltage from the second node. The bias generator circuit operates to apply a lower one of the first and second voltages to the common bulk.

Abstract: An improved level shifter for use in integrated circuits is disclosed. The level shifter is able to achieve a switching time below 1 ns while still using the core power supply voltages, VDDL and VDDH, used in the prior art. The improved level shifter comprises a coupling stage and a level-switching stage.

Abstract: Disclosed is an inverter capable of withstanding a high voltage. The inverter includes a control voltage generating circuit, a high voltage transmission circuit, and a low voltage transmission circuit. The control voltage generating circuit generates a first group of control voltages and a second group of control voltages according to an input voltage, in which one group includes decrement voltages and the other group includes identical voltages. The high/low voltage transmission circuit is coupled between a high/low voltage terminal and an output terminal, wherein when the input voltage is low/high, the high/low voltage transmission circuit is turned on according to the first/second group of control voltages so that an output voltage of the output terminal is equal to a high/low voltage of the high/low voltage terminal.

Abstract: A semiconductor integrated circuit includes: a power supply terminal that receives a power supply voltage; an external terminal; an output PMOS transistor connected between the power supply terminal and the external terminal; an auxiliary PMOS transistor connected between a gate of the output PMOS transistor and the external terminal; and a bias voltage generating circuit connected to a gate of the auxiliary PMOS transistor. The bias voltage generating circuit supplies a voltage lower than the power supply voltage to the gate of the auxiliary PMOS transistor, if it is necessary to maintain an OFF state of the output PMOS transistor by supplying an external voltage received at the external terminal to the gate of the output PMOS transistor.

Abstract: An output circuit may be provided with: input and output terminals; a ground terminal shared by both an input side and an output side; a first switching element of n-channel type having first positive and negative electrodes, and a first gate; a second switching element of the n-channel type having second positive and negative electrodes, and a second gate; a diode; and a resistive element; in which the first positive electrode is connected with a power source, the first negative electrode is connected with the output terminal, anode of the diode is connected with the first negative electrode, cathode of the diode is connected with the first gate, the resistive element is connected between the source and the first gate, the second positive electrode is connected with the first gate, the second negative electrode is connected with the ground terminal, and the second gate is connected with the input terminal.

Abstract: An apparatus is provided which comprises: a dual stack voltage driver, wherein the dual stack voltage driver comprises a first stack of transistors, and a second stack of transistors; and one or more feedback transistors each coupled to a transistor of the second stack of transistors.

Abstract: A logic level shifter interface including a string of logic components communicating between a first power domain and a second power domain; a first string of resistive components connecting a first power rail of the first power domain to a first power rail of the second power domain and having a plurality of intermediate first power rails at nodes between adjacent resistive components of the first string of resistive components; and a second string of resistive components connecting a second power rail of the first power domain to a second power rail of the second power domain and having a plurality of intermediate second power rails at nodes between adjacent resistive components of the second string of resistive components, where at least one logic component is powered by an intermediate first power rail of the first string of resistive components and an intermediate second power rail of the second string of resistive components.

Abstract: A circuit includes a first power node configured to carry a first voltage having a first voltage level, an output node, a node coupled between the first power node and the output node, and a contending transistor coupled between the node and a second power node configured to carry a second voltage having a second voltage level. The circuit generates a signal at the output node that ranges between the first voltage level and a third voltage level, the contending transistor couples the node with the second power node responsive to the signal, a difference between the first voltage level and the second voltage level has a first magnitude, a difference between the first voltage level and the third voltage level has a second magnitude, and the second magnitude is a multiple of the first magnitude having a value greater than one.

Abstract: Disclosed are a shift register element, a method for driving the same, and a display panel. The method includes: an output module including a first node and a third node, wherein the output module is configured to provide an output terminal with a signal of a first signal terminal or a second signal terminal according to voltage applied to the first node and the third node; a first driver configured to control the voltage of the first node, and voltage of a second node according to signals of the first input terminal and the second input terminal; a second driver configured to control voltage of the third node according to the voltage of the first node and the second node; and a feedback regulation module configured to control voltage of the first node according to the signal of the output terminal, and signals of a third input terminal and a fourth input terminal.

Abstract: Provided is a level shifter which can retain an operation margin and enhance an exceeded-breakdown-voltage preventing effect. The level shifter in an embodiment includes an exceeded-breakdown-voltage prevention circuit between a pair of first-conductivity-type cross-coupled transistors and a pair of second-conductivity-type input transistors. The exceeded-breakdown-voltage prevention circuit includes first-conductivity-type first transistors and second-conductivity-type second transistors which are coupled in series to each other, and first-conductivity-type third transistors coupled in series to the first and second transistors on a higher-potential side.

Abstract: A gate voltage generation circuit generates a gate voltage including a first voltage, a second voltage and a third voltage and supplies the gate voltage to a pixel transistor of a display device. The first voltage is a voltage for opening the pixel transistor. The second voltage is lower than the first voltage and is a voltage for closing the pixel transistor. The third voltage is an intermediate voltage between the first voltage and the second voltage. The voltage rises by way of the intermediate voltage at the time of rising from the second voltage to the first voltage.

Abstract: A level shift circuit which comprises a voltage applying part configured to apply predetermined voltage to a first node intermittently. An input part receives an input signal and applies reference voltage to a second node when a signal level of the input signal is equal to a first voltage level. A switching part connects the second node and the first node with each other during the voltage applying part does not apply the predetermined voltage to the first node. The switching part cuts off the connection between the second node and the first node during the voltage applying part applies the predetermined voltage to the first node. An inverter provides a phase-inverted signal of the signal given to the first node as an output signal.

Abstract: An integrated circuit device includes dispatcher circuitry that receives signals from a first number of sources, multiplexes the signals into a single mixed signal in a predetermined order, and transmits the mixed signal to a destination via a mixed signal interface having an arbitrary length and operating at an interface clock frequency equal to a product of a device clock frequency and the first number. A second number of samplers is disposed in series along the mixed signal interface, outputting a sampled mixed signal synchronized to the interface clock. A chain of tracking elements in series, corresponding in number to the second number, outputs a tracking indication separate from the sampled mixed signal. Capture circuitry demultiplexes the sampled mixed signal into a plurality of demultiplexed signals, according to a starting point based on the tracking indication, onto a plurality of signal buses corresponding in number to the first number.

Abstract: Provided is a semiconductor device which can operate stably even in the case where a transistor thereof is a depletion transistor. The semiconductor device includes a first transistor for supplying a first potential to a first wiring, a second transistor for supplying a second potential to the first wiring, a third transistor for supplying a third potential at which the first transistor is turned on to a gate of the first transistor and stopping supplying the third potential, a fourth transistor for supplying the second potential to the gate of the first transistor, and a first circuit for generating a second signal obtained by offsetting a first signal. The second signal is input to a gate of the fourth transistor. The potential of a low level of the second signal is lower than the second potential.

Abstract: In a described example, an apparatus includes a driver circuit coupled to an output pad, the driver having a p-channel FET coupled between a positive peripheral voltage and the pad, and having a first gate terminal coupled to a first gate control signal, and an n-channel FET coupled between the pad and a ground terminal and having a second gate terminal coupled to a second gate control signal. A predriver circuit is coupled to receive a data signal for output to the pad and further coupled to output the first gate control signal; and the predriver circuit is coupled to output a supply voltage to the first gate control signal in a first mode, and to output a bias voltage less than the supply voltage to the first gate control signal in a second mode; and a bias circuit is coupled for outputting the bias voltage.