Cmos Patents (Class 326/81)
  • Patent number: 11146268
    Abstract: In a level shifter circuit that transmits a set signal and a reset signal input to input terminals of a high-side latch circuit, the source sides of high voltage transistors are connected to current negative feedback resistors, and transistors are connected in parallel to the current negative feedback resistors. Further included is a high-side voltage detection circuit that detects whether the voltage of a high-side power supply terminal is a high voltage. When a high voltage is detected, the transistors are turned OFF to make the drain currents that flow smaller, thereby making it possible to improve the trade-off between heat generation and propagation delay characteristics in the high voltage transistors.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: October 12, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Masaharu Yamaji
  • Patent number: 11075671
    Abstract: A single-ended data transmission system transmits a signal having a signal voltage that is referenced to a power supply voltage and that swings above and below the power supply voltage. The power supply voltage is coupled to a power supply rail that also serves as a signal return path. The signal voltage is derived from two signal supply voltages generated by a pair of charge pumps that draw substantially same amount of current from a power supply.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: July 27, 2021
    Assignee: Rambus Inc.
    Inventors: John W. Poulton, Frederick A. Ware, Carl W. Werner
  • Patent number: 11043428
    Abstract: A method of manufacturing a semiconductor device includes configuring a layout pattern; and forming conductive lines corresponding to the layout pattern on a substrate, wherein configuring the layout pattern includes: arranging pre-conductive patterns and post-conductive patterns for a first logic cell, a second logic cell, and a third logic cell; rearranging the pre-conductive patterns and the post-conductive patterns so that two conductive patterns that are adjacent to a boundary between two adjacent logic cells from among the first logic cell, the second logic cell, and the third logic cell are formed by different photolithography processes; and arranging conductive patterns for a dummy cell arranged between the second logic cell and the third logic cell.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: June 22, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ha-Young Kim, Jin Tae Kim, Jae-Woo Seo, Dong-yeon Heo
  • Patent number: 11038495
    Abstract: An improved level shifter is disclosed. The level shifter is able to achieve a switching time below 1 ns using a relatively low voltage for VDDL, such as 0.75 V. The improved level shifter comprises a coupling stage and a level-switching stage. A related method of level shifting is also disclosed.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: June 15, 2021
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Ryan Mei, Xiaozhou Qian, Hieu Van Tran, Claire Zhu
  • Patent number: 11024370
    Abstract: The present disclosure describes embodiments of a write assist circuit. The write assist circuit can include a boost circuit configured to output a first negative voltage at a first output terminal, and an adjustment circuit configured to couple the first negative voltage to a second negative voltage higher than the first negative voltage. The adjustment circuit can include a transistor, and a second output terminal electrically connected to the first output terminal. The transistor can include a first source/drain terminal, a second source/drain terminal, and a gate terminal. The first source/drain terminal can be electrically coupled to the second output terminal. The second source/drain terminal can be electrically connected to a voltage source. The gate terminal can be electrically connected to a ground voltage supply.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: June 1, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kian-Long Lim, Chia-Hao Pao
  • Patent number: 11009409
    Abstract: To improve the efficiency of pressure detection, a driver applies a positive-phase signal to a capacitance element from an opposite side to a coupling point in a control device. Another driver applies a reverse-phase signal to another capacitance element from an opposite side to the coupling point. A control unit detects pressures applied to the capacitance elements based on a potential fluctuation at the coupling point.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: May 18, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masato Hirai, Takeshi Yoshizawa, Takeshi Kuwano
  • Patent number: 11005461
    Abstract: Various implementations described herein are directed to an integrated circuit having first devices arranged to operate as a latch. The first devices may include inner devices and outer devices. The integrated circuit may include second devices coupled to the first devices and arranged to operate as a level shifter. The second devices may include upper devices and lower devices. The lower devices may be cross-coupled to gates of the inner devices and the upper devices. The integrated circuit may include input signals applied to gates of the outer devices and the lower devices to thereby generate output signals from the outputs of the lower devices that are applied to the gates of the inner devices and the upper devices to activate latching of the output signals.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: May 11, 2021
    Assignee: Arm Limited
    Inventors: Andy Wangkun Chen, Sai Sriharsha Manapragada, Yicong Li, Yew Keong Chong, Bikas Maiti, Sanjay Mangal, Hsin-Yu Chen
  • Patent number: 10950153
    Abstract: Provided are a scan driving circuit and driving method thereof, array substrate and a display device. The scan driving circuit includes output ends at m stages, input circuits at m stages, and q shift register circuits. A first end of the input circuit at the i-th stage is connected to the output end at the (i?1)-th stage, and i is any integer greater than 1 and less than m+1. Any shift register circuits is respectively connected to k output ends, and second ends of k input circuits, and the k input circuits have a same combination of stage numbers as k output ends, all stage numbers in same combination of stage numbers have the same parity, and k is greater than 1 and less than m. The shift register circuit is configured to output a scanning signal to one output ends, and outputting the scanning signal to which output ends is indicated by an external control signal.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: March 16, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD
    Inventors: Jian Zhao, Mo Chen, Jilei Gao, Yang Zhang
  • Patent number: 10942409
    Abstract: Provided is an active matrix substrate (100) that includes multiple pixel TFTs (10), multiple gate wiring lines (GL) along which a scanning signal is supplied to the multiple pixel TFTs, multiple source wiring lines (SL) along which a display signal is supplied to the multiple pixel TFTs, a gate driver (20) that drives multiple gate wiring lines, and a source driver (30) that drives multiple source wiring lines. At least one of the gate driver and the source driver includes a current mirror circuit (70). The current mirror circuit is configured with two oxide semiconductor TFTs (71c and 72c) each of which includes an oxide semiconductor layer.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: March 9, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Kaoru Yamamoto
  • Patent number: 10924115
    Abstract: The present application provides a level shifter comprising a first P-type transistor; a second P-type transistor; a third P-type transistor, coupled to the second P-type transistor; a fourth P-type transistor, coupled to the first P-type transistor; a first N-type transistor, coupled to the third P-type transistor; a second N-type transistor, coupled to the fourth P-type transistor; a third N-type transistor, coupled to the first N-type transistor; a fourth N-type transistor, coupled to the second N-type transistor; and an inverter, coupled between the third N-type transistor and the fourth N-type transistor, wherein an input terminal of the inverter receives an input signal of the level shifter.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: February 16, 2021
    Assignee: Shenzhen Goodix Technology Co., Ltd.
    Inventor: Muli Huang
  • Patent number: 10911042
    Abstract: There is a need to provide a semiconductor device, a semiconductor system, and a semiconductor device manufacturing method capable of accurately monitoring a minimum operating voltage for a monitoring-targeted circuit. A monitor portion of a semiconductor system according to one embodiment includes a voltage monitor and a delay monitor. The voltage monitor is driven by power-supply voltage SVCC different from power-supply voltage VDD supplied to an internal circuit as a monitoring-targeted circuit and monitors power-supply voltage VDD. The delay monitor is driven by power-supply voltage VDD and monitors signal propagation time for a critical path in the internal circuit. The delay monitor is configured so that a largest on-resistance of on-resistances for a plurality of transistors configuring the delay monitor is smaller than a largest on-resistance of on-resistances for a plurality of transistors configuring the internal circuit.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: February 2, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuki Fukuoka, Toshifumi Uemura, Yuko Kitaji
  • Patent number: 10885846
    Abstract: The present disclosure relates to a pixel driving circuit, a display device and a driving method. The pixel driving circuit is configured to control on and off of a pixel unit, and includes: a first control sub-circuit, a first output sub-circuit, a second control sub-circuit, a second output sub-circuit, a third control sub-circuit, and a fourth control sub-circuit. Specifically, the fourth control sub-circuit is configured, if turned on, to cause a voltage drop of the first level signal input at the first level signal input terminal and to output the first level signal with the voltage drop to the third control node, such that a voltage at the third control node is less than or equal to a voltage at the first control node, thereby maintaining the third control sub-circuit off.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: January 5, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Minghua Xuan, Shengji Yang, Pengcheng Lu, Jie Fu, Lei Wang, Li Xiao
  • Patent number: 10878736
    Abstract: To suppress degradation of a transistor. A method for driving a liquid crystal display device has a first period and a second period. In the first period, a first transistor and a second transistor are alternately turned on and off repeatedly, and a third transistor and a fourth transistor are turned off. In the second period, the first transistor and the second transistor are turned off, and the third transistor and the fourth transistor are alternately turned on and off repeatedly. Accordingly, the time during which the transistor is on can be reduced, so that degradation of characteristics of the transistor can be suppressed.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: December 29, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Kimura, Atsushi Umezaki
  • Patent number: 10861504
    Abstract: Systems, apparatuses, and methods for implementing dynamic control of a multi-region fabric are disclosed. A system includes at least one or more processing units, one or more memory devices, and a communication fabric coupled to the processing unit(s) and memory device(s). The system partitions the fabric into multiple regions based on different traffic types and/or periodicities of the clients connected to the regions. For example, the system partitions the fabric into a stutter region for predictable, periodic clients and a non-stutter region for unpredictable, non-periodic clients. The system power-gates the entirety of the fabric in response to detecting a low activity condition. After power-gating the entirety of the fabric, the system periodically wakes up one or more stutter regions while keeping the other non-stutter regions in power-gated mode. Each stutter region monitors stutter client(s) for activity and processes any requests before going back into power-gated mode.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: December 8, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Benjamin Tsien, Alexander J. Branover, Alan Dodson Smith, Chintan S. Patel
  • Patent number: 10840909
    Abstract: A signal outputting circuit including: an input line to which an input signal is inputted; a first current generating circuit connected to the input line, the first current generating circuit generating a first current having a magnitude corresponding to a level of a supplied power supply voltage; a second current generating circuit connected to the input line, the second current generating circuit generating a second current that turns ON and OFF in accordance with switching of a level of an output signal; a resistor element provided at the input line; and an outputting circuit that switches a logic level of the output signal in accordance with a level of voltage generated at the input line.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: November 17, 2020
    Assignee: KABUSHIKI KAISHA TOKAI-RIKA-DENKI-SEISAKUSHO
    Inventors: Akira Yajima, Tomoki Narita
  • Patent number: 10811960
    Abstract: A voltage doubler circuit supports operation in both a positive voltage boosting mode to positively boost voltage from a first node to a second node and a negative voltage boosting mode to negatively boost voltage from the second node to the first node. The voltage doubler circuit is formed by transistors of a same conductivity type that share a common bulk that is not tied to a source of any of the voltage doubler circuit transistors. A bias generator circuit is coupled to receive a first voltage from the first node and second voltage from the second node. The bias generator circuit operates to apply a lower one of the first and second voltages to the common bulk.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: October 20, 2020
    Assignee: STMicroelectronics International N.V.
    Inventor: Vikas Rana
  • Patent number: 10804902
    Abstract: An improved level shifter for use in integrated circuits is disclosed. The level shifter is able to achieve a switching time below 1 ns while still using the core power supply voltages, VDDL and VDDH, used in the prior art. The improved level shifter comprises a coupling stage and a level-switching stage.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: October 13, 2020
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Ryan Mei, Claire Zhu, Xiaozhou Qian
  • Patent number: 10784843
    Abstract: Disclosed is an inverter capable of withstanding a high voltage. The inverter includes a control voltage generating circuit, a high voltage transmission circuit, and a low voltage transmission circuit. The control voltage generating circuit generates a first group of control voltages and a second group of control voltages according to an input voltage, in which one group includes decrement voltages and the other group includes identical voltages. The high/low voltage transmission circuit is coupled between a high/low voltage terminal and an output terminal, wherein when the input voltage is low/high, the high/low voltage transmission circuit is turned on according to the first/second group of control voltages so that an output voltage of the output terminal is equal to a high/low voltage of the high/low voltage terminal.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: September 22, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsin-Cheng Hsu, Tay-Her Tsaur, Po-Ching Lin
  • Patent number: 10763849
    Abstract: A semiconductor integrated circuit includes: a power supply terminal that receives a power supply voltage; an external terminal; an output PMOS transistor connected between the power supply terminal and the external terminal; an auxiliary PMOS transistor connected between a gate of the output PMOS transistor and the external terminal; and a bias voltage generating circuit connected to a gate of the auxiliary PMOS transistor. The bias voltage generating circuit supplies a voltage lower than the power supply voltage to the gate of the auxiliary PMOS transistor, if it is necessary to maintain an OFF state of the output PMOS transistor by supplying an external voltage received at the external terminal to the gate of the output PMOS transistor.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: September 1, 2020
    Assignee: SOCIONEXT INC.
    Inventor: Masahisa Iida
  • Patent number: 10734995
    Abstract: An output circuit may be provided with: input and output terminals; a ground terminal shared by both an input side and an output side; a first switching element of n-channel type having first positive and negative electrodes, and a first gate; a second switching element of the n-channel type having second positive and negative electrodes, and a second gate; a diode; and a resistive element; in which the first positive electrode is connected with a power source, the first negative electrode is connected with the output terminal, anode of the diode is connected with the first negative electrode, cathode of the diode is connected with the first gate, the resistive element is connected between the source and the first gate, the second positive electrode is connected with the first gate, the second negative electrode is connected with the ground terminal, and the second gate is connected with the input terminal.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: August 4, 2020
    Assignee: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO
    Inventors: Norikazu Oota, Kanae Murata, Takashi Ozaki
  • Patent number: 10693450
    Abstract: An apparatus is provided which comprises: a dual stack voltage driver, wherein the dual stack voltage driver comprises a first stack of transistors, and a second stack of transistors; and one or more feedback transistors each coupled to a transistor of the second stack of transistors.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: June 23, 2020
    Assignee: Intel IP Corporation
    Inventors: Dharmaray Nedalgi, Karthik Ns, Vani Deshpande, Leonhard Heiss
  • Patent number: 10686434
    Abstract: A circuit includes a first power node configured to carry a first voltage having a first voltage level, an output node, a node coupled between the first power node and the output node, and a contending transistor coupled between the node and a second power node configured to carry a second voltage having a second voltage level. The circuit generates a signal at the output node that ranges between the first voltage level and a third voltage level, the contending transistor couples the node with the second power node responsive to the signal, a difference between the first voltage level and the second voltage level has a first magnitude, a difference between the first voltage level and the third voltage level has a second magnitude, and the second magnitude is a multiple of the first magnitude having a value greater than one.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong Chern, Tsung-Ching Huang, Chih-Chang Lin, Ming-Chieh Huang, Fu-Lung Hsueh
  • Patent number: 10684669
    Abstract: A logic level shifter interface including a string of logic components communicating between a first power domain and a second power domain; a first string of resistive components connecting a first power rail of the first power domain to a first power rail of the second power domain and having a plurality of intermediate first power rails at nodes between adjacent resistive components of the first string of resistive components; and a second string of resistive components connecting a second power rail of the first power domain to a second power rail of the second power domain and having a plurality of intermediate second power rails at nodes between adjacent resistive components of the second string of resistive components, where at least one logic component is powered by an intermediate first power rail of the first string of resistive components and an intermediate second power rail of the second string of resistive components.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: June 16, 2020
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Xin Zhou, Brett A. Miwa
  • Patent number: 10685729
    Abstract: Disclosed are a shift register element, a method for driving the same, and a display panel. The method includes: an output module including a first node and a third node, wherein the output module is configured to provide an output terminal with a signal of a first signal terminal or a second signal terminal according to voltage applied to the first node and the third node; a first driver configured to control the voltage of the first node, and voltage of a second node according to signals of the first input terminal and the second input terminal; a second driver configured to control voltage of the third node according to the voltage of the first node and the second node; and a feedback regulation module configured to control voltage of the first node according to the signal of the output terminal, and signals of a third input terminal and a fourth input terminal.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: June 16, 2020
    Assignee: SHANGHAI TIANMA AM-OLED CO., LTD.
    Inventors: Yue Li, Renyuan Zhu, Dongxu Xiang, Zhonglan Cai, Juan Zhu
  • Patent number: 10659016
    Abstract: Provided is a level shifter which can retain an operation margin and enhance an exceeded-breakdown-voltage preventing effect. The level shifter in an embodiment includes an exceeded-breakdown-voltage prevention circuit between a pair of first-conductivity-type cross-coupled transistors and a pair of second-conductivity-type input transistors. The exceeded-breakdown-voltage prevention circuit includes first-conductivity-type first transistors and second-conductivity-type second transistors which are coupled in series to each other, and first-conductivity-type third transistors coupled in series to the first and second transistors on a higher-potential side.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: May 19, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yoji Kashihara
  • Patent number: 10621944
    Abstract: A gate voltage generation circuit generates a gate voltage including a first voltage, a second voltage and a third voltage and supplies the gate voltage to a pixel transistor of a display device. The first voltage is a voltage for opening the pixel transistor. The second voltage is lower than the first voltage and is a voltage for closing the pixel transistor. The third voltage is an intermediate voltage between the first voltage and the second voltage. The voltage rises by way of the intermediate voltage at the time of rising from the second voltage to the first voltage.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: April 14, 2020
    Assignee: Japan Display Inc.
    Inventor: Gen Koide
  • Patent number: 10581432
    Abstract: A level shift circuit which comprises a voltage applying part configured to apply predetermined voltage to a first node intermittently. An input part receives an input signal and applies reference voltage to a second node when a signal level of the input signal is equal to a first voltage level. A switching part connects the second node and the first node with each other during the voltage applying part does not apply the predetermined voltage to the first node. The switching part cuts off the connection between the second node and the first node during the voltage applying part applies the predetermined voltage to the first node. An inverter provides a phase-inverted signal of the signal given to the first node as an output signal.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: March 3, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Yuto Hidaka
  • Patent number: 10581433
    Abstract: An integrated circuit device includes dispatcher circuitry that receives signals from a first number of sources, multiplexes the signals into a single mixed signal in a predetermined order, and transmits the mixed signal to a destination via a mixed signal interface having an arbitrary length and operating at an interface clock frequency equal to a product of a device clock frequency and the first number. A second number of samplers is disposed in series along the mixed signal interface, outputting a sampled mixed signal synchronized to the interface clock. A chain of tracking elements in series, corresponding in number to the second number, outputs a tracking indication separate from the sampled mixed signal. Capture circuitry demultiplexes the sampled mixed signal into a plurality of demultiplexed signals, according to a starting point based on the tracking indication, onto a plurality of signal buses corresponding in number to the first number.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: March 3, 2020
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventors: Lior Moheban, Jacob Jul Schroder, Yuval Peled
  • Patent number: 10559606
    Abstract: Provided is a semiconductor device which can operate stably even in the case where a transistor thereof is a depletion transistor. The semiconductor device includes a first transistor for supplying a first potential to a first wiring, a second transistor for supplying a second potential to the first wiring, a third transistor for supplying a third potential at which the first transistor is turned on to a gate of the first transistor and stopping supplying the third potential, a fourth transistor for supplying the second potential to the gate of the first transistor, and a first circuit for generating a second signal obtained by offsetting a first signal. The second signal is input to a gate of the fourth transistor. The potential of a low level of the second signal is lower than the second potential.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: February 11, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Atsushi Umezaki
  • Patent number: 10541676
    Abstract: In a described example, an apparatus includes a driver circuit coupled to an output pad, the driver having a p-channel FET coupled between a positive peripheral voltage and the pad, and having a first gate terminal coupled to a first gate control signal, and an n-channel FET coupled between the pad and a ground terminal and having a second gate terminal coupled to a second gate control signal. A predriver circuit is coupled to receive a data signal for output to the pad and further coupled to output the first gate control signal; and the predriver circuit is coupled to output a supply voltage to the first gate control signal in a first mode, and to output a bias voltage less than the supply voltage to the first gate control signal in a second mode; and a bias circuit is coupled for outputting the bias voltage.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: January 21, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Venkateswara Reddy Pothireddy, Wahed Abdul Mohammed
  • Patent number: 10483753
    Abstract: A signal processing circuit includes a first circuit coupled between a power terminal and a first ground terminal and a second circuit coupled between the power terminal and a second ground terminal. The signal processing circuit is configured to receive a first signal at a voltage level relative to the first ground terminal and, in response to the first signal, provide a second signal at a voltage level relative to the second ground terminal. The signal processing circuit can be used in a battery protection circuit for a mobile device having an embedded battery. The battery protection circuit is configured with two NMOS transistors to allow the cell phone circuit to switch between the embedded battery and an external power source.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: November 19, 2019
    Assignee: BCD Semiconductor Manufacturing Limited
    Inventors: Shaohua Peng, Xuguang Zhang
  • Patent number: 10475780
    Abstract: A method for configuring level shifter spare cells includes providing a power rail connectable to a corresponding power domain, and providing a spare cell including a level shifter circuit. The level shifter circuit has first and second terminals that are connectable to the power rail, and the first and second terminals are floating with respect to the power rail.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: November 12, 2019
    Assignee: NXP USA, Inc.
    Inventors: Zhe Ge, Miaolin Tan, Peidong Wang
  • Patent number: 10439596
    Abstract: In order to reduce a signal propagation delay when an input signal falls, an NMOS transistor (M1) is connected between an input terminal (1) receiving a signal having an amplitude of 3.3 V and an input of an inverter (INV1). A first PMOS transistor (M2) having a low drive capability and a second PMOS transistor (M4) having a high drive capability are connected in parallel between a power supply terminal (VDD 18) supplying 1.8 V and a gate of the NMOS transistor (M1). A gate of the first PMOS transistor (M2) is connected to the input of the inverter (INV1). A gate of the second PMOS transistor (M4) is connected to an output of the inverter (INV1).
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: October 8, 2019
    Assignee: SOCIONEXT INC.
    Inventor: Masahisa Iida
  • Patent number: 10394299
    Abstract: A system includes a processing core built on a semiconductor substrate, the processing core having a first sub core and a second sub core, each of the first and second sub cores configured to perform a processing function, and a plurality of power rails traversing a dimension of the processing core and spanning from the first sub core to the second sub core, each of the power rails being configured to provide an operating voltage to the first and second sub cores, and wherein a boundary between the first sub core and the second sub core is irregularly shaped, and wherein each of the first and second sub cores corresponds to a respective power domain.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: August 27, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Satish Raj, Shiva Ram Chandrasekaran, Li Qiu, Arun Tyagi, Mathew Philip, Rajesh Verma
  • Patent number: 10382040
    Abstract: A high voltage level shifting circuit and related semiconductor devices are presented. The circuit comprises: a level conversion circuit that converts an input signal with a first high voltage to an output signal with a second high voltage; a first switch having a first node connected to a first power source and a second node connected to a control node of a first transistor; a second switch having a first node connected to the control node of the first transistor and a second node connected to a first connection node; and a switch control circuit connected to the first switch and the second switch and controls them not to be close at the same time. By adding these two switches to the level conversion circuit, this inventive concept substantially lowers the static current generated during a high voltage level conversion process.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: August 13, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Yi Jin Kwon, Hao Ni, Chang Wei Yin, Hong Yu
  • Patent number: 10326431
    Abstract: A novel clock level-shifter to reduce duty-cycle distortion across wide input-output voltage operating range is disclosed. In some implementations, a level shifter includes an input stage coupled to a first power supply to receive an input signal, an output stage coupled to a second power supply to generate an output signal, and a first switch coupled directly between the output stage and the second power supply, wherein the input signal turns on or off the first switch. In some implementations, the first switch has a gate, a source, and a drain, the source being coupled to the second power supply, the drain being coupled to the output stage, and the gate being driven directly by the input signal.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: June 18, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Pratik Rajeshbhai Patel, Percy Tehmul Marfatia, Rajagopal Narayanan
  • Patent number: 10312910
    Abstract: The integrated circuit connection device (1) enables an external component to be connected. The integrated circuit is powered by a supply voltage (VDD) and part of the circuit operates using at least one internal regulated voltage (VREG). The connection device includes two active transistors (N1, P1) of different conductivity connected in series between the supply voltage (VDD) and earth (VSS). The drains of these two active transistors (N1, P1) are connected to each other so as to form an external contact pad (2). The gates of these active transistors are controlled by voltage signals that have the same amplitude (Vesd). The connection device further includes switching means (3) for modifying the control signals (Vesd) applied across the active transistor gates, without exceeding the highest voltage between the supply voltage (VDD) and the internal regulated voltage (VREG).
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: June 4, 2019
    Assignee: EM MICROELECTRONIC-MARIN SA
    Inventors: Yves Theoduloz, Hugo Jaeggi, Lubomir Plavec
  • Patent number: 10312816
    Abstract: A primary controller of a switching power supply and the switching power supply are provided. The primary controller includes an input voltage detection module which receives a detected signal and generates a detection signal; a controller module which receives a feedback signal and a current sampling signal of the switching power supply, and generates a control signal according to the feedback signal and the current sampling signal; a PWM signal generation module, receive the detection signal and the control signal, generate a PWM signal according to the control signal when the detection signal is the second level, and stop generating the PWM signal when the detection signal is the first level; and a power switch transistor, having a control terminal coupled with an output terminal of the PWM signal generation module.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: June 4, 2019
    Assignee: SUZHOU POWERON IC DESIGN CO., LTD.
    Inventors: Changshen Zhao, Haisong Li, Wenliang Liu, Yangbo Yi
  • Patent number: 10278862
    Abstract: A laser eye surgery system comprises subsystems which communicate with one another through low voltage differential signaling (LVDS). The laser eye surgery system may comprise a first subsystem interface, including an LVDS driver or transmitter coupled to and in communication with an LVDS receiver of a first subsystem of the laser eye surgery system. The first laser eye surgery subsystem itself may comprise an LVDS transmitter coupled to and in communication with an LVDS receiver to return data to the first subsystem. Further laser eye surgery subsystems may also include the same arrangement of drivers and receivers with respective subsystem interfaces. LVDS lowers power consumption and the risk of error in communication between laser eye surgery systems, leading to safer and more reliable surgical procedures performed.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: May 7, 2019
    Assignee: OPTIMEDICA CORPORATION
    Inventor: Jan C. Wysopal
  • Patent number: 10263616
    Abstract: A radio frequency switch having a first node, a second node, and a plurality of switch cells that are coupled in series between the first node and the second node is disclosed. Each of the plurality of switch cells is made up of a main field-effect transistor (FET) having a main drain terminal, a main source terminal, a main gate terminal, and a main body terminal. Further included is a first body bias FET having a first drain terminal coupled to the main gate terminal, a first gate terminal coupled to the main drain terminal, a first body terminal coupled to the main body terminal, and a first source terminal, and a second body bias FET having a second drain terminal coupled to the main gate terminal, a second body terminal coupled to the main body terminal, and a second source terminal coupled to the first source terminal.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: April 16, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Baker Scott, George Maxim, Dirk Robert Walter Leipold
  • Patent number: 10243564
    Abstract: An input-output (I/O) receiver includes a receiving terminal, a first N-type metal-oxide-semiconductor (NMOS) transistor, a reformation circuit, and a compensation unit. The receiving terminal is coupled with an external voltage signal. The first NMOS transistor has a source electrode coupled with the receiving terminal and a gate electrode coupled with a first power supply voltage. The reformation circuit is configured to reform a voltage signal transmitted from a drain electrode of the first NMOS transistor. The compensation unit includes a first PMOS transistor, a second PMOS transistor, and a second NMOS transistor. Moreover, the compensation unit is configured to provide a compensation voltage to a voltage signal at the drain electrode of the first NMOS transistor thereby a maximum level of the voltage signal at the drain electrode of the first NMOS transistor reaches the first power supply voltage.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: March 26, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Shan Yue Mo, Jie Chen
  • Patent number: 10199091
    Abstract: An apparatus is described. The apparatus includes a semiconductor chip. The semiconductor chip includes a memory having multiple storage cells. The storage cells are to receive a supply voltage. The semiconductor chip includes supply voltage retention circuitry. The supply voltage retention circuitry is to determine a level of the supply voltage at which the storage cells are able to retain their respective data. The supply voltage retention circuitry is to receive the supply voltage during a stress mode of the supply voltage retention circuitry. The supply voltage retention circuitry is to more weakly retain its stored information than the storage cells during a measurement mode at which the level is determined.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: February 5, 2019
    Assignee: Intel Corporation
    Inventors: Minki Cho, Jaydeep Kulkarni, Carlos Tokunaga, Muhammad Khellah, James Tschanz
  • Patent number: 10194109
    Abstract: A data transfer circuit includes a first layer for transmitting first bits and a second layer for transmitting second bits. Each of the first layer and the second layer includes: first to mth banks configured to convert a plurality of received digital pixel signals into first to mth analog voltage signals, wherein ‘m’ denotes an integer which is greater than or equal to ‘2’; first to mth samplers configured to convert the first to mth analog voltage signals into first to mth digital transmission signals; and first to mth digital transfer units configured to respectively receive the first to mth digital transmission signals.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: January 29, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hyeok Jong Lee
  • Patent number: 10176879
    Abstract: Disclosed are a high voltage switch circuit and a semiconductor memory device including the same. The high voltage switching circuit includes: a control signal generating circuit configured to supply a supply voltage to an internal node and generate a control signal in response to a first enable signal; a well bias generating circuit configured to apply a well bias to a well of a transistor included in the control signal generating circuit in response to a second enable signal; and a switching circuit configured to switch an input voltage to an output voltage in response to the control signal.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: January 8, 2019
    Assignee: SK Hynix Inc.
    Inventors: Dong Hwan Lee, Min Gyu Koo
  • Patent number: 10140243
    Abstract: Systems, methods, and apparatus for implementing hardware flow control between devices coupled through a serial peripheral interface. A method for transmitting information using a serial peripheral interface includes initiating an exchange of data over one or more data lines of a serial peripheral interface bus by asserting a first voltage state on a slave select line, transmitting data and clock signals over the serial peripheral interface bus while the slave select line remains at the first voltage state, refraining from transmitting data and clock signals over the serial peripheral interface bus when the slave select line transitions to a second first voltage state, receiving data at a slave device into a receive buffer while the slave select line remains at the first voltage state, and asserting the second voltage state on the slave select line when occupancy of the receive buffer reaches or exceeds a threshold occupancy level.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: November 27, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Lalan Jee Mishra, Richard Dominic Wietfeldt
  • Patent number: 10067000
    Abstract: The invention provides an inverter. The inverter includes a first converter and a second converter. The first converter is coupled between a supply voltage and an output node of the inverter. The second converter is coupled between the output node of the inverter and a ground voltage. The first converter, the second converter, or both include diode-connected transistors. The propagation delay time of the inverter is substantially a linear function of the temperature of the inverter.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: September 4, 2018
    Assignee: MEDIATEK INC.
    Inventors: Bo-Jr Huang, Yi-Feng Chen, Jia-Wei Fang
  • Patent number: 10014861
    Abstract: Level shifters, memory systems, and level shifting methods are described. According to one arrangement, a level shifter includes an input configured to receive an input signal in a first voltage domain, an output configured to output an output signal from the level shifter in a second voltage domain different than the first voltage domain, a plurality of pull-down devices, and wherein one of the pull-down devices is coupled with the input and the output, a plurality of cross-coupled devices coupled with the pull-down devices and configured to provide transitions in the output signal as a result of transitions in the input signal, a plurality of current limiting devices coupled with the cross-coupled devices and configured to limit a flow of current from a source to the cross-coupled devices, and a plurality of dynamic devices configured to selectively provide charging current from the source to the cross-coupled devices.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: July 3, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Yogesh Luthra
  • Patent number: 9947695
    Abstract: Exemplary semiconductor devices include eight transistors and two capacitors interconnected in specific configurations. A display device may include a driver circuit having such a semiconductor device. An electronic device may also include such a semiconductor device and an input unit, LED lamp or speaker.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: April 17, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Masashi Tsubuku, Kosei Noda
  • Patent number: 9941704
    Abstract: A number of load units are connected to receive power from a number of power supply units. A potential load bus is connected to have a voltage level representative of both a total potential power requirement of the number of load units and a total potential power supply capability of the number of power supply units. A first control circuit enables operation of the number of load units when the voltage level on the potential load bus indicates that a sufficient supply of power is available. An actual load bus is connected to have a voltage level representative of both an actual total power consumption of the number of load units and an actual total power supply available from of the number of power supply units. A second control circuit signals an impending loss of sufficient power supply based on the monitored voltage level on the actual load bus.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: April 10, 2018
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: J. Rothe Kinnard, Robert Cyphers, Brian Benstead
  • Patent number: 9912335
    Abstract: Aspects of this disclosure are directed to level-shifting approaches with communications between respective circuits. As may be implemented in accordance with one or more embodiments characterized herein, a voltage level of communications passed between respective circuits are selectively shifted. Where the respective circuits operate under respective power domains that are shifted in voltage range relative to one another, the voltage level of the communications is shifted. This approach may, for example, facilitate power-savings for stacked circuits in which a low-level voltage of one circuit is provided as a high-level voltage for another circuit. When the respective circuits operate under a common power domain, the communications are passed directly between the respective circuits (e.g., bypassing any level-shifting, and facilitating fast communication).
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: March 6, 2018
    Assignee: NXP B.V.
    Inventors: Ajay Kapoor, Kristof Blutman, Jose Pineda de Gyvez, Arnoud van der Wel