Abstract: A level shifter is disclosed and includes at least four Type 1 transistors and at least four Type 2 transistors. The sources of several Type 1 transistors are electrically connected to a first voltage terminal while the sources of several Type 2 transistors are connected to a second voltage terminal. The level shifter receive an input signal and outputs a logically equivalent output signal with higher voltage, wherein the voltage of the output signal is between the voltages of the first voltage terminal and the second voltage terminal.

Abstract: A structure is described having a plurality of electronic devices with the same or different internal CMOS voltages; an interconnection between two or more of the electronic devices; driver and receiver circuits which provide selectable input/output voltage levels for interfacing with several generations of CMOS technology, thus allowing chips fabricated in such technologies to communicate using a signal voltage range most suitable for each chip; Circuitry for selecting or adjusting the type of receiver circuit used, thus allowing either the use of a differential comparator circuit with an externally supplied reference voltage, or alternatively, the use of an inverter style receiver with an adjustable threshold, the selection being accomplished by setting the external reference to a predetermined voltage; Circuitry for selecting or adjusting the switching threshold of the inverter receiver circuit, which enables the threshold to be set appropriately for a given input signal voltage range.

Abstract: In various embodiments, a circuit arrangement may be provided. The circuit arrangement may include a level shifting stage configured to be coupled to a first reference voltage, the level shifting stage having an output node. The circuit arrangement may further include a first input electrode in electrical connection with the level shifting stage. The circuit arrangement may also include a second input electrode in electrical connection with the level shifting stage. The circuit arrangement may further include a load having a first end and a second end, the first end coupled to the level shifting stage and the second end for coupling to a second reference voltage. In addition, the circuit arrangement may include a bypass circuit element connected in parallel to the load. The bypass circuit element may be configured to allow current to flow through upon application of an external voltage for bypassing the load.

Abstract: A semiconductor integrated circuit includes a bypass circuit that forms a bypass path under a low voltage condition, and the bypass circuit includes first and second bypass MOS transistors respectively placed between drains of first and second PMOS transistors and a ground voltage terminal, each transistor having a gate to which a second power supply voltage is applied, and third and fourth bypass MOS transistors respectively placed between the first and second bypass MOS transistors and the ground voltage terminal, each transistor controlled to be ON and OFF in accordance with an input signal and a voltage condition.

Abstract: An interface input has an input circuit adapted to receive input signal levels higher than a maximum signal level that a host circuitry's electronic components can reliably handle. The input circuit shifts the level of the input signal to a desired signal level. A keeper circuit is coupled to the input circuit and maintains trigger levels of the shifted signals consistent with the input signal level.

Abstract: A level shift circuit includes an input port to which an input signal is input, a first signal amplifying unit configured to amplify the input signal input to the input port, a node at the first signal amplifying unit to output the amplified signal, a level shift input port to which a level shift voltage for controlling a DC level of the node is input, a first supply voltage configured to drive the first signal amplifying unit, and a level shift voltage generation circuit configured to generate the first supply voltage and the level shift voltage.

Abstract: A level shift circuit of the invention includes a CMOS inverter circuit that receives an input pulse signal having a crest value of a first potential, a latch circuit that operates on a power supply of a second potential which is higher than the first potential, and a power supply circuit that supplies a power supply of not less than the first potential and less than the second potential to the CMOS inverter circuit. The latch circuit has one end thereof connected to an output end of the CMOS inverter circuit and outputs from the other end thereof an output pulse signal having a crest value of the second potential and a same phase as the input pulse signal. The power supply circuit functions to limit the power supply when the input pulse signal assumes at least the ground level.

Abstract: Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.

Abstract: A level shifter shifts the level of an input signal from a second voltage domain to a first voltage domain. To accommodate different input signal levels (e.g., including sub-threshold input signal levels) that may arise due to changes in the supply voltage for the second voltage domain, current for a latch circuit of the level shifter is limited based on the supply voltage for the second voltage domain. In this way, a drive circuit of the level shifter that controls the latch circuit based on the input signal is able to initiate a change of state of the latch circuit over a wide range of input signal levels.

Abstract: According to one embodiment, a semiconductor integrated circuit includes first and second level shift circuits. The first level shifter includes a plurality of transistors and is connected to a power source voltage supply node of a first power source system and to which a first signal of a second power source system and a level inversion signal of the first signal are input. The second level shifter includes a plurality of transistors and is connected to the power source voltage supply node of the first power source system and to which the level inversion signal of the first signal of the second power source system and an output signal of the first level shifter are input. The first and second level shifters have substantially the same circuit configuration and driving abilities of corresponding ones of the transistors in the first and second level shifters are substantially set equal.

Abstract: A level shifting multiplexer is disclosed. In one embodiment, a multiplexer is coupled to receive a first input signal from circuitry in a first power domain and a second input signal from circuitry in a second power domain. The multiplexer is configured to output a selected one of the first and second input signals to circuitry in the second power domain. The multiplexer also includes a level shifter circuit. When the first input signal is selected, the level shifter circuit may be enabled. When enabled, the level shifter circuit may level shift the first signal such that its voltage swing corresponds to that of the second voltage domain. The multiplexer may also include isolation circuitry configured to inhibit the level shifter.

Abstract: A dynamic level shifter is disclosed. In one embodiment, a dynamic level shifter circuit may receive an input signal referenced to a first voltage of a first power domain, and may output a corresponding signal referenced to a second voltage into a second power domain. The dynamic level shifter circuit may include an evaluation node that is precharged during a first phase (e.g., the low portion) of a clock signal. During the second phase (e.g., the high portion) of the clock signal, the evaluation node may be either pulled low or high, depending on the state of the input signal. A corresponding output signal, based on the evaluated level on the evaluation node, may be output into the second power domain.

Abstract: A CMOS logic integrated circuit includes a level shifter and a CMOS logic circuit. The level shifter converts a signal of a first logic level to a signal of a second logic level. The signal of the first logic level changes between a first low potential and a first high potential higher than the first low potential. The signal of the second logic level changes between the first low potential and a second high potential higher than the first high potential. The CMOS logic circuit includes a first N-channel type MOSFET and a second N-channel type MOSFET. The second N-channel type MOSFET is connected in series with the first N-channel type MOSFET. A first signal of the first logic level is input into a gate of the first N-channel type MOSFET. A second signal of the second logic level has an inversion relationship with the first signal.

Abstract: A semiconductor device includes a first input buffer adjusting a logic threshold voltage, a first replica circuit, a first reference voltage generating circuit, and a first comparator circuit. The first replica circuit is identical in circuit configuration to the first input buffer. The first replica circuit has an input and an output connected to the input. The first replica circuit generates the logic threshold voltage as an output voltage. The first reference voltage generating circuit generates a first reference voltage. The first comparator circuit compares the logic threshold voltage as an output voltage of the first replica circuit to the first reference voltage to generate a first threshold adjustment signal. The first comparator circuit supplies the first threshold adjustment signal to the first input buffer and the first replica circuit. The first threshold adjustment signal allows the first input buffer to adjust the logic threshold voltage.

Abstract: A level shift circuit including a level conversion unit that converts an input signal having a signal level of a first voltage into a signal having a signal level of a second voltage that is higher than the first voltage. The level conversion unit includes first and second MOS transistors of a first conductivity type and third and fourth MOS transistors of a second conductivity type, which differs from the first conductivity type and of which switching is controlled in accordance with the input signal. The third and fourth MOS transistors include drains supplied with the second voltage via the first and second MOS transistors, respectively. A control unit, when detecting a decrease in the first voltage, controls a body bias of the third and fourth MOS transistors to decrease a threshold voltage of the third and fourth MOS transistors.

Abstract: An input circuit includes an inverter, a first path control circuit and a second path control circuit. An input of the inverter is connected with a first node. A target inversion potential is higher than an inversion potential of the inverter. The first path control circuit electrically connects an input terminal and the first node when the input potential is higher than the target inversion potential, and blocks off an electrical connection between the input terminal and the first node when the input potential is lower than the target inversion potential. The second path control circuit electrically connects a ground terminal and the first node when the input potential is lower than a second inversion potential which is lower than the target inversion potential and blocks off the electrical connection between the ground terminal and the first node when the input potential is higher than the second inversion potential.

Abstract: An integrated circuit has a level shifter, a pull-circuit, and a voltage regulator. The level shifter and the pull-up circuit receive power from the same supply voltage. The voltage regulator changes the voltage level from the supply voltage to another voltage level used by the level shifter.

Abstract: A level-up shifter circuit is suitable for high speed and low power applications. The circuit dissipates almost no static power, or leakage current, compared to conventional designs and can preserve the signal's duty cycle even at high data rates. This circuit can be used with a wide range of power supplies while maintaining operational integrity.

Abstract: Implementations to mitigating side effects of impedance transformation circuits are described. In particular, mitigation circuitry may be coupled to a high impedance circuit to minimize or eliminate non-linear output of the high impedance circuit in order to provide a well-defined bias voltage to the input of a buffer or amplifier device coupled to a capacitive sensor. Additionally, the mitigation circuitry may be coupled to the high impedance circuit to reduce or eliminate rectifying effects of the high impedance circuit. Accordingly, a bias voltage can be utilized to provide a stable operating point of the buffer or amplifier device via a high impedance circuit utilizing one or more impedance transformations.

Abstract: An output circuit which outputs an output signal based on an input signal from an output terminal and brings the output terminal into a high impedance state in response to an impedance control signal. The output circuit includes an output pMOS transistor connected at a source thereof to a first power supply. The output circuit includes an output nMOS transistor connected between a drain of the output pMOS transistor and ground. The output circuit includes an output terminal connected between the drain of the output pMOS transistor and a drain of the output nMOS transistor. The output circuit includes a first level shifter circuit which outputs a first gate control signal from a first gate control terminal to control on/off of the output pMOS transistor. The output circuit includes a second level shifter circuit which outputs a second gate control signal from a second gate control terminal to control on/off of the output nMOS transistor.

Abstract: In a level shift circuit allows satisfactory operation with short delay time in the case of low-voltage setting of a low-voltage source, for example, when a state of an input signal IN transitions from a H (VDD) level to a L level, a node W2 precharged to a H (VDD3) level is discharged to ground (VSS) by a discharge circuit N2, and decreases in potential. The decrease in potential propagates to a latch circuit LA, and an output of the latch circuit LA propagates to an output circuit OC. Further, an inversion signal of the node W2 is input to the output circuit OC by bypassing the latch circuit LA. Thus, the output circuit OC starts operating prior to operation based on an output of the latch circuit LA.

Abstract: A semiconductor device includes a code generator and a level shifter. The code generator generates a code including one bit that is in a first logic state and at least one bit that is in a second logic state. The level shifter outputs signals that are at a first voltage level or at a second voltage level through a plurality of output terminals in response to the code. The level shifter includes a plurality of voltage controllers and a plurality of voltage converters. All but one of the voltage controllers control first signals output through all but one of the output terminals to be at the first voltage level in response to the at least one bit. One of the voltage converters controls a second signal output through the remaining output terminal to be at the second voltage level in response to the first signals.

Abstract: A level shifter is provided. The level shifter includes a signal converter connected to an external power source and a ground, first and second output terminals connected to the signal converter, the first and second output terminals being configured to output a bias voltage applied from the external power source, and a switching unit configured to switch a connection state of the signal converter according to an input signal to adjust output voltage values of the first and second output terminals, the switching unit including first and second transistors, the first transistor being of a type that is different from a type of the second transistor, the first and second transistors being connected to each other in series between an input terminal, to which an input signal is applied, and the external power source, gates of the first and second transistors being commonly connected to the second output terminal.

Abstract: A level shift circuit of the invention includes a CMOS inverter circuit that receives an input pulse signal having a crest value of a first potential, a latch circuit that operates on a power supply of a second potential which is higher than the first potential, and a power supply circuit that supplies a power supply of not less than the first potential and less than the second potential to the CMOS inverter circuit. The latch circuit has one end thereof connected to an output end of the CMOS inverter circuit and outputs from the other end thereof an output pulse signal having a crest value of the second potential and a same phase as the input pulse signal. The power supply circuit functions to limit the power supply when the input pulse signal assumes at least the ground level.

Abstract: A level shifter includes one PMOS and two NMOS transistors. A source of the first NMOS transistor is coupled to a low power supply voltage. An input signal is coupled to a gate of the first NMOS transistor and a source of the second NMOS transistor. The input signal has a voltage level up to a first power supply voltage. A source of the PMOS transistor is coupled to a second power supply voltage, higher than the first power supply voltage. An output signal is coupled between the PMOS and the first NMOS transistors. The first NMOS transistor is arranged to pull down the output signal when the input signal is a logical 1, and the second NMOS transistor is arranged to enable the PMOS transistor to pull up the output signal to a logical 1 at the second power supply voltage when the input signal is a logical 0.

Abstract: In a semiconductor device having a terminal connected to an internal portion, a termination circuit for providing on-die termination for the terminal of the device. The termination circuit comprises a plurality of transistors, including at least one NMOS transistor and at least one PMOS transistor, connected between the terminal and a power supply; and control circuitry for driving a gate of each of NMOS transistor with a corresponding NMOS gate voltage and for driving a gate of each PMOS transistor with a corresponding PMOS gate voltage, the control circuitry being configured to control the NMOS and PMOS gate voltages so as to place the transistors in an ohmic region of operation when on-die termination is enabled. The power supply supplies a voltage that is less than each said NMOS gate voltage and greater than each said PMOS gate voltage.

Abstract: First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an input circuit and a differential output driver connected to the single pair of LVDS signal paths. An input to the input circuit is also connected to the input of the driver. The input circuit may also receive an offset voltage. In response to its inputs, the input circuit in each device can use comparators, gates and a multiplexer to determine the logic state being transmitted over the pair of LVDS signal paths from the other device. This advantageously reduces the number of required interconnects between the first and second devices by one half.

Abstract: Apparatuses and methods for well buffering are disclosed. In one embodiment, an apparatus includes a complimentary metal oxide semiconductor (CMOS) switch having a gate, a drain, a source, and a well. The source and drain are formed in the well, and the gate is formed adjacent the well between the source and drain. The source is configured to receive a bias voltage from a power amplifier. The apparatus further includes a gate bias control block for biasing the gate voltage of the switch, a well bias control block for biasing the well voltage of the switch, and a buffer circuit for increasing the impedance between the well bias control block and the well of the switch.

Abstract: A level shifter includes first and second input terminals, first and second output terminals, first pull-down circuitry operable to pull down one of the first and second output terminals responsive to signals present on the first and second input terminals, first pull-up circuitry operable to pull up the first output terminal responsive to a signal present on the second output terminal or pull up the second output terminal responsive to a signal present on the first output terminal, and second pull-up circuitry operable to pull up one of the first and second output terminals responsive to the signals present on the first and second input terminals.

Abstract: A cascoded level shifter is subdivided into a first voltage section and a second voltage section, the first voltage section having a lower voltage supply than the second voltage section, and a combined voltage across the first voltage section and the second voltage section corresponding to the high voltage range. The shifter includes an input node receiving an input signal, a cascoded device disposed in one of the first voltage section and the second voltage section, the cascoded device includes a driver switch connected in series with a cascode switch at a midpoint node, the cascode switch switching in dependence on a reference voltage of a reference node and the input signal, and reference voltage perturbation circuitry configured to cause a transient perturbation to the reference voltage in response to a transition of the input signal to cause the cascode switch to switch.

Abstract: A data strobe signal output driver includes a trigger block, a predriver block, and a main driver block. The trigger block is configured to receive a first signal, a second signal, a first clock and a second clock, and to output a predrive signal based thereon. The predriver block is configured to receive the predrive signal, a driver off signal and a termination enable signal, and to output a first main drive signal and a second main drive signal based thereon. The main driver block is configured to output a data strobe signal based on the first and second main drive signals.

Abstract: A level converter circuit is provided for converting an input signal of a digital signal having a first signal level into an output signal having a second signal level higher than the first signal level. An amplifier circuit amplifies the input signal and outputs an amplified output signal, and a current generator circuit generates a control current corresponding to an operating current flowing through the amplifier circuit upon change of the signal level of the input signal. A current detector circuit detects the generated control current, and controls the operating current of the amplifier circuit to correspond to the detected control current. The current generator circuit includes series-connected first and second nMOS transistors as inserted between the current detector circuit and the ground. The first nMOS transistor operates responsive to the input signal, and the second nMOS transistor operates responsive to an inverted signal of the input signal.

Abstract: A voltage level shift circuit in which a difference in response characteristic depending on the signal level of an input signal is suppressed. The voltage level shift circuit generates an output signal VOUT having a voltage amplitude different from that of the input signal. An inverter INV2 generates a voltage V1 in the range of VSS to VDDI according to the input signal. An inverter INV3 generates a voltage V2 in the range of VSS to VPERI according to the input signal. An inverter INV4 generates the output signal VOUT according to V1 and V2.

Abstract: Some embodiments provide an integrated circuit (‘IC’) that includes at least first and second circuits operating at a first voltage. The IC includes, between the first and second circuits, a direct connection comprising a third circuit for transmitting a signal from the first circuit to the second circuit at a second voltage that is lower than the first voltage. At least one of the first and second circuits is a configurable circuit for configurably performing operations.

Abstract: A level shifter includes an input node, an output node, a pull-up transistor, a pull-down transistor, and at least one diode-connected device coupled between the pull-up transistor and the pull-down transistor. The level shifter is arranged to be coupled to a high power supply voltage, to receive an input signal having a first voltage level at the input node, and to supply an output signal having a second voltage level at the output node. The high power supply voltage is higher than the first voltage level. The at least one diode-connected device allows the output signal to be pulled up to about a first diode voltage drop below the high power supply voltage and/or to be pulled down to about a second diode voltage drop above ground. The first diode voltage drop and the second diode voltage drop are from the at least one diode-connected device.

Abstract: In a display device including a substrate, a pixel portion, and a driver circuit having first to ninth transistors and first and second inverters, the various transistors are configured such that one of a source and a drain of the fifth transistor is electrically connected to a gate of the first transistor. In embodiments, the electrical connection may be a direct connection. Additionally, a switch may be provided that is directly connected to an output terminal of the second inverter.

Abstract: A dual supply bidirectional level shifter performs voltage level shifting in two directions, low to high and high to low. A feedback control branch and a control stage inverter are provided that reduce leakage power and allow for low delay time while also allowing for a small circuit footprint.

Abstract: A circuit comprising an inverter coupled to an input and receiving an input signal. A first pull-down transistor coupled to the inverter, pulling down an output when the input signal is low. A second pull-down transistor coupled to the input, pulling down a complementary output when the input signal is high. A first pull-up transistor coupled to the complementary output, pulling up the output when the input signal is high. A second pull-up transistor coupled to the output, pulling up the complementary output when the input signal is low. A first switch receiving a first control signal, coupled to the complementary output. A first strong pull-up transistor coupled to the first switch, assisting the pull up of the output. A second switch coupled to the output, receiving a second control signal. A second strong pull-up transistor coupled to the second switch, assisting the pull up of the complementary output.

Abstract: Circuitry, operating in a high voltage domain, including a high and low voltage inputs, and including a plurality of devices designed to operate optimally powered in a native voltage domain that is lower voltage than said high voltage domain and some devices arranged in two sets. The circuitry including a further input for receiving the high native voltage level. Each set having at least one device, a first set being arranged to receive an intermediate low reference voltage level as a low voltage level signal and the high voltage level as a high voltage level signal and the second set being arranged to receive the high native voltage level as a high voltage level signal and the low voltage level as a low voltage level signal. The intermediate low reference voltage level includes a voltage level generated by subtracting the high native voltage level from the high voltage level.

Abstract: An interface between first and second voltage domains is provided. A level shifter is configured to receive an input signal from the first voltage domain and to level shift the input signal to provide an output signal for passing to the second voltage domain. A control signal generator is configured to generate a second voltage domain control signal in dependence on at least one first voltage domain control signal from a controller in the first voltage domain. The level shifter is configured to be in a retention state when the second voltage domain control signal has a first value, such that its output signal is held constant even when the controller becomes not actively driven by the first voltage supply. The level shifter is configured to be in a transmission state when the second voltage domain control signal has a second value, wherein the output signal depends on the input signal.

Abstract: An electronic device comprising a level shifter for performing a voltage shift of a low level input signal of a first voltage domain to a high level output signal of a second voltage domain, the level shifter having a high-side transistor in series with a low-side transistor so as to provide an output node between the channel of the high-side transistor and the channel of the low-side transistor for driving a load with the high level output signal of the second voltage domain. The level shifter being configured to have a first state in which the high-side transistor is conducting and the low-side transistor is not conducting, a second state in which the low-side transistor is conducting and the high-side transistor is not conducting and a third state in which the high-side transistor is not conducting and the low-side transistor is not conducting.

Abstract: A high-speed bus interface with an adaptive swing driver. A high speed interface includes a transmitter and a receiver coupled via a bus. The transmitter has an adaptive swing driver and a voltage-regulating-module (VRM). The adaptive swing driver includes a post-driver and a pre-driver. The post-driver provides an adaptive swing output with a dedicated adaptive voltage power supply (VDDQ) and transition emphasis driving capacity with an internal logic voltage supply (VDD). The pre-driver provides the transition emphasis driving capacity with a pull-up and a pull-down signal path to the post-driver. The voltage-regulating-module is configured to supply signal to the adaptive swing driver. The receiver includes a comparator and a bit-error-rate detector. The comparator amplifies the adaptive swing output received from the transmitter via a bus, while the bit-error-rate detector diagnoses the amplified adaptive swing output received from the comparator.

Abstract: A low-swing receiver includes a sense amplifier including a first transistor having a source connected with a first voltage supply and a gate for receiving a control signal, and a second transistor having a source connected with a second voltage supply, a drain connected to a drain of the first transistor, and a gate coupled to a second control signal via a capacitive element. A switching circuit is operative to selectively couple an input signal supplied to the sense amplifier with the gate of the second transistor as a function of a signal generated at an output of the sense amplifier. The sense amplifier is operative in a first mode to store charge in the capacitive element, and is operative in a second mode to impart a voltage on the gate of the second transistor which is indicative of the charge stored in the capacitive element.

Abstract: A level shift circuit is disclosed. The circuit includes a series circuit of a resistor and a switching device connected between a high voltage side power supply voltage in a secondary side voltage system and a low voltage side power supply voltage in a primary side voltage system, a series circuit of a resistor and a switching device connected between the high voltage side power supply voltage in the secondary side voltage system and the low voltage side power supply voltage in the primary side voltage system, and a latch malfunction protecting circuit operated in the secondary side voltage system to have voltages at a connection point of the resistor and the switching device and at a connection point of the resistor and the switching device inputted.

Abstract: According to one embodiment, a level shifter circuit operable with a low voltage input comprises first and second pull-down switches configured to receive the low voltage input as respective non-inverted and inverted control voltages, first and second pull-up switches coupled between the respective first and second pull-down switches and an output supply voltage, and a pull-up boost switching stage coupled to a node between the first pull-up switch and the first pull-down switch. The pull-up boost switching stage is configured to turn ON in response to the second pull-down switch turning ON, and to turn OFF before the first pull-up switch turns OFF. In one embodiment, the level shifter circuit may be implemented as part of an input/output (IO) pad of an integrated circuit (IC) fabricated on a semiconductor die.

Abstract: A level shift circuit includes: a pair of first and second P-channel transistors which are connected in a flip-flop manner and whose sources connected to a first power supply line; a pair of first and second N-channel transistors with the first N-channel transistor provided between the first P-channel transistor and a second power supply line and the second N-channel transistor provided between the second P-channel transistor and the second power supply line, in which input signals complementary to each other are inputted to their gates; and a current supply circuit provided between the first power supply line and a drain of the first N-channel transistor and between the first power supply line and a drain of the second N-channel transistor, respectively.

Abstract: A level shifter circuit is presented that can apply a negative voltage level to non-selected blocks while still being able to drive a high positive level when selected. An exemplary embodiment presents a negative level shifter that is not susceptible to low voltage pfet breakdown. This allows for a high voltage level shifter (transfer gate) that can drive a negative level for unselected blocks and, when enabled for a selected block, can still drive a positive high voltage level. By using a pair of low voltage PMOS device whose n-wells share the same level as other PMOS transistors in the design, layout area can be minimized. The gates of this pair of PMOSs are connected to VSS, thereby preventing these low voltage PMOS devices from thin oxide breakdown.

Abstract: To include a switch transistor inserted between a data bus and an input end of a signal receiving circuit and turned off when a potential of the data bus reaches VPERI?NVth, and an assist transistor that drives the input end of the signal receiving circuit to have VPERI. According to the present invention, because the switch transistor and the assist transistor assist a receiving operation performed by the signal receiving circuit, amplitude of a transferred signal can be reduced without reducing a transfer rate. With this configuration, power consumed by charging or discharging of the data bus can be reduced.

Abstract: A semiconductor device includes a chip, a plurality of pads that is formed along the perimeter of the chip, and that includes a first pad and a second pad placed next to the first pad, and a circuit that is formed on the chip, and that is coupled to the first and second pads. The circuit includes first and second conductivity type transistors that are coupled between first and second reference potentials and a comparator that includes a first input node coupled to the first pad and a second input node coupled to the second pad, and that compares a potential of the first input node with a potential of the second input node. The first pad is coupled to gate electrodes of the first and second conductivity type transistors, and the second pad is coupled to drain electrodes of the first and second conductivity type transistors.

Abstract: A circuit with a large load driving capability, which is structured by single polarity TFTs, is provided. With a capacitor (154) formed between a gate electrode and an output electrode of a TFT (152), the electric potential of the gate electrode of the TFT (152) is increased by a boot strap and normal output with respect to an input signal is obtained without amplitude attenuation of an output signal due to the TFT threshold value. In addition, a capacitor (155) formed between a gate electrode and an output electrode of a TFT (153) compensates for increasing the electric potential of the gate electrode of the TFT (152), and a larger load driving capability is obtained.