Abstract: A method for configuring level shifter spare cells includes providing a power rail connectable to a corresponding power domain, and providing a spare cell including a level shifter circuit. The level shifter circuit has first and second terminals that are connectable to the power rail, and the first and second terminals are floating with respect to the power rail.

Abstract: In order to reduce a signal propagation delay when an input signal falls, an NMOS transistor (M1) is connected between an input terminal (1) receiving a signal having an amplitude of 3.3 V and an input of an inverter (INV1). A first PMOS transistor (M2) having a low drive capability and a second PMOS transistor (M4) having a high drive capability are connected in parallel between a power supply terminal (VDD 18) supplying 1.8 V and a gate of the NMOS transistor (M1). A gate of the first PMOS transistor (M2) is connected to the input of the inverter (INV1). A gate of the second PMOS transistor (M4) is connected to an output of the inverter (INV1).

Abstract: A system includes a processing core built on a semiconductor substrate, the processing core having a first sub core and a second sub core, each of the first and second sub cores configured to perform a processing function, and a plurality of power rails traversing a dimension of the processing core and spanning from the first sub core to the second sub core, each of the power rails being configured to provide an operating voltage to the first and second sub cores, and wherein a boundary between the first sub core and the second sub core is irregularly shaped, and wherein each of the first and second sub cores corresponds to a respective power domain.

Abstract: A high voltage level shifting circuit and related semiconductor devices are presented. The circuit comprises: a level conversion circuit that converts an input signal with a first high voltage to an output signal with a second high voltage; a first switch having a first node connected to a first power source and a second node connected to a control node of a first transistor; a second switch having a first node connected to the control node of the first transistor and a second node connected to a first connection node; and a switch control circuit connected to the first switch and the second switch and controls them not to be close at the same time. By adding these two switches to the level conversion circuit, this inventive concept substantially lowers the static current generated during a high voltage level conversion process.

Abstract: A novel clock level-shifter to reduce duty-cycle distortion across wide input-output voltage operating range is disclosed. In some implementations, a level shifter includes an input stage coupled to a first power supply to receive an input signal, an output stage coupled to a second power supply to generate an output signal, and a first switch coupled directly between the output stage and the second power supply, wherein the input signal turns on or off the first switch. In some implementations, the first switch has a gate, a source, and a drain, the source being coupled to the second power supply, the drain being coupled to the output stage, and the gate being driven directly by the input signal.

Abstract: The integrated circuit connection device (1) enables an external component to be connected. The integrated circuit is powered by a supply voltage (VDD) and part of the circuit operates using at least one internal regulated voltage (VREG). The connection device includes two active transistors (N1, P1) of different conductivity connected in series between the supply voltage (VDD) and earth (VSS). The drains of these two active transistors (N1, P1) are connected to each other so as to form an external contact pad (2). The gates of these active transistors are controlled by voltage signals that have the same amplitude (Vesd). The connection device further includes switching means (3) for modifying the control signals (Vesd) applied across the active transistor gates, without exceeding the highest voltage between the supply voltage (VDD) and the internal regulated voltage (VREG).

Abstract: A primary controller of a switching power supply and the switching power supply are provided. The primary controller includes an input voltage detection module which receives a detected signal and generates a detection signal; a controller module which receives a feedback signal and a current sampling signal of the switching power supply, and generates a control signal according to the feedback signal and the current sampling signal; a PWM signal generation module, receive the detection signal and the control signal, generate a PWM signal according to the control signal when the detection signal is the second level, and stop generating the PWM signal when the detection signal is the first level; and a power switch transistor, having a control terminal coupled with an output terminal of the PWM signal generation module.

Abstract: A laser eye surgery system comprises subsystems which communicate with one another through low voltage differential signaling (LVDS). The laser eye surgery system may comprise a first subsystem interface, including an LVDS driver or transmitter coupled to and in communication with an LVDS receiver of a first subsystem of the laser eye surgery system. The first laser eye surgery subsystem itself may comprise an LVDS transmitter coupled to and in communication with an LVDS receiver to return data to the first subsystem. Further laser eye surgery subsystems may also include the same arrangement of drivers and receivers with respective subsystem interfaces. LVDS lowers power consumption and the risk of error in communication between laser eye surgery systems, leading to safer and more reliable surgical procedures performed.

Abstract: A radio frequency switch having a first node, a second node, and a plurality of switch cells that are coupled in series between the first node and the second node is disclosed. Each of the plurality of switch cells is made up of a main field-effect transistor (FET) having a main drain terminal, a main source terminal, a main gate terminal, and a main body terminal. Further included is a first body bias FET having a first drain terminal coupled to the main gate terminal, a first gate terminal coupled to the main drain terminal, a first body terminal coupled to the main body terminal, and a first source terminal, and a second body bias FET having a second drain terminal coupled to the main gate terminal, a second body terminal coupled to the main body terminal, and a second source terminal coupled to the first source terminal.

Abstract: An input-output (I/O) receiver includes a receiving terminal, a first N-type metal-oxide-semiconductor (NMOS) transistor, a reformation circuit, and a compensation unit. The receiving terminal is coupled with an external voltage signal. The first NMOS transistor has a source electrode coupled with the receiving terminal and a gate electrode coupled with a first power supply voltage. The reformation circuit is configured to reform a voltage signal transmitted from a drain electrode of the first NMOS transistor. The compensation unit includes a first PMOS transistor, a second PMOS transistor, and a second NMOS transistor. Moreover, the compensation unit is configured to provide a compensation voltage to a voltage signal at the drain electrode of the first NMOS transistor thereby a maximum level of the voltage signal at the drain electrode of the first NMOS transistor reaches the first power supply voltage.

Abstract: An apparatus is described. The apparatus includes a semiconductor chip. The semiconductor chip includes a memory having multiple storage cells. The storage cells are to receive a supply voltage. The semiconductor chip includes supply voltage retention circuitry. The supply voltage retention circuitry is to determine a level of the supply voltage at which the storage cells are able to retain their respective data. The supply voltage retention circuitry is to receive the supply voltage during a stress mode of the supply voltage retention circuitry. The supply voltage retention circuitry is to more weakly retain its stored information than the storage cells during a measurement mode at which the level is determined.

Abstract: A data transfer circuit includes a first layer for transmitting first bits and a second layer for transmitting second bits. Each of the first layer and the second layer includes: first to mth banks configured to convert a plurality of received digital pixel signals into first to mth analog voltage signals, wherein ‘m’ denotes an integer which is greater than or equal to ‘2’; first to mth samplers configured to convert the first to mth analog voltage signals into first to mth digital transmission signals; and first to mth digital transfer units configured to respectively receive the first to mth digital transmission signals.

Abstract: Disclosed are a high voltage switch circuit and a semiconductor memory device including the same. The high voltage switching circuit includes: a control signal generating circuit configured to supply a supply voltage to an internal node and generate a control signal in response to a first enable signal; a well bias generating circuit configured to apply a well bias to a well of a transistor included in the control signal generating circuit in response to a second enable signal; and a switching circuit configured to switch an input voltage to an output voltage in response to the control signal.

Abstract: Systems, methods, and apparatus for implementing hardware flow control between devices coupled through a serial peripheral interface. A method for transmitting information using a serial peripheral interface includes initiating an exchange of data over one or more data lines of a serial peripheral interface bus by asserting a first voltage state on a slave select line, transmitting data and clock signals over the serial peripheral interface bus while the slave select line remains at the first voltage state, refraining from transmitting data and clock signals over the serial peripheral interface bus when the slave select line transitions to a second first voltage state, receiving data at a slave device into a receive buffer while the slave select line remains at the first voltage state, and asserting the second voltage state on the slave select line when occupancy of the receive buffer reaches or exceeds a threshold occupancy level.

Abstract: The invention provides an inverter. The inverter includes a first converter and a second converter. The first converter is coupled between a supply voltage and an output node of the inverter. The second converter is coupled between the output node of the inverter and a ground voltage. The first converter, the second converter, or both include diode-connected transistors. The propagation delay time of the inverter is substantially a linear function of the temperature of the inverter.

Abstract: Level shifters, memory systems, and level shifting methods are described. According to one arrangement, a level shifter includes an input configured to receive an input signal in a first voltage domain, an output configured to output an output signal from the level shifter in a second voltage domain different than the first voltage domain, a plurality of pull-down devices, and wherein one of the pull-down devices is coupled with the input and the output, a plurality of cross-coupled devices coupled with the pull-down devices and configured to provide transitions in the output signal as a result of transitions in the input signal, a plurality of current limiting devices coupled with the cross-coupled devices and configured to limit a flow of current from a source to the cross-coupled devices, and a plurality of dynamic devices configured to selectively provide charging current from the source to the cross-coupled devices.

Abstract: Exemplary semiconductor devices include eight transistors and two capacitors interconnected in specific configurations. A display device may include a driver circuit having such a semiconductor device. An electronic device may also include such a semiconductor device and an input unit, LED lamp or speaker.

Abstract: A number of load units are connected to receive power from a number of power supply units. A potential load bus is connected to have a voltage level representative of both a total potential power requirement of the number of load units and a total potential power supply capability of the number of power supply units. A first control circuit enables operation of the number of load units when the voltage level on the potential load bus indicates that a sufficient supply of power is available. An actual load bus is connected to have a voltage level representative of both an actual total power consumption of the number of load units and an actual total power supply available from of the number of power supply units. A second control circuit signals an impending loss of sufficient power supply based on the monitored voltage level on the actual load bus.

Abstract: Aspects of this disclosure are directed to level-shifting approaches with communications between respective circuits. As may be implemented in accordance with one or more embodiments characterized herein, a voltage level of communications passed between respective circuits are selectively shifted. Where the respective circuits operate under respective power domains that are shifted in voltage range relative to one another, the voltage level of the communications is shifted. This approach may, for example, facilitate power-savings for stacked circuits in which a low-level voltage of one circuit is provided as a high-level voltage for another circuit. When the respective circuits operate under a common power domain, the communications are passed directly between the respective circuits (e.g., bypassing any level-shifting, and facilitating fast communication).

Abstract: A level shifter circuit is disclosed. A level shifter circuit includes a static pull-down circuit that causes an output node to be pulled low responsive to an input circuit receiving a first logic value on an input node. The input node is coupled to receive a signal from circuitry in a first voltage domain, while the output node is configured to provide a corresponding signal into a second voltage domain. The static pull-down circuit is implemented with a passgate having a pair of transistors coupled in series. The level shifter circuit further includes a dynamic pull-up circuit that, when active, causes the output node to be pulled high responsive to the input circuit receiving a second logic value on the input node. The dynamic pull-up circuit includes third and fourth transistors coupled in series between the output node and a supply voltage node of the second voltage domain.

Abstract: The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output. This decreases the amplitude voltage of a circuit (a shift register circuit, a decoder circuit, or the like) which outputs the signal input to the level shifter. Consequently, power consumption of the circuit can be reduced. Alternatively, a voltage applied to a transistor included in the circuit can be reduced. This can suppress degradation of the transistor or damage to the transistor.

Abstract: A semiconductor system includes a first semiconductor device configured to output command addresses; and a second semiconductor device configured to generate a first control signal including a pulse controlled in its pulse width in synchronization with a toggling time of a bank active signal for selecting a bank to be activated in an active operation in response to the command addresses, a second control signal enabled in response to the bank active signal, and an internal voltage in response to the first and second control signals.

Abstract: A level shifter circuit is provided that uses a boosting circuit. The boosting circuit is configured to improve the operation of the level shifter circuit when the high voltages of voltage domains across the level shifter circuit are widely separated. A circuit apparatus includes a core level shifter circuit that changes a first voltage of an input signal to a second voltage of an output signal. The circuit apparatus further includes a first boosting circuit that is coupled to the core level shifter circuit and generates a first transient voltage applied to the core level shifter circuit when the input signal transitions from a low value to a high value. The circuit apparatus also includes a second boosting circuit that is coupled to the core level shifter circuit and generates a second transient voltage applied to the core level shifter circuit when the input signal transitions from a high value to a low value.

Abstract: An external clock signal having a first frequency is received. A division ratio is automatically determined based at least in part upon a second frequency of an internal clock. The second frequency is greater than the first frequency. A decimation factor is automatically determined based at least in part upon the first frequency of the external clock signal, the second frequency of the internal clock signal, and a predetermined desired sampling frequency. The division ratio is applied to the internal clock signal to reduce the first frequency to a reduced third frequency. The decimation factor is applied to the reduced third frequency to provide the predetermined desired sampling frequency. Data is clocked to a buffer using the predetermined desired sampling frequency.

Abstract: A low-power-consumption semiconductor device or the like is provided. Charge is accumulated in a node connected to a capacitor for a certain period to perform a current-voltage conversion. A gate of a transistor is connected to the node and the potential of one of a source and a drain of the transistor is changed gradually or continuously so that the potential is read when the transistor is turned on. The threshold voltage of the transistor and the capacitance value of the node are measured, so that the current-voltage conversion is performed more precisely.

Abstract: A voltage dropping circuit generating a second power source voltage to output to a second node by dropping a first power source voltage supplied to a first node, includes: an output transistor having a first terminal to which the first power source voltage is supplied and a second terminal connected to the second node turns on or off according to a difference between the second power source voltage and a reference voltage; and a back gate variable diode circuit including a diode-connected transistor connected between the first node and the first terminal and to configured to turn on or off according to a voltage difference between the first and second power sources, wherein the first power source voltage is applied to the back gate of the diode-connected transistor when it is higher than the second power source voltage, and the second power source voltage is applied in other case.

Abstract: An apparatuses and methods for buffering a voltage from a circuit without current drive ability are described. An example apparatus includes a voltage buffer that includes two identical stages. The first stage is configured to receive an input voltage and produce an intermediate voltage as an output. The second stage is configured to receive the intermediate voltage and provide an output voltage that is equal to the input voltage. The voltage buffer may be coupled to a current source. The second stage of the voltage buffer may have current drive ability.

Abstract: Aspects of wide operating range level shifter designs are described. One embodiment includes a level shifter configured to receive an input signal in a first voltage domain and generate an output signal in a second voltage domain, a pulse generator configured to generate a pulse in response to sensing a rise transition on the input signal, and a droop circuit configured to decouple at least a portion of the level shifter from the second voltage domain in response to the pulse. According to one aspect of the embodiments, the pulse can be provided to the droop circuit to decouple at least a portion of the level shifter from the second voltage domain and reduce contention between transistors in the level shifter. Using the concepts described herein, the worst case rise time delay for level shifters can be significantly reduced.

Abstract: The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output. This decreases the amplitude voltage of a circuit (a shift register circuit, a decoder circuit, or the like) which outputs the signal input to the level shifter. Consequently, power consumption of the circuit can be reduced. Alternatively, a voltage applied to a transistor included in the circuit can be reduced. This can suppress degradation of the transistor or damage to the transistor.

Abstract: Certain aspects of the present disclosure provide methods and apparatus (e.g., a level shifter) for buffering an oscillating signal generated by an oscillator. One example apparatus generally includes an amplifier having a first amplification stage configured to amplify the oscillating signal generated by the oscillator and a second amplification stage configured to amplify an inverse of the oscillating signal generated by the oscillator; and a sensing circuit configured to adjust an operational bandwidth of the amplifier based on a frequency of the oscillating signal.

Abstract: This invention discloses a voltage level shifter, which comprises a first P-type metal-oxide-semiconductor (PMOS) transistor having a gate, a source and a bulk coupled to an input terminal, a first positive voltage power supply and a second positive voltage power supply, respectively, and a second PMOS transistor having a source, a drain and a bulk coupled to a third positive voltage power supply, an output node and the second positive voltage power supply, respectively, wherein the first and second PMOS transistors are formed in a single Nwell.

Abstract: The semiconductor device includes a switching arm unit in which first and second wide bandgap semiconductor elements, each having a body diode, are connected in series between a positive line and a negative line; a current detecting unit that detects a current in at least a wide bandgap semiconductor element in which a flyback current flows; and a semiconductor element driving unit that drives the first and second wide bandgap semiconductor elements. When driving one of the wide bandgap semiconductor elements, the semiconductor element driving unit determines, by referring to a fault inhibiting characteristic curve, whether a flyback current detection value of the other wide bandgap semiconductor elements falls within a fault growth region or a fault inhibiting region, and when a result of the determination indicates that the flyback current detection value is within the fault growth region, inhibits a current flowing in the one wide bandgap semiconductor element.

Abstract: The present invention provides a level shift circuit, an array substrate and a display device. The level shift circuit comprising: a first level non-inverting input terminal, a first level inverting input terminal, a second level non-inverting input terminal, a second level inverting input terminal, a level state transferring unit and a second level driving unit; the level state transferring unit receives a first level input through the first level non-inverting input terminal and the first level inverting input terminal, and transfers a high and low state of the input first level to the second level driving unit; the second level driving unit outputs a second level of a corresponding state to the second level non-inverting input terminal and the second level inverting input terminal according to the input high and low state, wherein the first level is not equal to the second level.

Abstract: A substrate bias circuit and method for biasing a substrate are provided. A substrate bias circuit includes a first voltage source, a second voltage source, a diode coupled between the first voltage source and the second voltage source, and a plurality of transistors, each transistor in the plurality of transistors having a substrate terminal. In one example, the first voltage source supplies, via the diode, the substrate terminal of a first transistor of the plurality of transistors during a power-up, and the second voltage source supplies the substrate terminal of the first transistor after the power-up.

Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a first p-type transistor, a second n-type transistor, a third transistor, and a fourth transistor. One of a source and a drain of the third transistor is connected to a wiring supplying first potential, and the other is connected to one of a source and a drain of the first transistor. One of a source and a drain of the second transistor is connected to the other of the source and the drain of the first transistor, and the other is connected to one of a source and a drain of the fourth transistor. The other of the source and the drain of the fourth transistor is connected to a wiring supplying second potential lower than the first potential. An oxide semiconductor material is used in channel formation regions of the third transistor and the fourth transistor.

Abstract: In one embodiment, an integrated circuit has hot-socket circuitry to protect I/O drivers during hot-socket events. The hot-socket circuitry has (i) N-well-to-pad switcher circuitry that ties driver PMOS N-wells to pads when the pad voltages are greater than the power-supply voltage and (ii) N-well-to-power-supply switcher circuitry that ties the driver PMOS N-wells to the power supply when the pad voltages are less than the power-supply voltage. The hot-socket circuitry also has a special PMOS device connected between the pad and a gate of at least one other PMOS device in the N-well-to-power-supply switcher circuitry to turn off the N-well-to-power-supply switcher circuitry quickly whenever the pad voltage is greater than the power-supply voltage. Applying a reduced power-supply voltage level to the gate of the special PMOS device enables the hot-socket circuitry to be implemented without having to use low Vt devices and without having to implement substantially large drive strengths.

Abstract: The present invention proposes a gate driver which simplifies a circuit structure by effectively compounding the pull-down holding circuit and signals to achieve a design for ultra-narrow bezel gate driver. In addition, It effectively lessens voltage offset at the second node and prolongs GOA circuit operating time to prolongs lifetime of the LCD when the seventh transistor of the first pull-down holding circuit adopts equivalent diode connection. At last, it reduces RC delay to efficiently lower power-consumption to more effectively decrease LCD energy-consumption when amount of transistors and signals of the first and the second pull-down holding circuits decreases.

Abstract: A device includes a pull-up circuit, first and second switches, and a feedback circuit. The pull-up circuit has a first terminal electrically coupled to a pad, and a second terminal electrically coupled to a first power node. The first switch has a first terminal electrically coupled to a first control terminal of the pull-up circuit, and a second terminal electrically coupled to a second control terminal of the pull-up circuit. The feedback circuit has a first terminal electrically coupled to the pad, and a feedback terminal. The second switch has a first terminal electrically coupled to the first control terminal of the pull-up circuit, a second terminal electrically coupled to the feedback terminal of the feedback circuit, and a control terminal electrically coupled to a second power node.

Abstract: A display device includes a plurality of pulse output circuits each of which outputs signals to one of the two kinds of scan lines and a plurality of inverted pulse output circuits each of which outputs, to the other of the two kinds of scan lines, inverted or substantially inverted signals of the signals output from the pulse output circuits. Each of the plurality of inverted pulse output circuits operates with at least two kinds of signals used for the operation of the plurality of pulse output circuits. Thus, through current generated in the inverted pulse output circuits can be reduced.

Abstract: A method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (IC) layout, representing a set of photomasks for fabricating an IC having the IC layout such that the IC meets a first specification value. A computer identities a proper subset of a plurality of first devices in the IC layout, such that replacement of the proper subset of the first devices by second devices in a revised IC layout satisfies a second specification value different from the first specification value. At least one layout mask is generated and stored in at least one non-transitory machine readable storage medium, accessible by a tool for forming at least one additional photomask, such that the set of photomasks and the at least one additional photomask are usable to fabricate an IC according to the revised IC layout.

Abstract: A circuit may include an input terminal configured to receive an input signal with a first voltage swing and an output terminal. The circuit may also include a first transistor, a second transistor, a third transistor, and a control circuit. The control circuit may be coupled to the input terminal, a gate terminal of the first transistor, and a gate terminal of the second transistor. The control circuit may be configured to adjust voltages provided to the gate terminals based on the input signal such that the first transistor conducts in response to the input signal being at a first logical level and the second transistor conducts in response to the input signal being at a second logical level to generate an output signal output on the output terminal. The second voltage swing of the output signal may be different from the first voltage swing of the input signal.

Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.

Abstract: A receiving circuit for a core circuit is provided and includes a first receiving-path unit. The first receiving-path unit is capable of receiving an input signal and outputting an output signal to the core circuit according to the input signal. The first receiving-path unit includes an input buffer which is capable of operating in a core power domain of the core circuit and receiving a first clamped signal. When a level of the input signal is substantially equal to or lower than a first predetermined voltage level, the input signal is passed to the input buffer to serve as the first clamped signal, and the input buffer is capable of outputting the output signal in the core power domain according to the first clamped signal. When the level of the input signal is higher than the first predetermined voltage level, the input signal is not passed to the input buffer.

Abstract: A driver circuit includes first and second pluralities of series-connected inverters for pre-driving an input signal to first and second drive transistors, and a plurality of capacitors. The first and second drive transistors coupled to the last inverter of the first and second pluralities of series-connected inverters. Each capacitor of the plurality of capacitors coupled between the output terminals of corresponding inverters of the first and second pluralities of series-connected inverters. In another embodiment, a plurality of discharge circuits is coupled to the first plurality of series-connected inverters. Another embodiment includes a combination of capacitors and discharge circuits coupled to the first plurality of series-connected inverters. The embodiments provide a driver circuit with high frequency voltage regulation.

Abstract: A circuit for providing voltage level shifting in an integrated circuit includes an inverter having an input coupled to receive an input signal having a first voltage level; an output stage having a first transistor coupled in series with a second transistor, and an output node between the first transistor and the second transistor generating an output signal having a second voltage level. A gate of the second transistor is coupled to an output of the inverter. A pull-up transistor is coupled between a reference voltage having the second voltage level and a gate of the first transistor. A switch is coupled between the gate of the first transistor and the gate of the second transistor to control a voltage at the gate of the first transistor. A method of providing voltage level shifting in an integrated circuit is also disclosed.

Abstract: A low-power high-swing current-mode logic (CML) driver circuit includes a first differential-pair and a second differential-pair. The first differential-pair includes first transistors, and is coupled to a first voltage supply that supplies a first voltage. The second differential-pair includes second transistors, and a common node of the second differential-pair is coupled to a second voltage supply. The second voltage supply supplies a second voltage that is higher than the first voltage. Control terminals of the first transistors are coupled to control terminals of the second transistors to form input nodes of the driver circuit.

Abstract: A clock signal generation circuit configured to generate the clock signal having a frequency that is maintained across variations in a number of operating conditions, such as changes in supply voltage, temperature and processing time. In an embodiment, the frequency spread of the generated clock signal of a PVT-compensated CMOS ring oscillator is configured to compensate for variations in the supply voltage, as well as for variations in process and temperature via a process and temperature compensation circuit. The PVT-compensated CMOS ring oscillator includes a regulated voltage supply circuit to generate a supply voltage that is resistant to variations due to changes in the overall supply voltage.

Abstract: A number of load units are connected to receive power from a number of power supply units. A potential load bus is connected to have a voltage level representative of both a total potential power requirement of the number of load units and a total potential power supply capability of the number of power supply units. A first control circuit enables operation of the number of load units when the voltage level on the potential load bus indicates that a sufficient supply of power is available. An actual load bus is connected to have a voltage level representative of both an actual total power consumption of the number of load units and an actual total power supply available from of the number of power supply units. A second control circuit signals an impending loss of sufficient power supply based on the monitored voltage level on the actual load bus.

Abstract: A level shifting circuit that includes a level shifter and a circuit stage. The circuit stage includes a pair of diodes circuits. The circuit stage includes a first output node and a second output node. The first output node is coupled via a current path to a first output of the level shifter and the second output node is coupled to via a current path to a second output of the level shifter. One of the diodes is coupled to the first output node and a power supply terminal. The other diode is coupled to the second output node and the power supply terminal.

Abstract: Described herein is a high-voltage level-shifter (HVLS) that can be used for both NMOS and PMOS bridges, exhibits a higher voltage tolerance for over-clocking than traditional level-shifters, has reduced crowbar current in its input driver, and no contention in its output driver. The HVLS comprises an input driver including a first signal conditioning unit, the input driver operating on a first power supply level and for conditioning an input signal as a first signal in the first signal conditioning unit; and a circuit to receive the first signal and to provide a second signal based at least in part on the first signal, the second signal being level-shifted from the first power supply level to a second power supply level, wherein the second power supply level is higher than the first power supply level.