Abstract: The circuit configuration for converting logic levels has a bipolar input stage and a CMOS output stage. The bipolar input stage is equipped to process ECL and CML logic levels. The CMOS-logic output stage is equipped to supply trailing CMOS gates having CMOS logic levels. A difference amplifier includes bipolar transistors, which are connected to a common emitter current source and to separate collector current sources. An input-output feedback CMOS inverter is connected to one of the collectors, and the output of the inverter is coupled to an output node.

Abstract: When there is a difference in the lengths of the passages among the parallel data wirings or a difference in the load capacitances inclusive of parasitic elements, a difference in the propagation time among the data becomes no longer negligible. At the time of transmitting data at high speeds in a short period, in particular, the setup time for receiving the data and the holding time are no longer maintained, and the data are not normally transmitted. In a data transmitter provided to address this problem, the receiver for receiving parallel data is provided with a simultaneous arrival judging circuit for comparing phases of part or whole bits of the received data, and with a timing adjusting mechanism for adjusting phases among the parallel bits at a point of receiving data in the receiver based on the judged results of the simultaneous arrival judging circuit, so that the data bits arrive simultaneously at the receiver.

Abstract: The invention relates to the interfacing of high speed, low voltage data streams with CMOS circuits and, more specifically, to converting low voltage, differential ECL signals levels to higher voltage levels which are compatible with CMOS circuits while maintaining high speed and sufficient drive capability. This is accomplished by making first stage inverters 5 and 6 as geometrically small as possible subject to the design rules in use to minimize the capacitance at the input of these inverters. The inputs of the first stage inverters are clamped by bias circuits 9/10/11 and 12/13/14 at DC levels so as to provide a narrow range of operation. Additional output inverters 7 and 8 act as buffers to provide the needed capacitive load drive capability.

Abstract: This invention relates to interfacing high speed, low voltage, data streams with CMOS circuits and, more specifically, to converting low voltage, differential, ECL signal levels to higher voltage levels which are compatible with CMOS circuits while maintaining high speed and sufficient drive capability for larger system applications. This is accomplished primarily by making the first stage inverters 5 and 6 as geometrically small as possible and providing additional cross-coupled buffers 7 and 8 capable of driving large capacitive loads.

Abstract: To provide an input circuit of an IC wherein the current flowing towards the input terminal when receiving a LOW level signal can be restricted to minimum, and the input threshold level can be controlled appropriately without degrading transition performance of the input circuit, an input circuit includes: a current control means for controlling a first current to be supplied to a first node according to a second current to be supplied to a second node an input level transfer means for transferring logic of the external logical signal into an intermediate signal whereof potential of a HIGH level is restricted within a power supply voltage; a level shift means for shifting a LOW level of the intermediate signal to substantially the same level of a LOW level of the external logical signal; an inverter for outputting a signal of low output impedance by inverting the shifted intermediate signal; and a transition current generating means for controlling the level shift means to supply a sufficient transition curre

Abstract: An output driver circuit for coupling a logic circuit to load includes an input node, an output node for coupling to the load and a pull down switch which discharges the output node in response to a signal received at the input node. A current sink circuit includes a feeder transistor which provides current to the control terminal of the pull down switch to render the pull down switch conductive when the voltage at the output node exceeds a first threshold value between a logic high and a logic low. The feeder transistor is charged by a first charging path having a first impedance by which it takes a first time period to render the pull down switch conductive, the first impedance providing a low standby current when the voltage at the output node is below about the first value.

Abstract: A small amplitude signal output circuit comprises an output section, for receiving a logic signal to output a small amplitude signal, having first and second transistors connected in series between a first source line and a second source line, and voltage control sections connected between each of the source lines and the output section for reducing the output voltage supplied from the output node, thereby allowing ON-resistance of the transistors of the output section to be smaller. The small ON-resistance of the transistors in turn allows variations in the output voltage of the output circuit caused by variations in the fabrication process to be smaller. The voltage control sections may have a function for reducing variations in the output circuit due to temperature variation.

Abstract: A small amplitude signal output circuit comprises an output section for receiving a logic signal to output a small amplitude signal, a level sense circuit for sensing the rise or fall of an output voltage at an output terminal, and a level control circuit for responding to the output of the level sense circuit to suppress the rise or fall of the output voltage. The output circuit suppresses voltage variations caused by variations in fabrication process of transistors, ambient temperature and source voltage noise.

Abstract: According to the present invention, an input circuit is provided comprising: an input terminal; a first power source terminal; a second power source terminal; a first bipolar transistor; a second bipolar transistor; a first electric current cut off member; a second electric current cut off member; a voltage clamping member; and a buffer. As a result, even when an electric potential greater than that of the power source voltage is applied to the input terminal, regardless of the supply or interruption of the power source voltage, destruction of the internal components is prevented and a steady-state electric current of the power source voltage and/or the input terminal is cut off. Hence, providing a PMOS transistor and NMOS transistor, serves to cut off the electric current routes of power source terminal VDD and the ground terminal.

Abstract: A tristate buffer comprises an output block having a pair of NPN bipolar transistor and nMOS transistor between the source line and ground line and connected to each other at the output terminal of the tristate buffer. The tristate buffer has a base potential control block for discharging the base of the NPN transistor and to couple the base to the output terminal of the tristate buffer during an initial stage of the high-impedance state. After the initial stage of the high-impedance state, the base and output terminal are disconnected from each other. A reverse bias overvoltage occurring in the base-to-emitter P-N junction and a current flow during the high-impedance state are eliminated.

Abstract: A TTL input stage for negative supply voltage systems is described herein which obviates the need for a positive supply and a level shifter. In one embodiment, a first JFET current source, the emitter/collector of a PNP bipolar transistor, and a second JFET current source are connected in series between a control input and a negative supply voltage. The base of the bipolar transistor is connected to ground. At a control input of 2V.sub.be above ground, the PNP transistor has a V.sub.be drop across its emitter/base junction, and each of the identical JFETs has a V.sub.be drop across it. An NPN bipolar transistor, having its base connected to the source of the second JFET and its emitter connected to the negative voltage, is turned on by the V.sub.be drop across the second JFET to provide the output of the TTL input stage. In one embodiment, the TTL input stage is a control circuit for turning an output MOSFET on and off.

Abstract: An emitter-coupled logic to CMOS logic converter includes a first current mirror having a first transistor that has a terminal. The first current mirror is operable to mirror a current in the terminal of the first transistor to produce a mirrored first current. The converter also includes a first current sink operable to generate a first current in the terminal of the first transistor. The converter also includes a second current mirror having a second transistor that has a terminal. The second current mirror is operable to mirror a current in the terminal of the second transistor to produce a mirrored second current. The converter further includes a second current sink operable to generate a second current in the terminal of the second transistor and a differential input pair operable to receive a differential voltage input and direct a current, based on the differential voltage input, to the terminal of the first transistor or the terminal of the second transistor.

Abstract: Several low power, low voltage swing, BiCMOS circuits for used in high speed chip-to-chip communications are described. In particular a BiCMOS low voltage swing transceiver comprising a driver and a receiver with low on-chip power consumption is reported. Operating at 3.3.V, the universal transceiver can drive and receive low voltage swing signals with termination voltages ranging from 5V down to 2V, without using external reference voltages and at frequencies exceeding 1 GHz. On-chip power consumption is much lower than that of known CML/ECL type transceivers having comparable speeds.

Abstract: A chopper comparator is constructed by connecting current control transistors Q.sub.15 to Q.sub.17 comprising p-channel MOSFETs between CMOS inverters 3 to 5 and a power source 7 to supply a power voltage V.sub.DD . A control signal V.sub.C to control a current flowing in the CMOS inverters 3 to 5 is supplied to gates of the current control transistors Q.sub.15 to Q.sub.17. In case of constructing the A/D converter, the chopper comparator is used.

Abstract: A first load 10 is connected between a signal terminal 12 for driving an output transistor 11 and a highest potential VCC. A first switch 7 is connected in parallel with the first load 10. A second switch 8 is connected between the signal terminal 12 and a current source 14. A third switch 9 is connected between the highest potential VCC and the current source 14. The first to third switches are on-off operated according to a CMOS level input to provide an ECL level from an output transistor. The current source 14 includes a bipolar transistor 1 and a resistor 2, thereby occupying only a small area and precluding output fluctuations due to fluctuations in manufacture.

Abstract: A circuit and method for implementing a MOSFET gate driver. Two bipolar NPN transistors (Q1, Q2), constructed to achieve rail-to-rail swings when driving a capacitive load (23) by overlapping their respective emitter regions (13) over their contained contact regions (19) to prolong internal device saturation and resulting turn-off delays, alternately connect the gate drive terminal (31) to either a supply terminal (HVDC) or an output terminal (29). Predrive circuitry for these transistors comprises NMOS transistors (M9, M18, M12 and M13). The NPN transistors are supplemented by a CMOS inverter (PMOS transistor M6 and NMOS transistor M17). A PMOS transistor (M7) provides additional base drive for transistor Q1 when the gate drive node is approaching the supply node. A diode (D2) protects transistor Q1 against base-emitter avalanche and protects transistor M7 from excessive drain-to-source voltages.

Abstract: Low-side driver circuit (200) for data transmission applications includes external connection (202) for connecting and providing drive current to an external physical interface circuit. Sink transistor (210) forms an isolation from the physical interface circuit, and channels low-side drive current to external connection (202). Sink transistor (210) includes base (216), collector (208), and emitter (224). Emitter follower transistor (228) associates with sink transistor (210), and in conjunction with "A" input to the gate of transistor (228), sink transistor (210) controls the state of emitter follower transistor (228). Blocking transistor (206) associates with base (216) of sink transistor (210) to block the base of sink transistor (210) in the off state of sink transistor (210). Pull-down diodes (218) and (220) associate with base (216) of sink transistor (210) to pull down the voltage of the base when sink transistor (210) is in an off state.

Abstract: The invention relates to a "power on demand" control circuit and the application thereof in a BiCMOS bus driver. The basic object resides in the creation of such a circuit with a low power need and a simple structure. This aim is to be solved by the provision of a control loop comprising a diode series circuit arrangement (D1, D2) and a bipolar transistor (Q2) between the collector and the base of the output transistor (Q1), which is of such a size that in the stable L state the base current of the outlet transistor (Q1) is so selected that the L state is maintained.

Abstract: A level shift is provided between a first level and a second level for a first and second compensatory signal. Power supply variations are measured and the levels are compensated for these power supply variations so that the power supply does not affect the first and second levels.

Abstract: A BiCMOS logic circuit having greater drive and speed at low voltage is provided. The logic circuit includes a switching device which allows the pull-down device of the logic circuit to be driven directly by an input signal without first having to switch a MOS device. The switching device conducts current between the input terminal of the logic device and the pull-down device when the output signal equals a certain value.

Abstract: A plurality of high speed differential output drivers are coupled to a reference current generator such that each output driver receives a substantially identical copy of a reference current signal for controlling one or more operational parameters (e.g., the propagation delay or skew) of the output driver. Multiple copies of the reference current signal are generated within the same region of an integrated circuit chip, thereby minimizing any process variations within the chip that might cause variances between the individual copies of the reference current signal. Each differential output driver has a differential pair of transistors that are coupled to ground or supply voltage through a common mode resistor that controls the common mode component of the driver output independent of the voltage swing of the output.

Abstract: A Bi-CMOS circuit includes a first bipolar, a second bipolar transistor and a CMOS control unit for performing switching controls of the first and second bipolar transistors on the basis of an input signal applied to an input terminal and for controlling an output signal output via the output terminal on the basis of the input signal. A turn-OFF unit temporality couples the base of the first bipolar transistor to a low-potential side power supply line on the basis of a current flowing in said control means when the first bipolar transistor is turned OFF, so that the first bipolar transistor can be rapidly turned OFF.

Abstract: An ECL stage has its current consumption adapted to its operation speed. For this purpose, the load resistor and the bias current source are adjustable so that the product of the current value of the source by the resistor value is substantially constant.

Abstract: An improved tri-state output buffer having an emitter-follower output stage clamps the reverse-bias voltage across the base-emitter path of an emitter-follower to limit the output leakage current and thereby extending the operating life of an integrated circuit (IC). A current sensitive voltage device such as a bipolar transistor or diode clamps the reverse-bias voltage of the base-emitter path. Voltage clamping prevents the bipolar transistors from activating while the buffer is disabled. The output leakage current that occurs when the junction is forward biased is minimized. This results in low output load capacitance that improves the propagation delay particularly when multiple buffers are used.

Abstract: A semiconductor integrated circuit memory device has at least two logic blocks, each logic block including at least two logic units and each logic unit having a number of metal oxide semiconductor field effect transistors (MOS FET's) integrated therein. Bipolar transistors for driving the MOS FET's are selectively arranged between the logic blocks and/or the logic units so as to shorten a critical path of a logic block. The memory device may include a word driver circuit having a bipolar transistor connected to MOSFETs in an address decoder and memory cells of the memory device. The memory device may also include a sense circuit having a bipolar transistor for high speed discharge of a bit line, as well as an output buffer including a bipolar transistor for reducing signal transmission delays in driving a bus.

Abstract: A current switch apparatus includes a bipolar transistor controlled by a reference voltage, a MOS transistor controlled by a logic signal, and a constant current source connected to the bipolar transistor and the MOS transistor.

Abstract: The invention provides a BiCMOS logic gate circuitry comprising: input and output terminals: an output driving section including two bipolar transistors in the form of totem pole connection between a high voltage line and a low voltage line in which an intermediate point between the two bipolar transistors is connected to the output terminal; a base driving section including a plurality of MOS transistors and being connected to an input terminal for receiving an input signal and connected to bases of the bipolar transistors; and a base clamping section including at least one clamping circuit being connected to at least one of the bipolar transistors through its base for restricting a base potential of the at least one bipolar transistor in the vicinity of the same potential as a base-emitter forward bias at which the bipolar transistor turns ON so as to reduce the necessary time for charging a parasitic capacitance of the base of the at least one bipolar transistor.

Abstract: A bus driver circuit having a driver input (16) for the reception of a data signal and a driver output (20) for the application of the output voltage of a voltage source (Vcc) to a bus core (10) in a manner dependent on the presence of a data signal at the driver input (16). It possesses a first controllable switch (A) placed between the voltage source (Vcc) and the driver output (20) and a control circuit loop (B), which on the application of the data signal to the driver input (16) is able to be placed in an active state by its producing a drive signal putting the controllable switch (A) in a conducting state. A second controllable switch (C) is between the control circuit loop (B) and the driver input (16). A comparator (D) compares the voltage at the driver output (20) with a reference voltage (V.sub.

Abstract: Architecture for a programmable logic device is described which can operate at substantially faster clock rates than present programmable logic devices. The PLD uses BiCMOS circuit elements to make use of the speed advantages of bipolar technology while also enjoying the limited power consumption of CMOS technology.

Abstract: The device has, on a single substrate, plural internal circuits, plural input circuits for receiving external input signals and outputting the same to the internal circuit, and plural output circuits for receiving signals outputted from the internal circuits and externally outputting the same, in which at least one of the circuits includes a totem-pole output stage of a first NPN bipolar transistor, on the power supply terminal side, and a second NPN bipolar transistor, on the ground side; a first differentiator circuit for providing pulsing action to the base of the first NPN transistor; a pair of series-connected PMOS transistors for controllably driving the second NPN transistor; and feedback MOS transistors for quickening turn-off of the output stage transistors. The circuit can be effected with a second differentiator circuit in place of the series-connected pair of PMOS transistors.

Abstract: A BiNMOS inverter and a BiCMOS inverter are utilized. The BiNMOS inverter uses first and second power sources. A potential of the second power source is greater than that of the first power source. The BiNMOS has a first bipolar transistor whose collector being connected to the first power source and whose emitter being connected to an output node, and a first P-type field effect transistor group having at least one P-type field effect transistor through which a drain-source current channel consists of the base of the first bipolar transistor and the second power source based on an input signal transmitted to at lease one input node.

Abstract: The present invention provides BICMOS level shifter having pull-up and/or pull-down transistors at pull-up and/or pull-down portions, which perform a switching operation in response to a reference signal of a stable voltage level, and a BICMOS data output buffer employing the BICMOS level shifters as respective pull-up and pull-down control circuits. Thereby, it is possible to attain low power consumption, high drive capability and high speed operation by bipolar transistors and is also possible to cope with unstable signals.

Abstract: A BiCMOS power driver circuit for interfacing to a bus comprises circuitry for channelling current from a power source to the base of a bipolar device to pull the output all the way down to within a bipolar V.sub.SAT voltage drop of ground, and then uses feedback to turn-off the pull-down circuit to conserve power. A similar circuit functions to provide Incident Wave Switching and Glitch Suppression by monitoring the voltage level at the output and sinking current as necessary to maintain a low logic level.

Abstract: The present invention relates to an input buffer used in semiconductor memory devices and more particularly to an input buffer capable of operating at a high speed by using a BiCMOS (bi-complementary metal oxide semiconductor) circuit.

Abstract: The logic of an intermediate signal (Y.sub.1) goes high when an input signal (CI) makes an "L" to "H" transition, and then a transistor (Q.sub.1) turns on and a transistor (Q.sub.2) turns off. The input signal (CI) at a potential corresponding to the logic "H" at a CMOS level has been applied to the gate of an NMOS transisitor (N.sub.1), and the NMOS transistor (N.sub.1) turns on rapidly. At this time, only current flowing through the base of an output transistor (Q.sub.0) flows through parallel connection of a resistor (R.sub.2) and an on-resistance of the NMOS transistor (N.sub.1). Since the NMOS transistor (N.sub.1) is on, the base potential of the output transistor (Q.sub.0) is raised if the resistor (R.sub.2) has a high resistance, and current fed from the output transistor (Q.sub.0) increases, thereby raising the emitter potential of the output transistor (Q.sub.0). Then the logic of an output signal (EO) goes high. Power consumption of an output buffer circuit is reduced.

Abstract: In a push-pull type logic apparatus including a push-pull buffer formed by two bipolar transistors, a control circuit for turning ON one of the bipolar transistors and turning OFF the other, and a voltage clamp circuit for clamping the voltage of the base of at least one of the bipolar transistors, a clamp releasing circuit is provided for releasing the clamp operation of the voltage clamp circuit when the corresponding bipolar transistor is turned ON. Also, a MOS transistor is connected between the collector and emitter of the corresponding bipolar transistor and is turned ON when the corresponding bipolar transistor is turned ON.

Abstract: A 3 state BiCMOS output buffer (100) with power down capability has been provided. The buffer includes an input stage (102), responsive to an input signal, an output coupled to both a pull-up driver (114), and an output pull-down driver (116) wherein the drivers provide an output signal at an output of the buffer in response to the input signal. Additionally, the buffer includes a power down sense circuit (108), coupled to a power supply node (118), for turning off an output pull-up transistor (214) when the power supply node is powered down and thus eliminating leakage paths within the buffer. The buffer also includes a noise limiting circuit (112) for slowing down a high to low transition at the output of the buffer thereby reducing the switching noise of the buffer while not affecting the overall speed of the buffer.

Abstract: A signal level converter is disclosed, for converting a signal having a first logic voltage swing characteristic to a signal having a second voltage swing characteristic. The converter comprises a level converting section and a differential circuit coupled thereto. The level converting section converts the supplied signal at the first logic voltage swing to an intermediate signal at a logic voltage swing different from the first voltage swing. The differential circuit 3, being supplied with the intermediate signal, produces an output signal at the second voltage swing level that corresponds to the potential difference between a high and low potential power supplies.

Abstract: A BiCMOS line driver that incorporates a fully-powered, zero- static power pull-down driver with a standard BiCMOS pullup in a novel parallel input signal path construction having substantially equal propagation delays to create a complementary signal driver with very high speed and extremely low skew in propagation.

Abstract: A BICMOS output buffer circuit (20) has a voltage converter (21), a reference voltage circuit (28), a driver circuit (24), and a clamping circuit (40). The reference voltage circuit (28) receives a regulated voltage and provides a reference voltage having a low voltage level and a high voltage level. The low voltage level and the high voltage level control the logic high voltage of an output data signal. During a transition from a logic low voltage to a logic high voltage of the output data signal, the output data signal is allowed to overshoot the low voltage level. After the transition is complete, the output data signal settles at the high voltage level. This limits the amount of overshoot of the output data signal. The clamping circuit (40) dampens the oscillations of the output signal.

Abstract: A programmable logic device includes a plurality of logic cells in which logic functions are performed, a plurality of input lines for supplying signals to be processed by the logic cells, a plurality of output lines for receiving signals that have been processed by the logic cells, and a plurality of repeater circuits combining bipolar and CMOS transistor technologies for transferring data from one point in the PLD to another point. Unidirectional repeater circuits transfer data from a first data bus in the PLD to a second data bus in the PLD. Bidirectional repeater circuits maintain signal integrity by transferring data along the length of a single PLD data bus. The bipolar technology in the repeater circuits provides superior speed in data transfer, while the CMOS technology limits power consumption of the repeater circuits.

Abstract: A bi-CMOS circuit has an emitter-coupled logic circuit responsive to an input signal for producing a logic signal and the complementary logic signal, an emitter follower responsive to the logic signal for changing the voltage level at the emitter node thereof and a switching circuit coupled between the emitter follower and a negative power voltage line and responsive to the complementary logic signal for selectively coupling the emitter node and the negative power voltage line with an output node of the bi-CMOS circuit so that through-current does not flow through the switching circuit.

Abstract: A novel, high-performance BiCMOS Output Driver. The Output Driver comprises a first pull-up means for pulling high the output of the Output Driver and a pull-down means for pulling low the output of the Output Driver. The first pull-up means includes a bipolar transistor. Coupled in parallel with the first pull-up means is a MOS transistor wherein the gate of the MOS transistor is electrically isolated from the base of the bipolar transistor.

Abstract: The current mode bus driver which is disclosed couples input digital signals to a bus which is normally biased with a voltage difference representing one binary type. The current mode bus driver responds to input digital signals of the other binary type by connecting a current source to one lead of the bus and a current sink to the other lead of the bus, thereby driving the bus to a voltage difference which represents the other binary type. In response to input digital signals of the first-mentioned binary type, the bus driver isolates the current source and current sink from the bus and connects the current source directly to the current sink. The selective switching is performed by n-channel MOSFETs which are driven by the input digital signals through unique buffer driver circuits employing a CMOS inverter, an n-channel MOSFET and an NPN transistor. A combination of MOSFETs and NPN transistors provide a current source and sink that permit operation of the bus at very low voltage levels.

Abstract: A tri-state driver circuit is disclosed which provides rail-to-rail output swings and does not consume a significant amount of d.c. power.

Abstract: For increasing an operation speed of a logic circuit in a case where an output level is shifted from a high level to a low level, a control circuit is made of a combination of a first control transistor and a second control transistor. An input circuit has a local terminal and produces a local signal in response to an input signal to supply the local signal to the local terminal. An output circuit has an output terminal and produces an output signal in response to the input and the local signals to supply the output signal to the output terminal. The first control transistor is connected between the local terminal and the second control transistor and has a first transistor control terminal which is supplied with the output signal for controlling operation of the first control transistor.

Abstract: An ECL output buffer circuit is constituted by an output buffer circuit main portion and its control circuit. In the output buffer circuit main portion, an output from a differential switch is input to the base of a bipolar transistor (emitter follower). The emitter of the bipolar transistor is connected to an output terminal. A ground potential is applied to the collector of the bipolar transistor. One end of the channel conductive path of a MOS transistor is connected to the base of the bipolar transistor. The other end of the channel conductive path is connected to a power-supply terminal via a constant-current source. The control circuit controls the ON/OFF operation of the MOS transistor and the output level of the bipolar transistor. When the output buffer circuit main portion is to be set in a standby state, the control circuit performs control to set the MOS transistor in an ON state and set the output of the bipolar transistor at low level.

Abstract: An ECL-to-BiCMOS/CMOS translator for translating a pair of differential ECL level signals into a BiCMOS/CMOS level signal is disclosed. The translator includes an output stage having an output node and a first output switching means for coupling the output node to a first voltage supply and a second output switching means for coupling the output node to a second voltage supply. A first input stage activates the first output switching means of the output stage in response to one of the differential ECL signals, and a second input stage activates the second output switching means of the output stage in response to the other differential ECL signal. The first input stage includes a first input switching means for coupling a first resistive element between the first voltage supply and the output node of the output stage, and the second input stage includes a second input switching means for coupling a second resistive element between the first voltage supply and the second voltage supply.

Abstract: The output signal and control signal from an internal circuit are supplied to a control circuit via an output signal line and a control signal line. The output signal from the control circuit is supplied to a first and second independent output buffer sections via control circuit output signal lines, respectively. The outputs of the first and second output buffer sections are selectively supplied from an output terminal to an external circuit via an output signal line. With this invention, it is possible to selectively use the output buffer sections having an ability according to use. Another semiconductor integrated circuit device comprises an internal circuit, a plurality of output buffers, a control circuit for selectively actuating the output buffers, and a sequential select circuit for sequentially selecting the plurality of output buffers.

Abstract: A row select circuit for semiconductor memories is disclosed. The row select circuit includes a decoder portion and a driver portion. The decoder potion of the row select circuit includes a plurality of decoder circuits, each servicing a multiplicity of rows. Two levels of decoding are used to select a row. First, one of the plurality of decoder circuits is selected. Second, a predecoder is provided for simultaneously selecting one of the multiplicity of rows serviced by the selected decoder circuit. A single current source is used to service the multiplicity of rows associated with a particular decoder. The driver portion of the circuit includes a driver circuit for each row. Each driver includes an inverter stage, a driver stage, a clamp and a voltage reference circuit. For a selected row, the driver circuit provides ultra-fast access time. For the deselected rows, the driver circuit consumes minimal power.