Abstract: A method and implementing structures for a domino block circuit configuration includes a plurality of domino logic blocks including inverter circuits to provide inverted signals which are needed for a comprehensive logic analysis and processing. A plurality of clocking signals are applied at various clocking inputs throughout the circuit. The clocking signals are timed relative to each other in a timing sequence to assure that the logic circuit evaluations occur only after relevant data and switching signals have stabilized.

Abstract: A system and method for transferring data between alternately evaluated first and second logic blocks of a dynamic logic pipeline. Associated with the system and method is a transparent data-triggered pipeline latch for controlling data flow between the first and second logic blocks. During an evaluation period accorded the first logic block, data existing at the logic block's data inputs is evaluated. Substantially simultaneously, the data-triggered latch is reset. As valid data is output from the first logic block, the latch is triggered. Immediately after the latch has been triggered, and before a clock-triggered evaluation period is accorded the second logic block, the data stored in the latch is output to the second logic block. Propagation of the early arriving data may be halted by ANDing the early arriving data signals with clocked signals which remain invalid. The invalid signals may comprise clock or data signals.

Abstract: A non-blocking multiple-phase clocking system for use with dynamic logic provides clock phases with overlapping evaluation phases to a circuit including a several cascaded dynamic logic gates. The circuit also includes a first flip-flop that is coupled to provide input signal(s) to the first dynamic logic gate of the cascade and a second flip-flop that is coupled to receive output signal(s) from the last dynamic logic gate of the cascade. Through the use of the overlapping evaluation phases and proper assignment of the clock signals to the dynamic logic gates, the output signal(s) generated by the dynamic logic gates receiving a particular clock phase are used as input signals to the dynamic logic gates receiving the next clock phase. Because of the overlapping of the clock phases, no latch is used. The clock phases are assigned to a particular dynamic logic gate so that the this dynamic logic gate enters the evaluation phase before the input signal(s) to the particular dynamic logic gate arrives (i.e.

Abstract: Data are transmitted from a control device through an interface cable to a set of driver devices in synchronization with an external clock signal, or a complementary pair of external clock signals. The signal line or lines carrying the external clock signal or signals are terminated at both ends by resistors with resistance values matching the characteristic impedance of the interface cable. Each driver device has a comparator that compares the external clock signal with a regulated reference voltage, or compares the two complementary external clock signals with each other, and thereby generates an internal clock signal. The driver devices receive the data in synchronization with these internal clock signals.

Abstract: A data transmission method exchanges data between at least first and second electronic devices which are coupled via a plurality of bus lines, where each of the bus lines is terminated via a terminating resistor having one end coupled to a bus line and another end applied with a terminating voltage. The data transmission method includes the steps of (a) setting a high logic level of data to a voltage higher than the terminating voltage and setting a low logic level of the data to a voltage lower than the terminating voltage, and (b) continuously outputting the data from the first electronic device to at least one bus line at a timing determined by a first clock signal by alternately repeating a state where the data is output to the one bus line and a state where an impedance between the first electronic device and the one bus line is set to a high impedance.

Abstract: A digital input/output interface for use with two digital circuits connected by a transmission line having a characteristic impedance Z.sub.0 includes a current driver in one of the digital circuits and a current receiver in the other digital circuit. The current driver is configured to generate a current in the transmission line when a digital signal is applied to the current driver. The current receiver includes a current conversion element connected to the transmission line at an input node through an input impedance Z.sub.in and adapted to convert the current in the transmission line into an output voltage, and an active termination element configured to actively adjust the input impedance Z.sub.in to match the characteristic impedance Z.sub.0 of the transmission line. An impedance transforming receiver for use with a transmission line having a small characteristic impedance Z.sub.

Abstract: A phase detection signal is generated with a phase detection logic pipeline and its associated tapped pipeline signal combinational logic circuit. The phase detection logic pipeline generates phase detection logic pipeline output signals from a first input clock signal and a second input clock signal. The first input clock signal is applied to a first flip-flop of a set of serially connected flip-flops to generate a pipeline signal. The pipeline signal is driven through the set of serially connected flip-flops by the second clock input signal. Logic pipeline output nodes connected between the serially connected flip-flops carry the phase detection logic pipeline output signals. The phase detection logic pipeline output signals are applied to the tapped pipeline signal combinational logic circuit, which logically combines the signals to generate the phase detection signal.

Abstract: An electronic circuit has a plurality of nodes at which a plurality of clock signals are present in operational use. The clock signals should have a pre-determined timing relationship amongst themselves. The circuit includes logic circuitry having inputs connected to the nodes and having an output to provide a pulse train. Any discrepancy between the actual and ideal pulse trains indicates a fault.

Abstract: A dynamic switching circuit for use in a domino circuit array is disclosed. The dynamic switching circuit includes a charge-saving transistor for preventing charge stored on the dynamic circuit's output node from discharging to ground. The charge stored on the output node is then fed back to a precharge control transistor to charge the dynamic node during the subsequent precharge/evaluate cycle.

Abstract: An apparatus and method is provided for precharging a conductor within a bus containing a plurality of conductors. The apparatus comprises a precharge circuit which drives an intermediate voltage between VDD and ground upon respective conductors. The precharge driver maintains the intermediate voltage within a range between a first voltage level and a second voltage level, the second voltage level being higher in magnitude than the first voltage level. The precharge voltage defined within an intermediate voltage range is chosen to consume minimal power within the precharge driver. An isolation device can be provided on each conductor for isolating the intermediate, precharged value from a receiver circuit input so as to minimize power consumption of the overall circuit. Precharging to an intermediate value causes logic-driven transitions within the bus to occur at a faster frequency than if the bus were precharged to full rail.

Abstract: An improved timer oscillation circuit capable of synchronizing an oscillation frequency, which is determined by a time constant of a resistance and a capacitance, to a clock signal, which includes a first voltage comparator, controlled by a clock signal, for charging a first voltage on a second capacitance and for outputting a result obtained by comparing the charged voltage on the second capacitance and a voltage from the first capacitance; and a second voltage comparator, controlled by the clock signal, for charging a voltage outputted from the first capacitance on a third capacitance and for outputting a result by comparing the charged voltage and an electric potential of the second voltage, so that it can be advantageously adopted to a digital circuit by outputting an oscillation signal having a cycle determined by a time constant of a resistance and a capacitance and which is synchronized to a clock signal.

Abstract: A synchronous semiconductor device includes an asynchronous circuit receiving a sequence of data signals supplied in synchronous with a first clock signal and outputting a sequence of resultant data signals based on the sequence of data signals, an output circuit clock generating circuit for generating second and third clock signals having phases inverse to each other from the first clock signal, and an output synchronizing circuit for outputting the sequence of resultant data signals in synchronous with the first clock signal using the second and third clock signals. The output circuit clock generating circuit includes a frequency dividing circuit for dividing the first clock signal in frequency such that the second and third clock signals have a frequency twice of that of the first clock signal and phases inverse to each other.

Abstract: A level converting circuit for an input clock signal having a relatively low amplitude comprising a level converting circuit for converting the input clock signal to an output clock signal having a relatively high amplitude, the level converting circuit having an input transistor which has a predetermined threshold voltage, and detecting/offsetting circuit for detecting the threshold voltage of the input transistor and adding an offset voltage in response to the detected threshold voltage to the input clock signal and then for providing the offset input clock signal to the level converting circuit. The novel setup performs clock interfacing of a thin-film transistor integrated circuit device represented by an active-matrix liquid crystal display device at a relatively high speed at a low voltage below 3 V for example.

Abstract: A domino logic circuit includes an evaluation circuit for receiving input signals and performing a logic operation on the input signals, a passgate circuit for controlling the transmission of signals to an output circuit and a feedback latch circuit for holding the output of the evaluation circuit for a predetermined portion of a clock cycle. The output circuit may also include a pair of control transistors to allow the output latching circuit to be turned off during the evaluate portion of the clock cycle thus improving the speed of the domino logic circuit. During the first half of the reset portion of each cycle, the output latching circuit is active and allows the circuit to retain its output state. During the time the passgates are turned off, the evaluate circuit is disconnected and may begin resetting. During the second half of the reset portion of the clocking signal, the passgates open, which allows the output stage to be reset.

Abstract: A dynamic clocked inverter latch with reduced charge leakage includes a first node biasing circuit with a P-MOSFET and an N-MOSFET totem-pole-coupled between VDD and an output node, and a second node biasing circuit with another N-MOSFET and another P-MOSFET totem-pole-coupled between the output node and VSS. The first P-MOSFET receives an input data signal and the first N-MOSFET receives a clock signal and in accordance therewith together cause the output node to charge to a charged state having a charge voltage associated therewith. The second N-MOSFET also receives the input data signal while the second P-MOSFET receives the inverse of the clock signal and in accordance therewith together cause the output node to discharge to a discharged state having a discharge voltage associated therewith.

Abstract: The present invention relates to an implementation of adiabatic circuitry using a pipeline structure which allows for simultaneous evaluation of cascaded functions, which does not require each logic function to be implemented in dual complimentary circuitry, which does not require reversible logic functions, which does not require the use of diodes to insure adiabatic current flow, and which can be implemented using MOS technology. A significant feature of the present invention relates to use of a six-phase clock cycle associated with six phases of circuit operation including, in order, a precharge phase, a precharge disable phase, an evaluate phase, a hold phase, a precharge enable phase and a guard phase. Another significant feature of the present invention relates to simultaneous evaluation of cascaded logic functions during a single phase of operation.

Abstract: The programmable logic device (PLD) of this invention includes two or more programmable logic blocks interconnected by a programmable switch matrix that includes a programmable input switch matrix (input switch matrix) and a programmable centralized switch matrix (centralized switch matrix). Each programmable logic block receives input signals only from the centralized switch matrix. The output signals from a programmable logic block are coupled to a plurality of input/output (I/O) pins by an output switch matrix. The output signals from the programmable logic block are also fed directly to the programmable input switch matrix. In addition, an input macrocell couples the signal on an I/O pin driving the input macrocell, i.e., the associated I/O pin, to the programmable input switch matrix. Each programmable logic block includes a programmable logic array, a programmable logic allocator, and programmable logic macrocells. The PLD includes a block clock generation circuit.

Abstract: A synchronization mechanism for synchronizing an outside clock with a delayed inside clock is provided. The delayed inside clock is distributed across a network of clock lines within the integrated circuit to deskew the clock signal at the supply points. Although the inside clock signal is deskewed, it is nevertheless delayed compared to an input clock signal provided by a pad of the integrated circuit. A distribution line provided on the periphery of the integrated circuit supplies an outside clock signal that is not substantially delayed compared to the input clock signal at the IC's pad. The synchronization mechanism provides synchronization between the outside clock, as received by an input/output block, and the inside clock. The synchronization is required because configurable logic blocks (CLBs) of the IC are typically referenced by the delayed inside clock.

Abstract: A logic family employing a plurality of two-terminal chalcogenide switches as logic gates therein. Preferably the two-terminal chalcogenide switches are chalcogenide threshold switches. The logic can employ multi-phase clocking such as four-phase clocking.

Abstract: A digital circuit comprising a pair of D Flip-Flops which synchronize an oming NRZ.sub.-- L serial data stream to an external ten megahertz clock signal. The combination of a third D Flip-Flop and an EXCLUSIVE-NOR gate generates a clear pulse whenever a change of state occurs within the synchronized serial data stream. This clear pulse is supplied to a ten state state machine resetting the state machine to state S0. When the state machine transition to state S4 the state machine generates an enable signal which is supplied to a toggle Flip-Flop enabling the Flip-Flop allowing the Flip-Flop to change state. The ten megahertz clock signal then clocks the toggle Flip-Flop causing the Flip-Flop to change state. At state S9 the state machine again provides an enable signal to the toggle Flip-Flop enabling the toggle Flip-Flop which allows the ten megahertz clock signal to change the state of the output of the toggle Flip-Flop.

Abstract: An energy saving clock signal generator is disclosed including a source of multi-phase waveform signals, a shift register, and a matrix switch. The waveform source provide four, six or more waveform signals to the shift register and the matrix switch. A number of progressive pulses N.sub.pp which are an integer multiple of the number of waveform signals are applied from the shift register to the matrix switch. The matrix switch responds to the waveform signals and the progressive pulse signals to produce a number of output clock signals which may be used to drive adiabatic logic circuits.

Abstract: A digital dynamic circuit is presented which effectively extends the percentage of each clock cycle available for logical operations. The circuit uses a two-phase overlapping clocking design which results in the circuit (1) having only a single latch delay, (2) being insensitive to mid-cycle clock jitter, and (3) being insensitive to the discrete nature of gate delays. Thus, the circuit can better utilize the time available to perform logic.

Abstract: A memory includes a memory array and a decoder. The memory array includes a plurality of memory locations and the decoder is coupled to receive an address for decoding the address to generate a select signal for selecting one of the plurality of memory locations in the memory array for a memory operation. The memory further includes circuitry coupled to the decoder for delaying the select signal for a first predetermined delay time to generate a delayed select signal and for selectively applying one of the select signal and the delayed select signal to the memory array. The circuitry applies the delayed select signal to the memory array during the memory operation before the select signal is to be deasserted such that address hold time of the memory operation is decreased without affecting the memory operation.

Abstract: A dynamic clock switching circuit in which a multiplexer (MUX) is connected to clock A and clock B. MUX control lines are encoded to signal clock A or clock B. A MUX control change detector is connected to the multiplexer and to the MUX control lines. A MUX control change detector decodes the MUX control lines and asserts a MUX change signal upon a condition that a change from one clock to another is signaled. A Hold Sync flip-flop is connected to a hold output of a Hold Start flip-flop. The Hold Sync flip-flop is connected to and clocked by the clock A. A Hold Disable flip-flop is connected to an OK to change output of the Hold Sync flip-flop. The Hold Disable flip-flop is connected to and clocked by clock A. A Clock Sync flip-flop is connected to a hold disable output of the Hold Disable flip-flop. A reset input of the Hold Start flip-flop is connected to a clock sync output of the Clock Sync flip-flop. An AND is connected to the hold output and to the hold disable output.

Abstract: An adiabatic dynamic non-inverter circuit is a mechanism by which a logic level signal and its inverse are simultaneously available in dynamic logic circuitry without significant power dissipation. The principles of this non-inverter circuit are used to create an exclusive-or gate which also does not dissipate significant power. Both of these circuits employ simplified circuit topologies.

Abstract: A clock generator circuit for producing a clock signal while drawing reduced current drain is disclosed. The clock generator circuit includes a crystal oscillator which produces a periodic signal having a relatively small voltage swing, controlled by one or more reference voltages; the reference voltages are preferably produced by a sub-threshold biased voltage reference circuit. The small signal output of the crystal oscillator is applied to the first of a series of frequency divider stages, prior to amplification by a level shift circuit. Each divider stage includes a current switch which switches the current drawn through current divider legs to produce output signals to latches in the divider stage. Each divider stage also includes one or more current source switched latches, each controlled by current sources that are switched by the current switch.

Abstract: A semiconductor integrated circuit has a clock input buffer, a set of clock drivers, an input buffer, an input latch, an output latch, and a three-state buffer. The clock input buffer produces a first intermediate clock signal in phase with an external clock signal and a second intermediate clock signal out of phase with the external clock signal. With the first intermediate clock signal applied, the set of clock drivers produce non-overlapping two internal clock signals, namely, a first internal clock signal in phase with the external clock signal and a second internal clock signal out of phase with the external clock signal. The input latch is controlled by either the first internal clock signal or the second internal clock signal and latches an output of the input buffer connected to an input/output terminal. The output latch is controlled by the second intermediate clock signal and the latch control signal and latches a signal to be outputted.

Abstract: A state machine is configured with a phase-locked loop clock signal generator which can operate at a rate faster than an externally generated reference clock signal applied to the phase-locked loop. The output of the phase-locked loop is used to trigger registers coupled to the state machine at a selected rate to enable signals at output terminals of the state machine to be updated at a rate different than the rate of the externally generated reference clock signal.