Abstract: A multiplexor generating a glitch free output. A slower clock signal and sleep clock signal are respectively synchronized with positive and negative edges of the faster clock signal. The sleep signal is further synchronized with a negative edge of the slower clock signal and provided to an AND gate gating the slower clock signal based on the value of a select signal formed by the synchronized sleep signal. The slower clock signal is delayed by a number of faster clock cycles equal to the time taken by the select signal to be received at the AND gate after the sleep signal is synchronized to the slower clock signal. In an alternative embodiment, a signal control block ensures that the 0 to 1 transition on one of the select signals follows the 1 to 0 transition on another select signal when the value of the sleep signal changes. In addition, each select signal is synchronized with a negative edge of the corresponding clock signal selected.

Abstract: A method and apparatus for evaluating logical inputs electronically using electronic logic circuits in monotonic dynamic-static pseudo-NMOS configurations. The apparatus includes alternating dynamic and static circuit portions adapted to transition monotonically in response to a common clock (or complemented clock) signal. The circuit portions include pseudo-NMOS configured switching circuits implementing logical functions.

Abstract: In a glitch free clock multiplexer circuit and a method thereof, the glitch free clock multiplexer circuit includes a delay unit for receiving asynchronous clock signals (Clock A, Clock B) and an external selection signal (Sel) and outputting a delay signal by delaying a clock signal selected by the external selection signal (Sel) for a certain clock cycle, a state region transition generating unit for comparing the delay signal with a count value provided from a user, outputting a first control signal (Sel_clock) according to a comparison value and a second control signal (enable) for controlling the first control signal in a logic low state, and a glitch removal unit for outputting a clock output signal (Clock_out) by performing an AND operation of a temporary clock signal (Temp_clock) selected by the first control signal and a third control signal generated by delaying the second control signal (enable) for a certain clock cycle.

Abstract: A method for improving the speed of conventional CMOS logic families is disclosed. When applied to static CMOS, OPL retains the restoring character of the logic family, including its high noise margins. Speedups of 2× to 3× over (optimized) conventional static CMOS are demonstrated for a variety of circuits, ranging from chains of gates, to datapath circuits, and to random logic benchmarks. Such speedups are obtained using identical netlists without remapping. When applied to pseudo-nMOS and dynamic families, in combination with remapping to wide-input NORs, OPL yields speedups of 4× to 5× over static CMOS. Since OPL applied to static CMOS is faster than conventional domino logic, and since it has higher noise margins than domino logic, we believe it will scale much better than domino with future processing technologies.

Abstract: A circuit including a clock signal input to receive a clock signal, at least one data signal input to receive at least one data signal, and a multiple input conditional inverter to receive the clock signal and the data signal, and to generate a dynamic output. The circuit also includes a conditional keeper circuit to charge a dynamic output node when the clock is evaluating and the dynamic output is high.

Abstract: A Self-Timed CMOS Static Circuit Technique has been invented that provides full handshaking to the source circuits; prevention of input data loss by virtue off interlocking both internal and incoming signals; full handshaking between the circuit and sink self-timed circuitry; prevention of lost access operation information by virtue of an internal lock-out for the output data information; and plug-in compatibility for some classes of dynamic self-timed systems. The net result of the overall system is that static CMOS circuits can now be used to generate a self-timed system. This is in contrast to existing self-timed systems that rely on dynamic circuits. Thus, the qualities of the static circuitry can be preserved and utilized to their fullest advantage.

Abstract: A system of individually adjusting noise immunity of each input of a dynamic circuit including parallel or series-parallel pull-down network comprises identifying precharge nodes of the dynamic circuit requiring a reduction of noise. Then further identifying NMOS transistor drains connected to the respective precharge nodes, then creating a pull-up network of PMOS transistors for the precharge nodes, respectively. After creating a pull-up network of PMOS transistors, the system further includes arranging the order of the PMOS transistors corresponding to the respective precharge nodes to improve the noise immunity and performance of the dynamic circuit. After completing the arranging of the order of the PMOS transistors, the system can further include sizing the PMOS transistors to achieve the required reduction of noise for the precharge nodes, respectively.

Abstract: In many electronic systems, it is common to communicate data from a transmitter in one device to a receiver in another. Accurate communications requires use of several matched clock signals. Mismatches in these clock signals cause transmitters to add “jitter” to transmitted data or receivers to be more intolerant of jitter in received signals, increasing the chances of mis-interpreting the data. Accordingly, the inventors devised an exemplary clock-distribution method which entails generating a base set of matched clock signals, deriving at least two separate sets of matched clock signals from the base set, and distributing one of the sets of clock signals to a set of matched components in a circuit and the other set of matched clock signals to a different set of components in the same circuit. The clock signals driving the matched components are isolated from mismatched aspects of the other components, and thus exhibit better matching.

Abstract: The present invention includes a logic circuit block operated in synchronism with a clock signal, power supply switches, and a power supply switch control circuit for switch-controlling the power supply switches so as to provide an operation period shorter than the cycle of the clock signal. When the logic circuit block activated in synchronism with a clock signal has a frequency lower than a clock signal frequency, the logic circuit block does not develop a malfunction if capable of operation for each cycle of the clock signal at least only for a time interval defined by the clock signal frequency of the maximum operation speed. Since the supplying of operating power to the logic circuit block is cut off according to the clock signal frequency except for a period necessary for a circuit operation, leak current, that will flow through each turned-off transistor in the meantime, can be significantly reduced.

Abstract: A dynamic semiconductor integrated circuit is provided, in which an operation speed is increased, an operation is stabilized, and low power consumption is realized in a system where a NAND dynamic circuit is connected to a NOR dynamic circuit. A compensating circuit is provided, which compensates for a voltage drop at an output node of the NOR dynamic circuit due to a coupling capacitance formed between the output node of the NOR dynamic circuit and an output node of the NAND dynamic circuit, caused when the output node of the NAND dynamic circuit is discharged while the output node of the NOR dynamic circuit holds a charge.

Abstract: A semiconductor device includes first, second and third semiconductor circuits. The first semiconductor circuit has a first function. The second semiconductor circuit has a second function different from the first function. The third semiconductor circuit is provided in the second semiconductor circuit and has part of the first function. The third semiconductor circuit transmits/receives no signals to/from the second semiconductor circuit and operates independently of the second semiconductor circuit.

Abstract: A dual rail flip flop with complementary outputs includes a master stage with embedded logic, a sensing stage, and one or more slave stages. The flip flop operates in a pre-charge state and an evaluate state. During the pre-charge state when a clock signal is low, the flip flop pre-charges internal keeper nodes to a high value. When the clock signal transitions high, the flip flop enters an evaluation state and one of the internal keeper nodes evaluates to a low value. The sense stage senses which of the internal keeper nodes is evaluating to zero, and drives it to zero faster. The slave stages reflect the state of the internal keeper nodes during the evaluate state, and maintain their states during the pre-charge state.

Abstract: A slave latch circuit has a gate for being supplied with a signal which is an inversion of a signal outputted from a first output terminal and a control'signal, generating a signal based on the supplied signals, and outputting the generated signal from a second output terminal. The gate controls the output signal outputted from the second output terminal. The gate may comprise a NAND gate for being supplied with a ground potential as the control signal in a normal mode of operation for thereby fixing the output signal outputted from the second output terminal to a power supply potential. Alternatively, the gate may comprise a NOR gate for being supplied with the power supply potential as the control signal in the normal mode of operation for thereby fixing the output signal outputted from the second output terminal to a ground potential.

Abstract: A source synchronous type interface circuit in which, for fetch of a transmitted data, a source synchronous clock indicating a data transmission timing is transmitted from transmission to reception side along with the data, so that a reception clock is generated to define an operation timing of a first reception flip-flop for taking in a data from the reception signal of the source synchronous clock. The interface further includes a second reception flip-flop for feeding an output from the first reception flip-flop further to a second reception flip-flop in synchronization with a common system clock and a variable delay circuit for absorbing phase fluctuations of the first reception flip-flop depending on transmission delay time, to assure a phase difference required for correctly receiving the data. The variable delay circuit has a delay amount automatically controlled according to phase differences between the system clock and the source synchronous clock received.

Abstract: A phase frequency detector (PFD) circuit (516) compares two clock signals and generates a number of outputs to indicate a phase difference between these two clock signals (513, 519). The phase frequency detector has more than three states. The PFD circuit may be used in phase locked loop (PLL) or delay locked loop (DLL) circuit in order to maintain or lock a phase relationship between the two clock signals. The PFD circuitry will allow for a fast lock acquisition time, even when there is a relatively wide frequency range between the two clock signals.

Abstract: A double data rate dynamic logic gate in which an evaluation phase is performed for each phase of a clock signal. In one embodiment, an nMOSFET pull-down logic unit is clocked by two nMOSFETs switched in complementary fashion, and dynamic latches provide the output signals. In another embodiment, two nMOSFET pull-down logic units are employed, each clocked by an nMOSFET in complementary fashion, and a static logic unit provides the output signals.

Abstract: A logical processing part is formed by a pass transistor logic element, and an output signal of the pass transistor logic element is applied to the gates of MOS transistors for differentially amplifying and latching the output signal in the latch stage. This latch stage is formed by master and slave latch circuits, and power supply to the master latch circuit is cut off while holding an information signal only in the slave latch circuit with the level of a power supply voltage thereto increased, reducing a leakage current in a sleep mode or a power down mode. A logic circuit correctly operating at a high speed with low current consumption under a low power supply voltage is provided.

Abstract: The present invention includes a logic circuit block operated in synchronism with a clock signal, power supply switches which supply power to the logic circuit block, and a switch control circuit which controls the power supply switches. The switch control circuit switch-controls the power supply switches so as to bring a period shorter than the cycle of the clock signal to an on operation period in synchronism with a clock signal. When the logic circuit block is supposed to be activated in synchronism with a clock signal having a frequency lower than a clock signal frequency for defining the maximum operation speed of the logic circuit block, the logic circuit block does not develop a malfunction theoretically if capable of operation for each cycle of the clock signal at least only for a time interval defined by the clock signal frequency of the maximum operation speed.

Abstract: A dynamic logic system is disclosed that uses transmission gates coupled between the inputs and output of inverting CMOS logic gates creating a “vented” CMOS logic gate (VCMOS). A clock is used to turn the transmission gates on during a pre-charge or “vent” cycle which causes the inputs and output of the VCMOS to go to an intermediate or vented state between a logic one and a logic zero. During an evaluation phase, inputs are applied to the VCMOS gate which will evaluate to a logic one or zero depending on the states of the inputs and the logic of the VCMOS gate. A family of vented CMOS gates are constructed by adding transmission gates in series with inputs or outputs to create input VCMOS (IVCMOS) and output VCMOS (OVCMOS) which are used to construct vented dynamic logic blocks (VDLB). A VDLB comprises groups of VCMOS gates which may be vented and isolated from other gates during venting.

Abstract: An apparatus for determining a state of a plurality of clock signals, comprising a circuit configured to store a state of each of said plurality of clock signals upon an edge of a data signal.

Abstract: A data serializer includes a differential output stage. The differential output stage has n pairs of first and second control inputs, wherein each pair of control inputs corresponds to one of n data inputs. Each pair of first and second control inputs is driven by first and second logic AND circuits having p-channel output drive transistors.

Abstract: A dynamic circuit having reduced dynamic node switching latency. The operating status of the dynamic circuit alternates between a pre-charge phase in which a pre-charge device charges the dynamic node, and an evaluation phase in which data at the input of the dynamic circuit may or may not precipitate a dynamic node discharge. Each evaluation phase may be characterized as including an initial standby interval prior to the evaluation discharge, followed by an evaluate interval over which the dynamic node completes an evaluation discharge. A standby device is utilized to drive an output of the dynamic circuit low during a pre-charge phase and to maintain the output low during an standby interval in which dynamic circuit inputs do not result in the dynamic node being discharged. The dynamic circuit includes a standby control circuit that disables the standby device during the evaluation interval, resulting in reduced dynamic node switching capacitance.

Abstract: In a semiconductor integrated circuit, the number of rows of transistors in each of first driver circuits is increased or decreased using MOS transistors group in clock driver circuits regions arranged in an array, such as in portions of circuit cell regions into which a core region is divided, in order to supply clock signals to cell, such as a megacell, through a mesh of interconnected clock signal supply lines, in the core region.

Abstract: A logical design method for a semiconductor integrated circuit includes the steps of: a) generating a circuit at a logical level so as to meet given functions and specifications; b) extracting a critical path, which will cause the longest delay, from the circuit generated in the step a); c) counting how many times a path leading from each input terminal to an output terminal in every logic cell of the circuit has operated; d) calculating a degradation rate associated with the path leading from each said input terminal to the output terminal in each said logic cell on the critical path by reference to the number of times of operation obtained in the step c); and e) exchanging a connection to one of the input terminals of each said logic cell, which terminal is associated with the critical path, with a connection to another one of the input terminals of the logic cell, which terminal is associated with another path corresponding to a lower degradation rate than that of the critical path, by reference to the deg

Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate (i) one or more first enable signals and (ii) one or more first flag signals in response to a first clock signal and a second enable signal. The second circuit may be configured to generate a second flag signal in response to (i) the one or more first enable signals, (ii) the one or more first control signals, (iii) a second clock signal, and (iv) a pulse signal. The third circuit may be configured to generate the pulse signal in response to (i) a third clock signal and (ii) the one or more first flag signals.

Abstract: A data serializer includes a differential output stage. The differential output stage has n pairs of first and second control inputs, wherein each pair of control inputs corresponds to one of n data inputs and n is an integer greater than one. Each pair of first and second control inputs is driven by a respective logic AND circuits having a rise time controlled by a first adjustable controlled current source and a fall time controlled by a second adjustable controlled current source.

Abstract: A logic gate includes a logic circuit having an input node and an output node, an enabling transistor coupled between a first power supply node and the output node, the enabling transistor adapted to couple the output node to the first power supply node during an evaluation phase in the logic gate, and a pre-charge transistor coupled between the output node and a second power supply node, the pre-charge transistor adapted to couple the output node to the second power supply node during a pre-charge phase in the logic gate.

Abstract: A reversible adiabatic logic circuit includes a forward logic function circuit, a reverse logic function circuit, a compensation circuit and a clamping circuit. The forward logic function circuit driven by a first clock among power supply clocks having 8 phases during one time period, computes a forward logic function of a complimentary dual rail circuitry using NMOS transistors and determines charging paths of output nodes. The reverse logic function circuit driven by a second clock behind the first clock by two phases, computes a reverse logic function of the complimentary dual rail circuitry using NMOS transistors and determines discharging paths of output nodes. The compensation circuit compensates a decrease in the swing in the output nodes due to thresholds of the NMOS transistors. The computing units of the forward logic function and the reverse logic function are implemented by NMOS transistors only, and the decrease in the swing of the NMOS transistors is compensated using a pair of PMOS transistors.

Abstract: The present invention is a method and apparatus that synchronizes logic in an integrated circuit (IC). The present invention discloses a global clock signal with a global phase and an approximately 50% duty cycle. Additionally, the present invention discloses a first local clock signal with a first phase and an approximately 50% duty cycle that couples to a first dynamic logic gate where the first local clock signal is generated from the global clock signal. One or more intermediate local clock signals with one or more intermediate phases are generated from the global clock signal where each intermediate local clock signal has an approximately 50% duty cycle that couples to one or more intermediate dynamic logic gates. An end local clock signal with an end phase and an approximately 50% dutycycle that is also generated from the global clock signal and that couples to an end dynamic logic gate.

Abstract: A single rail domino logic circuit using a four-phase clocking scheme. A stacked PMOS pair provides a quarter clock cycle precharge time. The quarter clock cycle precharge time allows for placement of an additional inverter in the output signal path to form both an output signal and a complement of the output signal for use in subsequent logic stages.

Abstract: The present invention allows the logic state of a clocked precharge (CP) logic gate to be tested when stopping or starting the logic gate's clock and comprises a plurality of clock signals with overlapping phases and a plurality of CP logic gates coupled in series. Each CP logic gate of the plurality of CP logic gates is coupled to an individual clock signal. The present invention further comprises one or more signal keeper devices coupled to certain individual CP logic gates in the critical path of the logic state. The signal keeper device allows the state of the plurality of CP logic gates to be tested when stopping or starting the individual clock signal of an individual logic gate of said plurality of logic gates. The present invention is suitable for a variety of testing techniques that includes IDDQ, scan testing, and hardware emulation testing.

Abstract: In transmitting a first pair of differential clock signals UCLK, UXCLK having an extremely small amplitude voltage based on a power-source potential and a second pair of differential clock signals LCLK, LXCLK having an extremely small amplitude voltage based on the power-source potential, an inverting circuit as a signal receiving circuit is composed of a CMOS inverting circuit. A PMOS transistor composing the CMOS inverting circuit has a gate electrode and a source electrode receiving the first pair of differential clock signals. An NMOS transistor composing the CMOS inverting circuit has a gate electrode and a source electrode receiving the second pair of differential clock signals. When the potentials of the differential clock signals change, potentials at the respective gate and source electrodes of the two transistors shift in opposite directions, which surely cuts off the transistors.

Abstract: A top clock stacked circuit is provided that substantially prevents charge sharing and that prevents any deleterious bipolar effect. The top clock stacked circuit comprises a primary pre-charge circuit coupled to a primary node, a first device coupled between the primary node and a first secondary node, and a second device coupled between the first secondary node and a second secondary node. A second pre-charge circuit is coupled to the first secondary node and a pre-discharge circuit is coupled to the second secondary node. In response to a first clock polarity, the primary and the second pre-charge circuits pre-charge the primary and the first secondary nodes, respectively, and the pre-discharge circuit pre-discharges the second secondary node. Thereafter, in response to a second clock polarity, the first device creates a path between the primary node and the first secondary node. Because both nodes are pre-charged to the same voltage, charge sharing is substantially prevented.

Abstract: A two-phase dynamic logic circuit for complementary GaAs HIGFET fabrication processes has a precharge transistor connected between a precharge volt source and an output node of the logic circuit. The precharge transistor is controlled by a clock signal such that the output node precharges when the clock signal is low and is isolated from the precharge voltage source when the clock signal is high. An evaluate transistor connected to the output node and an NFET logic block has a first terminal connected to the evaluate transistor such that the evaluate transistor is between the NFET logic block and the output node. A second terminal of the logic block is connected to a voltage source and a data input terminal that is arranged to receive data input signals. The NFET logic block includes on or more transistor(s) is arranged to generate a logic value.

Abstract: A method and apparatus is provided for changing a self-timed circuit into a self-resetting circuit to reduce the inherent delay of the self-timed circuit by an amount of latency between the assertion of the data and the assertion of the valid signal. Circuitry is provided to enable the effective de-coupling of the self-timing operation to enable data to move through the logic circuitry without the latency associated with the reception and generation of "valid" and "complete" signals being necessary. On the "receiving" side (the circuit being set into self-resetting mode), the logic circuit does not have to wait for the reception of the "valid" signals to begin operation. On the "driving" side (the circuit sending the data), the logic circuit does not have to wait for the "completion" signal to arrive to permit a new operation to occur.

Abstract: A circuit and method are described for transferring data in a semiconductor memory in synchronism with a reference clock. A data transfer circuit according to the invention includes a non-overlapping clock generator, a data output circuit, and a data input circuit. The non-overlapping clock generator generates a plurality of non-overlapping clock signals, each of which is active during a different time interval during a period of one external clock cycle. The data output circuit selects and outputs a selected one of a plurality of internal data signals in response to an active one of the non-overlapping clock signals. The data input circuit then receives the selected one of the internal data signals and outputs it to the semiconductor memory in response to the active one of the non-overlapping clock signals.

Abstract: The present invention comprises a plurality of clock signals with an approximately 50% duty cycle and overlapping phases. The phases of the plurality of clocks are such that the phase of an individual clock signal overlaps the phase of an earlier clock signal by an amount equal to the overlap of the phase of the next clock signal. The present invention further comprises a plurality of clocked precharge (CP) logic gates coupled in series. An individual CP logic gate couples to an individual clock signal though the CP logic gate's evaluate device. For the data flow through the individual CP logic gate, the logic gate receives its data input from an earlier CP logic gate in the series and passes to the next CP logic gate in the series. The earlier CP logic gate couples to an earlier phase clock signal, and the next CP logic gate couples to the next phase clock signal.

Abstract: A timing circuit that utilizes the delay inherent in a clock tree to achieve a desired timing relationship between control or clock signals. The timing circuit is particularly applicable to high speed environments and to asynchronous logic, though it is also applicable to lower speed environments and synchronous logic. A method producing the desired control or clock signals is also disclosed.

Abstract: A clock control circuit receives an external clock signal and generates an internal clock signal. Through use of internal programming and an external trigger signal, the clock control circuit blocks out one or more of the clock cycles of the external clock signal to generate the internal clock signal. The clock control circuit can be used in any semiconductor device, and especially in synchronous flash memory devices with a burst operation. In the synchronous flash memory devices, one or more of the internal clock cycles are blocked out to account for increased delays during certain data sensing operations such as word line switching during data reading. In the synchronous flash memory devices, the sensed data is stored in input/output buffers and transferred out synchronously to the external clock signal.

Abstract: A system and method for providing a static mode for logic circuits with dynamic latches. The invention provides a reliable static mode for testing of the logic circuit, prevents "through current" power consumption when clocks to the logic circuit are stopped, and allows the circuit to be powered down when idle. The system includes a circuit for forcing clock phases to an active state, a circuit for breaking feedback paths within the logic circuit, and an optional clock loss detector for detecting clock inactivity and automatically initiating the static mode.

Abstract: A method and apparatus for precharging a dynamic bus on either phase of a clock signal is presented. An intelligent precharger in accordance with the invention monitors a dynamic bus and detects and signals a discharge event on the bus during a current phase of a clock signal. The current phase of the clock signal can be either one of a first phase or second phase of the clock signal. On the subsequent phase of the clock signal, which is the other of the first phase or second phase of the clock signal, the bus is then precharged.

Abstract: A non-blocking multiple-phase clocking system for use with domino-type dynamic logic provides clock phases with overlapping evaluation phases to a circuit including a several cascaded dynamic logic gates. The circuit also includes a first flip-flop that is coupled to provide input signal(s) to the first dynamic logic gate of the cascade and a second flip-flop that is coupled to receive output signal(s) from the last dynamic logic gate of the cascade. The clocking system provides a first clock phase to the first dynamic logic gate, a second clock phase to the second dynamic logic gate and so on. A timing analysis is performed of each logic path in the circuit to determine the arrival time of each critical input signals to each dynamic logic gate. The delay between adjacent clock phase is then predetermined so that each dynamic logic gate enters its evaluation phase before the critical input signal(s) to the particular dynamic logic gate arrives.

Abstract: A logic circuit family implements self-resetting CMOS logic array macros (SLAMs) which include a plurality of inputs to which a plurality of data input signals can be applied; a plurality of input buffers coupled to receive the input signals from the inputs; a NOR circuit coupled to receive the outputs of the input buffers and a pulsed logic timing signal synchronized within a predefined window with the arrival of the data input signals; an output buffer coupled to receive the output of the NOR circuit; and an output at which a data output signal is produced, with the output signal being a logical NOR of the data input signals; and with each of the NOR circuit, the plurality of input buffers, and the output buffer optionally having a separate reset input to reset it to a standby state. The SLAMs address the very high pressure on the performance of both control logic and control logic design systems.

Abstract: An I/O interface includes latches, clocks, and conditioning circuits implemented in a custom physical layout to produce a reliable and flexible interface to high frequency busses running a plurality of protocols and signal specifications. Three clock trees are used to synchronize the buffering and conditioning of input/output signals before sending such signals to a pad or core. The clock trees are implemented via custom layouts to allow tight control of clock/strobe parameters (e.g., skew, duty cycle, rise/fall times). Two of the clock trees are local to the I/O interface and trigger a plurality of output latches configured on-the-fly to buffer output data signals from the core in asynchronous or synchronous mode. In the synchronous mode, a clock/strobe could be either edge-centered or window-strobe with respect to the data.

Abstract: A method for generating non-blocking multiple-phase clocking system for use with domino-type dynamic logic includes receiving a primary clock signal and generating several delayed phases of the received primary clock signal. The number of clock phases equals the number of dynamic logic gates in the circuit. The method provides a first clock phase to the first dynamic logic gate of the circuit, a second clock phase to the second dynamic logic gate and so on. A timing analysis is performed of each logic path in the circuit to determine the arrival time of each critical input signals to each dynamic logic gate. The delay between adjacent clock phase is then predetermined so that each dynamic logic gate enters its evaluation phase before the critical input signal(s) to the particular dynamic logic gate arrives. This adjustment of the clock phases maximizes the logic evaluation speed of the dynamic logic circuit.

Abstract: In case microcontroller and digital signal processing blocks are used together in one chip, there has been a problem in which the synchronization of the clocks are not consistent with each other when sending a signal from one block to another. In addition, when a reference clock is activated during a change of input signal, an incomplete interval has occurred. Accordingly, in order to solve the above mentioned problem, the present invention discloses a synchronizing circuit which uses a latch circuit("RS") consisted of NAND gates to synchronize an asynchronous input data and a reference clock, thereby solving the problem in which an incomplete interval occurs.

Abstract: The present invention provides an asynchronous state machine with a programmable tSKEW that is used to generate an empty and full flag in a synchronous FIFO buffer. The present invention reduces the delay associated in producing the full or empty flags from a typical eight gate delays, to as little as no gate delays. The present invention accomplishes this by using a set state machine which can only make an internal flag go low, or active, and a reset state machine which can only make the internal flag go high, or inactive. The functioning of the set state machine and the reset state machine is controlled by a blocking logic. The output of each of the state machines is stored in a latch. The output of the latch is presented to an input of the blocking logic, which is used by the blocking logic to control the activity of the state machines.

Abstract: An interface circuit is disposed between a generator of control signals and a plurality of electronic switches in order to produce boosted voltage signals corresponding to the control signals for activating the electronic switches. To avoid the use of a capacitor with a high capacitance and thus to reduce an area of the integrated circuit, the interface circuit includes a generator of activation signals and a plurality of voltage multipliers each having an input connected to an output of the control signal generator, an output connected to at least one terminal for activating an electronic switch and two control terminals connected to an activation signal generator. Each voltage multiplier includes MOS transistors operatively coupled in series between the input and the output. The MOS transistors operate in response to the activation signals to produce a boosted voltage on the capacitor.

Abstract: A circuitry (10) is provided for automatically retiming a received synchronous data signal to a local clock. The circuitry (10) includes a first flip-flop (20) operable to register at least one synchronous data signal in response to a receive clock signal and to generate at least one data output signal. An OR gate (26) receives a data latch enable signal and a local clock signal. The local clock signal is frequency coherent with the receive clock signal. The OR gate (26) produces an enable signal. A latch (28) is coupled to the OR gate (26) for receiving the enable signal and in cascading arrangement with the first flip-flop (20). The latch (28) latches the data output signal on the falling edge of the local clock signal when the data latch enable signal is low. The latch (28) holds the latched data output signal as long as the local clock signal and the data latch enable signal are low. When either the local clock signal or the data latch enable signal is high, the latch (28) passes the data output signal.

Abstract: A method and implementing structure for a domino block circuit 200 includes a minimal component latching circuit 203 which is merged with an exemplary MUX functional block 201, to provide both inverting and latching functions with minimal propagation delay in the domino data path. Implementations with scanning circuitry and including a holding feature are also illustrated.