Abstract: An apparatus for extending lifetime reliability of CMOS circuitry includes a first switching device between a logic high supply rail/logic low supply rail, and a virtual supply rail coupled to the CMOS circuitry. In a first mode of operation the first switching device supplies the full voltage value between the logic high supply rail and the logic low supply rail, and in a second mode of operation, the first switching device isolates the virtual supply rail from the logic high supply rail/logic low supply rail, thereby reducing the voltage supplied to the CMOS circuitry. A second switching device coupled between the virtual supply rail and the logic low supply rail/logic high supply rail, in a third mode of operation, equalizes the voltage on the virtual supply rail and the logic low supply rail/logic high supply rail.

Abstract: An apparatus for extending lifetime reliability of CMOS circuitry includes a logic high supply rail, a logic low supply rail, and a virtual supply rail. In an intense recovery mode of operation, a first switching device is rendered nonconductive so as to isolate the virtual supply rail from the one of the logic high supply rail and the logic low supply rail, and the second switching device is rendered conductive so as to equalize the voltage on the virtual supply rail and the other of the logic high supply rail and the logic low supply rail. At least one device within the circuitry provides one of the logic high voltage and the logic low voltage to a gate terminal of an FET within the circuitry, with a source terminal of the FET coupled to the virtual supply rail, such that the FET is subjected to a reverse bias condition.

Abstract: A low leakage monotonic CMOS logic circuit and a method, a method of design and a system for designing such circuits. The circuit, including: one or more logic stages, at least one of the logic stages having a predominantly high input state or having a predominantly low input state; wherein the logic stages having the predominantly high input state, comprise one or more thin gate dielectric and high threshold voltage PFETs with respect to a reference PFET and one or more thick gate dielectric and low threshold voltage NFETs with respect to a reference NFET; and wherein the logic stages having the predominantly low input state, comprise one or more thick gate dielectric and low threshold voltage PFETs with respect to the reference PFET and one or more thin gate dielectric and high threshold voltage NFETs with respect to the reference NFET.

Abstract: A variable threshold voltage keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits. The threshold voltage of the keeper transistor is dynamically modified during circuit operation to reduce the contention current without sacrificing noise immunity. The threshold voltage of the keeper transistor is controlled by a body bias generator which switches between two voltages in accordance with the clock signal.

Abstract: A semiconductor integrated circuit with an operating voltage having an absolute value is 2.5 V or below includes circuit blocks to which operation voltage is supplied by first and second power lines and a first switching element for each circuit block. Each circuit block includes a first MOS transistor in which a leakage current flows even under a condition that a gate voltage is equal to a source voltage. Each of the first switching elements controls the leakage current flowing through a corresponding first MOS transistor of each circuit block. Also, while one of the first switching elements is controlled to reduce the leakage current flowing through the circuit block relating to one of the first switching elements, another one of the first switching elements is controlled to allow current to flow through the circuit block relating to another one of the first switching elements.

Abstract: A non-inverting dynamic register includes a domino stage, a mux, and an output stage. The domino stage evaluates a logic function based on at least one input data signal and a pulsed clock signal, and opens an evaluation window when the pulsed clock signal goes low, and pulls a pre-discharged node high if it evaluates, and keeps the pre-discharged node low if it fails to evaluate. The mux pulls a feedback node high if the pre-discharged node goes high during the evaluation window, and pulls the feedback node low if the pre-discharged node is low during the evaluation window. The output stage is coupled to the pre-discharged node and the feedback node. The output stage provides an output signal based on states of the pre-discharged and the feedback nodes.

Abstract: Interconnect driver circuits that can be used in the interconnect structures of dynamic integrated circuits (ICs) such as dynamic programmable logic devices (PLDs). An exemplary IC includes two or more logic circuits, and two or more self-resetting interconnect driver circuits coupled between the logic circuits. Each self-resetting interconnect driver circuit includes a multiplexer circuit driving a buffer circuit. In a first state, the buffer circuit drives a first value onto the output terminal of the buffer circuit. In a second state, the buffer circuit first drives a second value onto the output terminal of the buffer circuit and then returns to the first state. Several different circuits are described in detail.

Abstract: A scannable latch incorporates a logic front end that has at least one dynamic logic gate that has a logic tree that perform the normal Boolean logic operation. The dynamic logic gate is combined a scan pull-down logic tree that is coupled to a scan hold latch output and to the dynamic node of the dynamic logic gate. A scan clock and a normal clock determine whether the logic circuitry is in the normal logic mode or in the scan test mode. A static output latch has at least one input that is responsive logic state of a dynamic node. The evaluated state of the dynamic node is set by either the logic tree of the dynamic logic gate or the scan pull-down logic tree of the scan circuitry in response to the logic state of the scan clock or the normal clock.

Abstract: A scannable latch incorporates a logic front end that has at least one dynamic logic gate that has a logic tree that perform the normal Boolean logic operation. The dynamic logic gate is combined a scan pull-down logic tree that is coupled to a scan hold latch output and to the dynamic node of the dynamic logic gate. A scan clock and a normal clock determine whether the logic circuitry is in the normal logic mode or in the scan test mode. A static output latch has at least one input that is responsive logic state of a dynamic node. The evaluated state of the dynamic node is set by either the logic tree of the dynamic logic gate or the scan pull-down logic tree of the scan circuitry in response to the logic state of the scan clock or the normal clock.

Abstract: A gated clock logic circuit includes a pulse generator and a precharged latch. The pulse generator generates a pulse signal in response to a clock signal, and the precharged latch generates a gated clock signal in response to the clock signal, the pulse signal, and a control signal.

Abstract: The present invention provides a low swing current mode logic circuit including: a current mode logic block having data inputs and outputs; a pre-charging circuit for pre-charging the outputs; a dynamic current source; an evaluation circuit for evaluating the logic block during an evaluation phase; and, a feedback path arranged between the outputs and the dynamic current source which is responsive to a difference between the outputs. The simplicity of generating the low swing, achieved by the feedback which may be implemented by only two transistors, is in contrast with the complexity introduced by some methods used by other logic styles for achieving low swing.

Abstract: The present invention discloses an XOR-based conditional keeper and an architecture implementing its application to match lines, wherein the XOR gate in the conditional keeper receives a clock signal synchronous with CAM (Content Addressable Memory) cells and cooperates with a floating signal from the floating node to create an XOR control signal, and the XOR control signal is transmitted to a P-type transistor to create a data signal to control the XOR-based conditional keeper so that the XOR-based conditional keeper can execute an appropriate corresponding action, which can replace the conventional keepers of merely “on” and “off” modes. Further, the XOR-based conditional keeper of the present invention can apply to the dynamic CAM match line architecture so that the dynamic match line can have lower power consumption, higher noise immunity, and high processing speed.

Abstract: Dynamic logic register including evaluation logic, delay logic, latching logic, and a keeper circuit. The evaluation logic evaluates a logic function based on data input. The logic function evaluates to either a first state or a second state. The delay logic generates a kill signal, where the kill signal is a delayed version of a clock signal, and where the delay between the clock and kill signals comprises a hold time, and where the hold time is shortened when the logic function evaluates to the first state. The latching logic is responsive to the clock and kill signals and the state of pre-charged node, and controls the state of an output node based on the state of a pre-charged node during an evaluation period between an operative edge of the clock signal and the next edge of the kill signal, and otherwise presents a tri-state condition to said output node.

Abstract: A boost circuit is disclosed that includes a plurality of transistors connected between complementary phases of a clock signal. The boost circuit further includes a first electrical node connected between at least two of the plurality of transistors wherein the plurality of transistors are configured to generate a second voltage from a first voltage at the electrical node in response to the clock signal.

Abstract: A non-inverting dynamic register includes a domino stage, a mux, and an output stage. The domino stage evaluates a logic function based on at least one input data signal and a pulsed clock signal, and opens an evaluation window when the pulsed clock signal goes high, and pulls a pre-charged node low if it evaluates, and keeps the pre-charged node high if it fails to evaluate. The mux pulls a feedback node low if the pre-charged node goes low during the evaluation window, and pulls the feedback node high if the pre-charged node is high during the evaluation window. The output stage is coupled to the pre-charged node and the feedback node. The output stage provides an output signal based on states of the pre-charged and the feedback nodes.

Abstract: A scan flip-flop circuit including an input section employing a dynamic circuit and an output section employing a static circuit, capable of latching in data within a period of a pulse width that is shorter than the clock cycle, wherein only three N-type transistors are connected in series in the input section employing a dynamic circuit. A data signal is input directly to one of the three N-type transistors. On the other hand, a test input signal is input to an AND/OR inverter circuit. The AND/OR inverter circuit receives, as a control signal, the potential of the node obtained as the clock signal passes through two inverter circuits. Therefore, there is required only a short hold time for the test input signal.

Abstract: In an embodiment of the invention, a CMOS circuit arrangement is provided. The CMOS circuit arrangement includes a PMOS logic circuit providing a logic function, having PMOS field effect transistors, wherein a first operating potential is fed to an input of a PMOS logic circuit, an NMOS logic circuit providing the logic function, having NMOS field effect transistors, a first clock transistor, the first source/drain terminal of which is coupled to an input of the NMOS logic circuit, wherein a clock signal is applied to the gate terminal of the first clock transistor, and wherein a second operating potential is fed to the second source/drain terminal. An output of the PMOS logic circuit and an output of the NMOS logic circuit are coupled to one another. Furthermore, an inverter circuit is coupled to the output of the PMOS logic circuit and to the output of the NMOS logic circuit.

Abstract: A circuit for calculating a logical combination of two input operands includes a first input for receiving a first dual rail signal having data values of the first input in a calculation cycle and precharge values in a precharge cycle, a second input for receiving a second dual rail signal having data values of the second input in the calculation cycle and precharge values in the precharge cycle, and an output for outputting a third dual rail signal having result values in the calculation cycle and precharge values in the precharge cycle.

Abstract: Clock error detections circuits can detect clock duty cycle error and/or quadrature phase error. During an evaluation phase, capacitors are charged. During an evaluation phase, the capacitors are unequally discharged based on the error. A positive feedback mechanism latches the result.

Abstract: A domino circuit and method include a master evaluation node to which a master discharge path with a wide input AND gate is coupled and a virtual evaluation node to which an output stage and slave discharge path are coupled. A current mirror interconnects the master discharge path and the slave discharge path. The devices in the current mirror are sized so that current flowing in the master discharge path is amplified into the slave transmission path.

Abstract: A dynamic logic gate has a device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node with a device during an evaluate phase of the clock. The dynamic node has a keeper circuit comprising an inverter with its input coupled to the dynamic node and its output coupled to the back gate of a dual gate PFET device. The source of the dual gate PFET is coupled to the power supply and its drain is coupled to the dynamic node forming a half latch. The front gate of the dual gate PFET is coupled to a logic circuit with a mode input and a logic input coupled back to a node sensing the state of the dynamic node. The mode input may be a slow mode to preserve dynamic node state or the clock delayed that turns ON the strong keeper after evaluation.

Abstract: A non-inverting dynamic register includes a domino stage, a mux, and an output stage. The domino stage evaluates a logic function based on at least one input data signal and a pulsed clock signal, and opens an evaluation window when the pulsed clock signal goes low, and pulls a pre-discharged node high if it evaluates, and keeps the pre-discharged node low if it fails to evaluate. The mux pulls a feedback node high if the pre-discharged node goes high during the evaluation window, and pulls the feedback node low if the pre-discharged node is low during the evaluation window. The output stage is coupled to the pre-discharged node and the feedback node. The output stage provides an output signal based on states of the pre-discharged and the feedback nodes.

Abstract: A non-inverting dynamic register includes a domino stage, a mux, and an output stage. The domino stage evaluates a logic function based on at least one input data signal and a pulsed clock signal, and opens an evaluation window when the pulsed clock signal goes high, and pulls a pre-charged node low if it evaluates, and keeps the pre-charged node high if it fails to evaluate. The mux pulls a feedback node low if the pre-charged node goes low during the evaluation window, and pulls the feedback node high if the pre-charged node is high during the evaluation window. The output stage is coupled to the pre-charged node and the feedback node. The output stage provides an output signal based on states of the pre-charged and the feedback nodes.

Abstract: Circuit arrangement for producing a dual-rail output signal having a signal processing apparatus with two switches, which are driven as a function of an input signal, a first output connected via one of the switches to a signal processing apparatus foot point, which is at a first potential, and a second output connected via the other switch to the foot point. The signal processing apparatus is connected via a switching apparatus to outputs of the circuit arrangement in order to output a dual-rail output signal. The outputs of the switching apparatus are each connected to one or to both inputs of the switching apparatus as a function of a control signal. A potential monitoring apparatus defines the potentials at the outputs of the circuit arrangement when these outputs are not connected via the switching apparatus and the signal processing apparatus to the foot point of the signal processing apparatus.

Abstract: A domino logic test circuit includes a dynamic node, a precharge device for charging the dynamic node, and an output inverter for inverting an output of the dynamic node. A logic network is coupled to the dynamic node for discharging the dynamic node in accordance with logic. A footer device enables and disables the logic network. A keeper device is coupled to the dynamic node for retaining a charge state of the dynamic node while awaiting the logic network to operate in accordance with the logic. A test mode selection device is coupled to the dynamic node and is configured to enable a latch in the test mode. A phase selection device is configured to receive at least a wait signal and to enable selection of at least a precharge phase for charging the dynamic node to a voltage level, a write phase for generating a value to the latch based on the logic and the voltage level of the dynamic node, and a wait phase for enabling reading the value. The selection is based, at least partially, on the wait signal state.

Abstract: A keeper device for dynamic logic includes a first keeper path statically coupled to a dynamic data path, the first keeper path configured to prevent false discharge of the dynamic data path during an evaluation thereof, and a second keeper path selectively coupled to the dynamic data path. The second keeper path is configured to maintain the dynamic data path at a nominal precharge level prior to an evaluation thereof, wherein the second keeper path is decoupled from the dynamic data path during the evaluation.

Abstract: Embodiments related to fast flip-flops are disclosed.

Abstract: A method and apparatus for determining the size of a keeper transistor in a dynamic circuit is provided. A first portion of a dynamic circuit, comprising the keeper transistor, is analyzed to determine keeper current data that describes what size the keeper transistor would need to be to supply a specified amount of keeper current. A second portion of the dynamic circuit is analyzed, separate from the first portion, to determine an estimated amount of leakage current that passes through the PDN when the PDN is not actively discharging the dynamic node may be determined. The size for the keeper transistor that enables the keeper transistor, when activated, to produce an amount of keeper current that is substantially equal to the estimated amount of leakage current may be determined based on the analysis performed on the first and second portion.

Abstract: A synchronous output buffer circuit which effectively moves combinational logic associated with an output enable operation, boundary scan operation, and voltage translation to a pipe that leads into a pair of output registers that operate in response to the output clock signal. The output registers may be forced to asynchronously route an input signal to an output terminal during a reset mode and during a boundary scan mode. The output registers can include a safety circuit, which prevents pull-up and pull-down devices (which drive the output signal), from turning on at the same time.

Abstract: A logic gate with a differential evaluation stage, precharge circuitry for precharging outputs of the gate, latch circuitry for latching the outputs and an inverter. The gate uses high speed, low threshold voltage devices in the evaluation stage, yet uses higher threshold voltage devices in other portions of the gate (e.g., precharge circuitry). This use of dual threshold voltage devices minimizes power consumption while maximizing speed. During standby mode, the gate is operated in an evaluation mode to substantially mitigate standby current.

Abstract: A dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock controlled provides increased noise immunity in dynamic digital circuits. By clocking the pre-charge element with a signal having a reduced swing in the voltage direction that turns off the pre-charge element, the pre-charge element provides a small current that prevents the dynamic summing node of a gate from erroneously evaluating due to noise, and eliminates the need for a keeper device. Providing the reduced-swing asymmetric clock as a separate signal prevents performance degradation in the rest of the circuit. Specifically, the foot devices in the dynamic portion of the circuit are controlled with the full swing clock so that evaluation is not compromised by noise or slowed. Foot and pull-up devices in any static portion of the circuit are also controlled with the full-swing clock so that switching speed and leakage immunity are not affected.

Abstract: A multi-enabled clock gating circuit reduces clock enable setup time. In one example, the multi-enabled clock gating circuit comprises an OAI logic gate and a clock enable control circuit. The OAI logic gate is configured to generate a gated clock signal by inverting an input clock signal responsive to one of a timing-sensitive clock enable signal and a timing-insensitive clock enable signal being active. The clock enable control circuit is configured to prevent the OAI logic gate from receiving the timing-insensitive clock enable signal responsive to the timing-sensitive clock enable signal being active. In one or more embodiments, a multi-enabled clock gating circuit having reduced clock enable setup time may be included in an integrated circuit for implementing clock gating during different operating modes of the integrated circuit.

Abstract: A method and apparatus are provided for implementing subthreshold leakage current reduction in limited switch dynamic logic (LSDL). A limited switch dynamic logic circuit includes a cross-coupled NAND and inverter logic. A dynamic node provides a first input to the NAND. A sleep signal provides a second input to the NAND. An output of the NAND provides an input to the inverter logic that inverts the NAND output and provides a complementary output. The NAND logic includes a series connected first sleep transistor receiving the sleep input. The first sleep transistor is turned OFF during the sleep mode. A second sleep transistor is connected between a voltage supply rail and the NAND output. The second sleep transistor is turned ON during the sleep mode to force high the NAND output and force low complementary output.

Abstract: A dynamic logic gate has a dynamic node pre-charged in response to a pre-charge phase of a clock signal and a logic tree with a plurality of logic inputs for evaluating the dynamic node during an evaluate phase of the clock signal in response to a Boolean combination of the logic inputs. The logic tree has a stacked configuration with at least one multi-gate FEAT device for coupling an intermediate node of the logic tree to the dynamic node in response to a first logic input of the plurality of logic inputs or in response to the pre-charge phase of the clock signal. The multi-gate FEAT device has one gate coupled to the first logic input and a second gate coupled to a complement of the clock signal used to pre-charge the dynamic node.

Abstract: A bus switch chip is limited to operating with a power-supply voltage of 1.8 volts relative to a 0-volt ground. Differential bus signals switched through the bus switch chip swing from 2.7 to 3.3 volts, well above the chip's specified power-supply voltage. The bus switch chip is level-shifted by applying a 1.5-volt signal as the chip's ground, and a 3.3-volt signal as its power supply, so the chip's net power supply is within the specification at 1.8 volts. High-Definition Multimedia Interface (HDMI) and Digital Visual Interface (DVI) require that the differential signals are never driven to ground. However, some non-compliant video transmitters drive differential signals to ground when disabled. External pullup resistors or internal pullup transistors in the bus switch chip are added to the bus signals from non-compliant transmitters to pull disabled signals above the 1.5-volt chip ground to prevent damage from signals below the chip's 1.5-volt ground.

Abstract: A semiconductor integrated circuit device (1) includes: a transistor switch (SWA) for electrically connecting and disconnecting output of a flip-flop (FF64) of a shift register (SR1) and input of a flip-flop (FF65) of a shift register (SR2); and a transistor switch (SWB) for electrically connecting and disconnecting an input driver (Din2) and input of the flip-flop (FF65). Here, when the shift registers (SR1 and SR2) are connected, the transistor switch (SWA) is turned ON and the transistor switch (SWB) is turned OFF by a selection signal.

Abstract: Disclosed are keeper circuits for electronic circuits that selectively maintain the voltage level of an intermediate circuit node at a desired level. In one exemplary embodiment, a keeper transistor either provides current or drains current from the intermediate node to maintain the desired voltage level in response to a signal to do so. The keeper circuit works against a leakage current that either drains current from the node or supplies current to the node. A current-setting transistor is coupled in series with the keeper transistor to set the maximum current through the keeper circuit to a value that is related to this leakage current, preferably tracking the leakage current. With this construction, the current-setting transistor is able to track variations in the leakage current caused by variations in the manufacturing process, and thereby provide dynamic leakage compensation.

Abstract: Circuits are provided for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. Sleep transistors and a dual threshold voltage CMOS technology may be utilized to place idle domino logic circuits into a low leakage state. The circuits may significantly lower the total leakage power as compared to the standard dual threshold voltage domino logic circuits at both the high and low die temperatures. The energy overheads of the circuit techniques may be low, justifying the activation of the proposed sleep schemes by providing net savings in total power consumption during short idle periods.

Abstract: Leakage currents at IC inputs can be avoided while the IC is disabled by providing a switch that is responsive to deactivation of an enable input to isolate functional circuitry of the IC from one of the power supply nodes of the IC. This eliminates power supply current while the IC is disabled. Further unwanted current flow can be avoided while the IC is disabled by providing a switch that is responsive to the enable input for selectively connecting and disconnecting the base of a reference voltage transistor to and from the transistor's grounded collector, which collector is defined by the substrate of the IC. Disconnection of the base from the grounded substrate/collector eliminates base current and thus prevents emitter-to-collector current flow through the transistor when the IC is disabled.

Abstract: An edge-triggered flip-flop is provided that includes one or more storage nodes and a pre-charge circuit in communication with the storage circuit. The storage circuit is configured to pre-charge the one or more storage nodes to a pre-determined voltage potential. The storage circuit further includes a first pull-down logic circuit in communication with the storage circuit and separate second pull-down logic circuit in communication with the storage circuit. The first pull-down logic circuit is configured to discharge one or more of the pre-charged storage nodes in response to first input data and the second pull-down logic circuit is configured to discharge one or more of the pre-charged storage nodes in response to second input data.

Abstract: Power dissipation of a semiconductor integrated circuit chip is reduced when it is operated at an operating voltage of 2.5 V or below. A switching element is provided in each circuit block within the chip. Constants of the switching element are set so that leakage current in each switching element in their off-state is smaller than the subthreshold current of MOS transistors within the corresponding circuit block. Active current is supplied to active circuit blocks, while switching elements of non-active circuit blocks are turned off. Thus, dissipation currents of non-active circuit blocks are limited to leakage current value of corresponding switching elements. Thus, the sum of dissipation currents of non-active circuit blocks is made smaller than the active current in the active circuit blocks. As a result, power dissipation in the semiconductor integrated circuit chip can be reduced even in the active state.

Abstract: A domino clocking method includes providing a domino logic circuit including first and second coupled domino gates, providing a first clock signal for clocking the first domino gate, and providing a second clock signal for clocking the second domino gate, wherein the first clock signal has a shortened positive phase duty cycle relative to the second clock signal. The positive phase of the first clock signal is shortened by an amount greater than or equal to a precharge time plus a falling edge skew between the clock signals. The footer transistor in the second domino gate can be eliminated. The first and second clock signals have the same frequency. The timing of the data presented to the first domino gate, and the first and second clock signals is adjusted so that there is no direct path between the power supply voltage and ground during the entire precharge phase of the second domino gate.

Abstract: The present invention relates to the field of hardware logic circuits and in particular to dynamic hardware logic implemented in computer processors, and more particularly, to an integrated circuit comprising a dynamic logic function implementing a predetermined logic function with a plurality of transistor stacks, the integrated circuit comprising a precharge node at the input of said logic function implementation, an output latch connected to the output node of said logic function for stabilizing the result of the evaluation of said logic function. The present invention provides such integrated dynamic circuit with a latch, which is protected against instability even in situations involving complex logic functions which are evaluated and their output states are saved by said output latch.

Abstract: The present invention system and method provides voltage level support for an output target signal (e.g., a dynamic node output signal) that “keeps” the output target signal at a particular voltage level with efficient suspension of the voltage level maintenance or support during an evaluation transition period (e.g., a read operation) of the output target signal.

Abstract: A logic circuit including at least one evaluate circuit coupled to a static output logic circuit. In one example, the evaluate circuit includes a dynamic node, a full keeper, an evaluate device, and a logic tree. In some examples, the output logic circuit is a sampled static output logic circuit and includes a sample device. In some examples, the logic circuit includes multiple evaluate circuits, each with a dynamic node coupled to a control gate of a transistor of the output logic circuit. Some examples may include a delay in a clock signal to increase the internal race margin.

Abstract: A variable threshold voltage keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits. The threshold voltage of the keeper transistor is dynamically modified during circuit operation to reduce the contention current without sacrificing noise immunity. The threshold voltage of the keeper transistor is controlled by a body bias generator which switches between two voltages in accordance with the clock signal.

Abstract: A semiconductor integrated circuit according to the present invention comprises a latch circuit, a retaining circuit, and a feedback circuit, wherein the latch circuit inputs therein an input data signal, a clock signal and a feedback signal and outputs an output data signal, the retaining circuit retains the output data signal, and the feedback circuit inputs therein the input data signal and the output data signal to thereby generate the feedback signal based on logic combinations of the input data signal and the output data signal, and an internal operation of the latch circuit is turned on/off by means of the feedback signal.

Abstract: Multi-Threshold CMOS (MTCMOS) devices include a high threshold voltage current control switch that is responsive to a first control signal, a low threshold voltage logic circuit and a flip-flop that is configured to store data from the low threshold voltage logic circuit and that is responsive to a second control signal. A control circuit also is provided that is configured to change a logic state of the second control signal and then, after a first delay, to change a logic state of the first control signal, in response to the MTCMOS device entering a sleep mode. The control circuit is further configured to change the logic state of the first control signal and then, after a second delay that is different from the first delay, to change the logic state of the second control signal in response to the MTCMOS device entering an active mode. Related methods also are provided.

Abstract: A dynamic logic register including a complementary pair of evaluation devices, delayed inversion logic, a dynamic evaluator, latching logic, and a keeper circuit coupled to the output. The evaluation devices are responsive to a clock signal and provide a pre-charged node and an evaluation node. The delayed inversion logic outputs a complete signal that is a delayed and inverted version of the clock signal. The dynamic evaluator, coupled between the pre-charged and evaluation nodes, evaluates a logic function based on a data signal during an evaluation period between operative edges of the clock and complete signals. The latching logic enables the state of an output node to be determined by the state of the pre-charged node during the evaluation period and otherwise clamps the pre-charged node to prevent perturbations of the data signal from propagating to the output node.

Abstract: A circuit comprises an evaluate clock trace to receive an evaluate clock signal and a precharge clock trace to receive a precharge clock signal. The circuit further comprises sample circuitry coupled to a first signal trace, a second signal trace, the precharge clock trace and the evaluate clock trace to facilitate a detection of a transition on the first signal trace from a first voltage level to a second voltage level. In addition, the circuit comprises latch circuitry coupled to the first signal trace, the second signal trace, the precharge clock trace and the evaluate clock trace to utilize at least a portion of the sample circuitry to maintain voltage levels on the first and the second signal traces when an evaluate clock and a precharge clock are inactive.