Abstract: A time-to-digital system, such as a frequency synthesizer, includes a power management circuit and a time-to-digital converter (TDC). Said power management circuit is coupled to a frequency reference clock and a variable clock, and arranged to output a delayed frequency reference clock and a single pulse of said variable clock ahead of a transition of said delayed frequency reference clock. Said TDC is coupled to said power management circuit and arranged to produce a digital TDC output.

Abstract: A splitter circuit in a semiconductor device includes a first inverter that receives an input signal and outputs an inverted signal, a second inverter that receives the inverted signal and outputs a non-inverted signal (a first output signal), a third inverter that receives the input signal and outputs an inverted signal (a second output signal) and an auxiliary inverter that shares an output signal line with the third inverter. The third inverter and the auxiliary inverter use an inverted signal of the input signal as power supplies.

Abstract: A signal generating apparatus includes: a direct digital synthesizer configured to generate an output signal of a frequency according to first control data based on a reference clock; and a controller configured to provide the direct digital synthesizer with the first control data at a timing synchronized with the reference clock, wherein the controller includes a table which stores second setting data for controlling the frequency of the output signal based on jitter information and provides the direct digital synthesizer with the second setting data in the table as the first control data at the timing.

Abstract: A synthesizer includes: a synthesizer unit that outputs an oscillation signal based on a reference oscillation signal; a temperature detecting unit that detects a temperature; a time variation detecting unit that detects a time variation in frequency of the reference oscillation signal based on a result of temperature detection by the temperature detecting unit; and a control unit that adjusts a frequency of the oscillation signal outputted from the synthesizer unit based on a result of detection by the time variation detecting unit. With such a configuration, frequency compensation control is performed on a transducer having a large temperature coefficient.

Abstract: In one embodiment, the present invention includes a mixer circuit to receive and generate a mixed signal from a radio frequency (RF) signal and a master clock signal, a switch stage coupled to an output of the mixer circuit to rotatingly switch the mixed signal to multiple gain stages coupled to the switch stage, and a combiner to combine an output of the gain stages.

Abstract: A computer-readable, non-transitory medium stores therein a design support program that causes a computer capable of accessing a storage device storing therein for each cell, an output voltage value of the cell, for each elapsed time period from a start of variation of an input voltage applied to the cell, to execute a process. The process includes extracting from the storage device, the output voltage value for each elapsed time period related to an cell under design selected from circuit information of a circuit under design; determining based on a specific voltage value, an extracted elapsed time period to be corrected; adding a time constant of an output from the cell under design to the elapsed time period determined to correction; and outputting the output voltage value for each corrected elapsed time period and the output voltage value for each elapsed time period that is not determined for correction.

Abstract: A clock generator is illustrated. The clock generator mentioned above includes a multimodulus frequency divider and a delta-sigma modulator. The multimodulus frequency divider is archived by switching the phase thereof. The multimodulus frequency divider increases the operating frequency of the clock generator effectively, and has a characteristic with half period resolution for reducing the jitter of an output clock signal when its spectrum is spread. Besides, the delta-sigma modulator increases the accuracy of the triangle modulation and reduces error of quantization by adding a few components therein. Thus, the clock generator could be expanded to a programmable clock generator.

Abstract: In an embodiment, an integrated circuit may include one or more power managed blocks and a power manager circuit. The power manager circuit may be configured to generate a block enable for each power managed block and a block enable clock. The power managed block may generate local block enables to various power switches in the power managed block, staggering the block enables over two or more block enable clock cycles. In particular, the power managed block may include a set of series-connected flops that receive the block enable from the power manager circuit. The output of each flop may be coupled to a respective set of power switches and may enabled those switches. The change in current flow due to enabling and/or disabling the power managed block may thus be controlled. In an embodiment, the frequency of the block enable clock may be set to a defined value independent of process, voltage, and temperature conditions in the integrated circuit.

Abstract: Calibration data for calibrating time to digital conversion is obtained by switching a feed circuit of a time to digital converter between a normal operating mode or a calibration mode. A delay circuit with a delay circuit input and a plurality of taps outputs. A sampling register samples data from the data inputs. The feed circuit provides for selection of transitions of the oscillator signal that control timing of a first active transition at the clock circuit after a transition at the delay circuit input. A control circuit switches the feed circuit between normal operating mode and calibration mode, and controls the feed circuit successively to select a plurality of different transitions to control timing of the first active transition in the calibration mode. The control circuit reads out resulting data from the sampling register for each selection and determines calibration data for the oscillator signal from said data.

Abstract: A Decision Feedback Equalizer (DFE) capable of preventing incremental increases of a jitter of a recovered clock and reduction of a voltage margin of decided data due to delay of feedback data. The DFE includes a combiner for combining received data with feedback data and outputting the combined data as equalization data, a decision circuit for deciding recovery data by receiving the equalization data, a feedback loop for supplying the recovery data to the combiner as feedback data and a clock recovery circuit for removing a delay data component from the equalization data through the feedback loop, recovering a clock with respect to the other equalization data except the delay data component and supplying the recovered clock for decision operation of the decision circuit.

Abstract: Exemplary techniques for turning off the clock signal to flip flops are described, which may reduce power consumption by electronic devices. In an implementation, a clock-gating logic turns off the clock signal to a flip flop when a data input of the flip flop remains untoggled. The reduction in power consumption is envisioned to also reduce heat generation.

Abstract: A clock generating device includes: a DDS circuit that generates a periodic signal; and a comparator that compares an input signal and a reference signal and outputs a binary signal. The clock generating device includes a rate-of-change correcting unit that applies correction for increasing a rate of change at a crossing point with the reference signal to the periodic signal generated by the DDS circuit.

Abstract: In forming a frequency synthesizer by using PLL using processing of digital signals, an A/D converting unit is not required. By the integration of a digital value that depends on a set frequency, a saw-tooth wave serving as a phase signal is generated. A frequency signal output from a voltage-controlled oscillator is input via a frequency divider to an edge detecting unit, which then detects a rising edge or a falling edge of the frequency signal to generate a rectangular-wave signal that depends on a frequency of the frequency signal. Then, a latched circuit latches a value of the saw-tooth wave in response to the rectangular-wave signal, and this value is integrated in a loop filter and the resultant is used as a control voltage of the voltage-controlled oscillator.

Abstract: One of the advantages of direct frequency synthesis technique (e.g., flying-adder architecture) is its capability of generating arbitrary frequency by utilizing the time-average-frequency concept. In the clock output of the direct frequency synthesizer, instead of one type of cycle, there are two types of cycles. Unlike the conventional one-type-cycle clock wherein clock energy is concentrated at its designed frequency, Time-Average-Frequency based clock spreads some of its energy into spurious tones, which could be harmful to certain applications. The spurious tones are caused by the periodic carry sequence generated from a fractional part accumulator inside the frequency synthesizer. The invention suggests a method and an apparatus to break this periodicity and convert the spurious tones into broadband noise.

Abstract: A semiconductor device having an on-chip voltage regulator to control on-chip voltage regulation and methods for on-chip voltage regulation are disclosed. A semiconductor device includes a circuit positioned between a ground bus and a power bus. A power switch array is positioned between the circuit and one of the ground bus or the power bus to generate a virtual voltage across the circuit. A monitor is positioned between the ground bus and the power bus. The monitor is configured to simulate a critical path of the circuit and to output a voltage adjust signal based on an output of the simulated critical path. A controller is configured to receive the voltage adjust signal and to output a control signal to the power switch array to control the virtual voltage.

Abstract: A programmable Local Clock Buffer has a single inverter between the clock input and the delayed clock output. A transistor switch modulates the single inverter stage between a clock signal transmit state and a non-transmitting state. A combination of delay select bits control the timing of the beginning and ending of the transmit state of the inverter relative to the clock input via the transistor switch.

Abstract: Transmitter device which includes at least: a) one delay line designed to output M signals which are delayed in relation to each other, where M is an integer greater than 1; b) a memory, designed to store at least M digital samples of a waveform, where each digital sample contains N bits, and to output each of the M digital samples successively on N output lines respectively under the control of one of the M delayed signals; and c) a digital-analog converter which includes N inputs linked to N output lines, designed to convert the M digital samples received as input from the N output lines of the memory and to successively output, on an output of the digital-analog converter, each of the M analog converted digital samples which together form an analog signal which is representative of the waveform.

Abstract: A time to digital converter includes: a delay circuit having a plurality of delay stages that delay an input clock signal in multiple stages, at least one of the delay stages being a variable delay stage; a plurality of flip flops that capture outputs of the delay stages corresponding thereto in a one-to-one relation in response to input of a reference signal; an edge detecting circuit that detects changing edges of respective outputs of the flip flops; a counter circuit that counts a number of edges detected by the edge detecting circuit; and a control circuit that controls a delay amount of the variable delay stage according to the number of edges counted by the counter circuit.

Abstract: Provided is a transmitter including a polar modulation circuit which adjusts a timing lag between an amplitude component and a phase component more accurately than a conventional art.

Abstract: To make Flying-Adder architecture even more powerful, a new concept, time-average-frequency, is incorporated into the clock generation circuitry. This is a fundamental breakthrough since it attacks the clock generation problem from its root: how is the clock signal used in real systems? By investigating from this direction, a much more powerful architecture, fixed-VCO-Flying-Adder architecture, is created. Furthermore, based on fixed-VCO-Flying-Adder frequency synthesizer and time-average-frequency, a new type of component called Digital-to-Frequency Converter (DFC) is born.

Abstract: A clock data recovery comprises a phase detector, a phase interpolator, an initial phase detector, and an initial phase decoder. The phase detector receives an incoming data stream and an interpolated clock signal and output an early/late value indicating timing relationship between the incoming data stream and the interpolated clock signal. The phase interpolator receives the early/late signal and at least one reference clock signal and generate an interpolated clock signal considering the early/late value and the at least one reference clock signal. The initial phase detector receives the incoming data stream and output a first data indicating a phase of the incoming data stream. The initial phase decoder receives data indicating a phase of the incoming data stream and select the at least one reference clock signal from a plurality of clock signals considering the data indicating a phase of the incoming data stream.

Abstract: A phase accumulator generates phase data for a direct digital synthesis (DDS) device based on a reference phase to provide analog sinusoidal outputs that are locked to the reference phase and thus phase coherent. The frequency of a sinusoidal DDS output may be controlled by changing a frequency control word (FCW) provided to the phase accumulator without affecting the incrementing reference phase. The sinusoidal DDS output is based on a multiple of the FCW and the reference phase and thus remains locked to the reference phase, providing phase coherency even when the FCW changes to change the frequency.

Abstract: Described is an apparatus that includes a frequency source and a plurality of time domain direct digital synthesizers each having an input connected to an output of the frequency source and an output providing an output frequency signal. A particular time domain direct digital synthesizer includes a sigma-delta modulator that functions as a second order multi-stage noise shaping sigma-delta modulator. In one exemplary embodiment sigma-delta modulator outputs provide a unitary-weighted word used to switch certain unit capacitors that comprise part of a delay modulator to produce a time-varying delay having a time-averaged value that directly corresponds to a binary value appearing on a plurality of phase accumulator outputs.

Abstract: The present invention is related to a digital circuit for use in a mixed-signal circuit.

Abstract: There is provided a digital lock detector and a frequency synthesizer using the same. The digital lock detector includes a comparator unit receiving a plurality of control bits, and generating a bit signal to notice a lock condition of the plurality of control bits; a delay cell block generating a plurality of delay signals based on the bit signal, and outputting a clock signal by combining the bit signal and the plurality of delay signals; and a detection unit detecting a shift time of the clock signal, and generating a lock indication signal according to the detection result.

Abstract: Provided is a waveform generating apparatus that generates a signal having an arbitrary waveform, comprising a waveform memory that stores a plurality of pieces of waveform data that each include a sequence of signal values; a filtering section that (i) reads from the waveform memory a piece of waveform data serving as a basis for a waveform to be generated, from among the plurality of pieces of waveform data, (ii) performs a conversion by filtering the read piece of waveform data to obtain a piece of converted waveform data, and (iii) writes to the waveform memory the piece of converted waveform data; and a waveform output section that reads the piece of converted waveform data from the waveform memory and outputs a signal having a waveform corresponding to the sequence of signal values of the read piece of converted waveform data.

Abstract: A circuit for signal conditioning including a first stage with a digital/analog converter, a second stage with an I/Q-modulator, and at least one third stage with a mixer. Instead of a multiplicity of independent oscillators, a shared oscillator is provided for the first, second, and third stages, from an output signal of which a respective oscillator signal and clock-pulse signal for each stage of the first, second, and third stages is derived. The oscillator signal and respective clock-pulse signal of the oscillator are supplied via a frequency divider to at least one stage of the first, second, and third stages, or the oscillator signal of the oscillator is supplied via a frequency multiplier to at least one stage. Also, the oscillator signal of the oscillator is supplied as a reference signal to a frequency synthesizer of at least one stage of the first, second, and third stages.

Abstract: A semiconductor device comprises synthesized frequency generation logic arranged to receive a reference signal, and to provide an output frequency signal. The synthesized frequency generation logic comprises divider logic arranged to receive the reference signal and to generate a divided signal comprising a frequency with a period equal to N times that of the reference signal. The synthesized frequency generation logic is further arranged to generate the synthesized frequency signal comprising a frequency with a period equal to 1/M that of the divided signal. The synthesized frequency generation logic comprises or is operably coupled to decision logic module and comprises or is operably coupled to a switching logic module such that the decision logic module is arranged to determine whether a near-integer spur arises in using the synthesized frequency signal, and configures the switching logic module to select the synthesized frequency signal in response thereto.

Abstract: There is provided a digital lock detector and a frequency synthesizer using the same. The digital lock detector includes a comparator unit receiving a plurality of control bits, and generating a bit signal to notice a lock condition of the plurality of control bits; a delay cell block generating a plurality of delay signals based on the bit signal, and outputting a clock signal by combining the bit signal and the plurality of delay signals; and a detection unit detecting a shift time of the clock signal, and generating a lock indication signal according to the detection result.

Abstract: A method includes generating a plurality of reference phases of a reference signal and selecting a sub-phase from each of the plurality of reference phases to form a set of selected sub-phases. In the method selecting operates in response to synchronized outputs of a multi-phase phase accumulator that operates synchronously in accordance with one of the sub-phases of the set of sub-phases, and where the outputs of the multi-phase phase accumulator may be synchronized using at least one additional sub-phase.

Abstract: Techniques for synthesizing a signal having a desired frequency from an oscillation signal. In an aspect, a reference signal having a known frequency may be periodically used to determine a ratio between the desired frequency and the frequency of the oscillation signal. The oscillation signal may be decimated by the ratio to generate a synthesized signal having approximately the desired frequency. In an aspect, the decimation may be performed by generating a pulse in response to the output of an accumulator that accumulates in steps of the ratio. To save power, the oscillation signal may be derived from a low-power oscillator, while the reference signal may be turned on only during periodic calibration. Further aspects for improving the frequency accuracy of the synthesized signal are disclosed.

Abstract: The present invention relates to a direct digital frequency synthesizer using a variable sine wave-weighted digital to analog converter with improved size and efficiency and a synthesizing method thereof. The direct digital frequency synthesizer and the synthesizing method thereof are capable of simplifying a configuration for matching output data of a phase accumulator to sine wave amplitude without increase in complexity of a DAC by applying a nonlinear DAC for directly generating a current corresponding to base points with sine weights and a variable sine wave-weighted DAC for generating fine currents to be combined with variable weights based on the base points. Accordingly, it is possible to provide a high quality output, reduce a size and power consumption, and increase a speed.

Abstract: A phase-locked loop circuit comprises a phase error detector for receiving a multi-phase reference signal and a synchronized phase signal of the phase-locked-loop circuit, and for performing a rotational transformation to convert the multi-phase reference signal into two-phase quantities at a synchronous rotation d-q reference frame. A monotonic transfer module receives the two-phase quantities, and generates a monotonic phase error signal which is monotonic when a phase difference between the multi-phase reference signal and the synchronized phase signal ranges from ?180 degrees to 180 degrees. A regulator receives the monotonic phase error signal, and generates a synchronized rotation frequency. An integrator receives the synchronized rotation frequency, and generates the synchronized phase signal.

Abstract: Generation of multiple clocks having a synchronized phase relationship may reduce the size, complexity, power consumption, jitter and cost of circuitry while improving its functionality, performance, reliability and fault coverage. A multiple frequency clock generator may comprise an independent digital control oscillator (DCO) for generating a first clock and dependent DCOs for generating additional clocks that align at a common multiple frequency with the first clock with or without adjustment thereof. The independent and dependent DCOs may generate the first and additional clocks from a delay lock loop (DLL) by selecting a sequence of tap select signals. Tap select signals may be adjusted to maintain a desired phase and/or frequency of the first and additional clocks. Dependent DCOs may generate sequences of tap select signals based on the sequence of tap select signals generated by the independent DCO to incorporate adjustments, e.g., PLL error corrections.

Abstract: A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node.

Abstract: A method includes generating a plurality of reference phases of a reference signal and selecting a sub-phase from each of the plurality of reference phases to form a set of selected sub-phases. In the method selecting operates in response to synchronized outputs of a multi-phase phase accumulator that operates synchronously in accordance with one of the sub-phases of the set of sub-phases, and where the outputs of the multi-phase phase accumulator may be synchronized using at least one additional sub-phase.

Abstract: There is provided a signal generating apparatus for generating an output signal corresponding to pattern data supplied thereto. The signal generating apparatus includes a timing generating section that generates a periodic signal, a shift register section including a plurality of flip-flops in a cascade arrangement through which each piece of data of the pattern data is propagated sequentially in response to the periodic signal, a waveform generating section that generates the output signal whose value varies in accordance with a cycle of the periodic signal, based on data values output from the plurality of flip-flops, and an analog circuit that enhances a predetermined frequency component in a waveform of the output signal generated by the waveform generating section.

Abstract: A digital frequency synthesizer can be implemented with single source design, a multiplexer design, a fractional divider design, or a frequency multiplier and frequency divider design. Implementations can utilize a controller dithering circuit or a delta-sigma modulator. The frequency synthesizer can be implemented in a CMOS structure and can utilize a clean up phase locked loop (PLL).

Abstract: A frequency synthesizer includes first and second frequency dividers for receiving and frequency-dividing a signal generated by a voltage-controlled oscillator, a frequency mixer for mixing output signals of the first and second frequency dividers, and a third frequency divider for receiving and frequency-dividing a signal having one frequency of two frequencies that are output by the frequency mixer. The first, second third and frequency dividers and the frequency mixer are provided in a feedback loop within a PLL circuit between the voltage-controlled oscillator and the phase comparator. The phase comparator has a first input terminal to which a signal to which a signal that is output by the third frequency divider is input and a second input terminal to which a reference clock signal that is output by a reference signal generator is input. A loop filter supplies the voltage-controlled oscillator with a voltage that is based upon result of the phase comparison by a phase comparator.

Abstract: A frequency synthesizer for a time base generator of a level measuring device which works according to the radar principle, with at least one first output for output of a first frequency signal, with at least one second output for output of a second frequency signal, and with a reference oscillator for producing a reference frequency signal, the first frequency signal and the second frequency signal having a small difference frequency relative to one another, the first frequency signal being producible by interaction of the reference oscillator with a direct digital synthesizer. The first frequency signal and second frequency signal can be generated with especially low noise by the second frequency signal being derived from the reference oscillator without interconnection of a direct digital synthesizer and the direct digital synthesizer being operated such that only a noise spectrum is produced which is at least partially minimized.

Abstract: A method for reducing noise in a frequency synthesizer includes selecting a design variable k, calibrating a feedback time delay (Td), such that Td=kTVCO, where TVCO is the period of the synthesizer output signal. The method further includes estimating an instantaneous quantization error to a number of bits equal to q, defining a reference bias current of Icp/(k2q), where Icp is a charge pump current signal, and applying the estimated instantaneous quantization error to a current array to produce a down modification signal (?I). The current array is biased by the reference bias current. The down modification signal (?I) is summed with the charge pump current signal Icp to modulate a down current portion of the charge pump current signal Icp.

Abstract: A balanced input inverter circuit includes a first P-type MOS transistor including a gate terminal connected to an input, a source terminal connected to a first power source potential, and a drain terminal connected to an output, a first N-type MOS transistor including a gate terminal connected to the input, a drain terminal connected to the output, and a source terminal connected to a second power source potential, a first inverter circuit including an input terminal connected to an inverted input, and an output terminal connected to a back gate terminal of the first N-type MOS transistor, a first diode connected between the first power source potential and a first power source terminal of the first inverter circuit, a second inverter circuit including an input terminal connected to the inverted input, and an output terminal connected to a back gate terminal of the first P-type MOS transistor, and a second diode connected between the second power source potential and a second power source terminal of the sec

Abstract: A digitally controlled frequency generator includes an oscillator module for generating a first clock signal having an oscillating frequency, a programmable control module operable so as to generate a control signal corresponding to a desired frequency, and a direct digital frequency synthesizer coupled to the oscillator module and the programmable control module for receiving the first clock signal and the control signal therefrom, and for generating a second clock signal having the desired frequency based on the first clock signal from the oscillator module and the control signal from the programmable control module.

Abstract: To provide a synthesizer module that can be used not only in a destination area but also in the whole world and that can be readily set in output frequency. In the synthesizer module, a calculation formula table of a nonvolatile memory stores a plurality of frequency modes and the calculation formula of carrier frequencies corresponding to those frequency modes, and further stores, in its certain area, a frequency mode set during an initial setting of the device. A CPU, when receiving a channel number from a rotary SW during a frequency setting, calculates, based on a calculation formula corresponding to a currently set frequency mode, a carrier frequency corresponding to the channel number. This carrier frequency is set to a CONT of a PLL part.

Abstract: There is provided a digital lock detector and a frequency synthesizer using the same. The digital lock detector includes a comparator unit receiving a plurality of control bits, and generating a bit signal to notice a lock condition of the plurality of control bits; a delay cell block generating a plurality of delay signals based on the bit signal, and outputting a clock signal by combining the bit signal and the plurality of delay signals; and a detection unit detecting a shift time of the clock signal, and generating a lock indication signal according to the detection result.

Abstract: An apparatus for clock generation is presented. In one embodiment, the apparatus comprises a phase interpolator that generates an output with a phase value within reference phases associated with two input clocks. Logic units are coupled to determine a number of phase settings for the phase interpolator. A divider is coupled to the phase interpolator to generate an output clock based on a modifiable divider setting.

Abstract: A digital waveform synthesiser (1) is implemented as a single chip integrated circuit on a single chip (2) and comprises a direct digital synthesiser (10) which produces a synthesised output signal waveform on an output terminal (4) which is substantially phase and frequency locked to the phase and frequency of an externally generated input signal applied to an input terminal (5).

Abstract: Some embodiments include an output driver having a first circuit to provide a plurality of first parallel circuit paths between an output node and a first supply node, a second circuit to provide a plurality of second parallel circuit paths between the output node and a second supply node, and a control circuit responsive to a voltage at the output node to vary a value of a current in the plurality of first parallel circuit paths and a value of a second current in the plurality of second parallel circuit paths to control a signal shape of the output signal. Additional apparatus, systems, and methods are disclosed.

Abstract: A digital frequency synthesizer and a method thereof are provided. In the digital frequency synthesizer, a plurality of multiphase signals (MPSs) is generated by a phase delay locked loop array, and a transition reference values is generated by a programmable transition value generator. An operation result obtained according to an input signal and an accumulated value is compared with the transition reference values to generate a phase selection control signal. A phase signal is selected among the MPSs according to the phase selection control signal. After that, a sampling control is performed to the selected phase signal to generate a synthetic signal. The digital frequency synthesizer and the method thereof are flexible and are easy to produce tiny analytic phase, thus, not only fine tuning phases is added but also the resolution of the synthetic signal is improved.

Abstract: A waveform generator includes a plurality of delay elements such as in a delay line circuit of a free-running oscillator, phase locked loop (PLL) circuit or delay locked loop (DLL) circuit, an algebra module, a switching module and an output module. The oscillator includes a plurality of delay elements and a plurality of taps disposed between the delay elements, with each tap providing a uniquely phased, oscillating transition signal. The algebra module includes an algebra data input port, a clock input port and an algebra data output port. The algebra module generates a signal at the algebra data output port indicating a first rising edge of the arbitrary waveform in response to a signal received at the algebra data input port. The switching module includes a switch input port in electrical communication with the algebra data output port, a plurality of switch tap input ports in electrical communication oscillator taps and switch output port.