Abstract: A phase alignment architecture enhances the performance of communication systems. The architecture aligns a divided clock (e.g., in differential Inphase (I) and Quadrature (Q)) to a main clock, even at extremely high speeds, where skew variations of the divided clock are comparable to the main clock period. The improvement in phase alignment facilitates ultra high-speed communications.

Abstract: A method and/or computer for a tuned spin count in a multithreaded system determines a re-calculation time interval at which to re-calculate a current spin lock value. Then, a spin-lock-re-calculation is repeatedly executed at the re-calculation time interval to perform: observing a current environment of the multithreaded system, determining, using a second-order tuning and values of the current environment, a dynamically calculated heuristic to provide the newly-recalculated spin lock value, and memorizing the newly re-calculated spin lock value, in a memory, as the current spin lock value. Meanwhile, thread(s) in the multithreaded system which want to execute a spinlock will obtain the current spin lock value which is memorized in the memory, and execute the spin lock using the current spin lock value to set a length of the spin lock.

Abstract: A processing-efficient chirp generator that allows flexibility in controlling phase, frequency and slope, i.e., rate of change of frequency. In one embodiment, a fine phase propagation block generates phase values in increments of the fine time step, each phase value also offset from other phase values by multiples of a coarse time step. The phase samples are realigned in time after conversion to digital-to-analog converter (DAC) values.

Abstract: A method and apparatus for operating an electronic device is provided. The electronic device, which includes a phase lock loop (PLL) receives sensor indicators from at least one sensor. Upon receiving sensor indicators, the device identifies a motion indicator based on the sensor indicators. A parameter of the PLL is adjusted based on the motion indicator, the PLL having at least one component susceptible to microphonics. When the PLL includes a charge pump, a parameter that may be adjusted is a pump current of the charge pump. When the PLL further comprises an oscillator for generating a reference signal, the parameter that may be adjusted is a trim of the oscillator.

Abstract: An adaptive clock generation circuit for synthesizing Time-Average-Frequency in dynamic fashion includes (a) a timing circuit for generating a base unit of fixed time span, (b) a control circuit that takes inputs from a microelectronic system wherein the control circuit and the clock generation circuit reside, for generating a update signal and a frequency control word, (c) a direct period synthesizer for generating a plurality of types of pulses by utilizing said base unit and the frequency control word, for creating a segment of a clock pulse train by connecting electrical pulses in series that are selected from said plurality of types according to the update signal, for creating the entire clock pulse train by connecting said segment in series. The resulting Time-Average-Frequency of the clock pulse train matches a selected frequency that is required by the operation of the microelectronic system wherein the clock generation circuit resides.

Abstract: The invention describes methods and systems for digital synthesis of electric signals. According to the invention, one or more bit-patterns are provided, each indicative of a rectangular waveform having a characteristic frequency. Further to determining a selected signal frequency to be synthesized, a selected bit-pattern associated therewith is obtained. Bits of the selected bit-pattern are cyclically serialized to generate a substantially rectangular waveform signal comprising the characteristic frequency. Then, the signal is filtered to suppress spurious frequencies outside a certain unfiltered frequency band which corresponds to the selected bit-pattern to thereby obtain a filtered signal with prominent frequency component corresponding to the selected signal frequency.

Abstract: A digital-to-analog conversion apparatus to convert a digital signal to an output analog voltage signal includes an analog-to-digital conversion processing circuit and an analog voltage signal output circuit. The analog-to-digital conversion processing circuit is configured to increase a resolution of the digital-to-analog conversion apparatus without increasing a frequency of an input clock signal. The analog voltage signal output circuit is configured to generate the output analog voltage signal based on the input clock signal at the increased resolution of the digital-to-analog conversion apparatus.

Abstract: A digital/analog converter (30) with a first return-to-zero unit (311) which is connected to a first busbar (321), wherein the first busbar (321) is connected in each case to a first output of several differential units (351, 352, 35n). In this context, the first return-to-zero unit (311) provides at least one clock input which is directly or indirectly connected to a first photodiode, wherein the first photodiode is fed from a pulsed light source (5).

Abstract: A transmission line driver and a method for driving the same are provided, in which a composite current source is provided as an input current source, such that an output voltage is fixed. The composite current source includes an internal current source and an external current source. The composite current source is supplied to a single-ended transmission line driver or a differential transmission line driver, such that the output voltage is fixed.

Abstract: A semiconductor device includes: a plurality of target lines to be driven; a plurality of target line drivers configured to drive the corresponding target lines in a logic level corresponding to a plurality of target line selection signals; a plurality of booster enable units configured to generate a booster enable signal by sensing whether a group of target lines that is obtained by grouping the target lines by a predetermined number is enabled or not; and a plurality of self-boosters configured to boost corresponding target lines by sensing levels of the corresponding target lines in response to the booster enable signal.

Abstract: This disclosure is directed to devices, integrated circuits, systems, and methods for implementing an internal body tie bias circuit in a CMOS logic circuit. In one example, a CMOS logic circuit is formed in an integrated circuit. The CMOS logic circuit includes a PMOS transistor, an NMOS transistor; and a body tie bias circuit formed in the integrated circuit. The body tie bias circuit is coupled between a body tie connection terminal of the PMOS transistor and a body tie connection terminal of the NMOS transistor.

Abstract: There is described a time-to-digital conversion scheme using an arrangement of delay elements based Time-to-Digital Converter, TDC (20), wherein dithering is built in the digital domain and introduced in the analog domain as a modulation of a supply voltage (TDC-supply) supplying delay elements of the TDC, each having a propagation delay which exhibits a dependency to their supply voltage.

Abstract: A system, method, and computer program product for converting a design from edge-triggered docking to two-phase non-overlapping clocking is disclosed. The method includes the steps of replacing an edge-triggered flip-flop circuit that is coupled to a combinational logic circuit with a pair of latches including a first latch circuit and a second latch circuit and determining a midpoint of the combinational logic circuit based on timing information. The second latch circuit is propagated to a midpoint of the combinational logic circuit and two-phase non-overlapping clock signals are provided to the pair of latches.

Abstract: A variable frequency synthesizer and method of outputting the variable frequency is disclosed. The synthesizer comprises a first reference frequency, a direct digital synthesizer (DDS) receiving the first reference frequency and outputting a tuned frequency, a variable frequency comb generator receiving the tuned frequency and outputting a variable frequency comb comprised of a plurality of comb lines, a mixer receiving the variable frequency comb and a signal from an oscillator and outputting an intermediate frequency, a phase lock loop (PLL) receiving a second reference frequency and the intermediate frequency and outputting a phase lock signal, and the oscillator receiving the phase lock signal and outputting a variable synthesized frequency.

Abstract: A DDS achieved in size and cost reductions by removing a ROM for storing a table and the like and suppressing an operation amount is provided. A DDS includes an NCO, a DAC, and a BPF. The NCO outputs a sawtooth wave. The DAC converts either one of the sawtooth wave outputted from the NCO and a triangle wave signal converted by a waveform converting circuit based on the sawtooth wave, from a digital signal into an analog signal. The BPF receives the signal converted into the analog signal by the DAC and extracts a sine wave at a predetermined frequency from the inputted signal, by allowing a signal at a frequency within a fixed range to pass therethrough.

Abstract: Disclosed is a frequency synthesizer including first and second shift register circuits 3a and 3b each for outputting PLL setting data on a rising edge of a load enable signal, first and second fractional modulators 4a and 4b each for generating dividing number control data on the basis of the PLL setting data in synchronization with a reference signal, and first and second fractional PLL synthesizers 5a and 5b each for generating a high frequency signal according to the PLL setting data, the reference signal, and the dividing number control data. By controlling the timing of the load enable signal, the frequency synthesizer carries out phase control between the high frequency signals generated by the first and second fractional PLL synthesizers 5a and 5b.

Abstract: A fractional-N frequency synthesizer having an exact output frequency and phase includes a phase locked loop including a phase detector responsive to a reference signal and a fractional divider. The phase locked loop has an output signal whose frequency is a fractional multiple of the input reference signal. The synthesizer also includes a modulator having a modulus for providing an output to the fractional divider, in which the modulus multiplied by the ratio of the frequency of the output signal to the frequency of the reference signal is a non-integer number.

Abstract: An electronic device for synthesizing a frequency is provided. The electronic device includes a bank changer configured to output a channel code corresponding to a reference frequency signal and a feedback frequency signal, a channel code mapper configured to generate a changed channel code by applying an offset to the channel code output from the bank changer, and a voltage controlled oscillator configured to control a total capacitance of a plurality of capacitors based on the changed channel code and to oscillate a frequency dependent on the total capacitance.

Abstract: Direct digital frequency synthesis is the process by which a digital frequency synthesizer component may output a stable, precise clock frequency at any of a broad range of possible frequency output values for any number of applications, usually across an integrated circuit. The digital frequency synthesizer set forth in this disclosure is a combination of a controller configured to receive a frequency control word and generate a first frequency control sub-word and a second frequency control sub-word based on the frequency control word, a frequency generator configured to generate a source frequency within a first predetermined frequency range based on the first frequency control sub-word, and a variable frequency divider configured to generate an output frequency within a second predetermined range based on the second frequency control sub-word and the source frequency.

Abstract: A method for reducing signal edge jitter in an output signal from a numerically controlled oscillator includes processing an input signal with a first accumulator to provide a first accumulator output signal and continuing to use a carry in the processing of the input signal with the first accumulator in the event of an overflow. The method further includes processing the input signal with a second accumulator to provide a second accumulator output signal and rejecting a carry in the processing of the input signal with the second accumulator in the event of an overflow. The method further includes outputting the second accumulator output signal at an output of the numerically controlled oscillator and synchronizing the second accumulator using the first accumulator output signal.

Abstract: A frequency synthesizer includes an oscillator for providing an RF clock, a phase shifter arranged to provide a shifted reference clock by changing phase of a frequency reference clock, and a time-to-digital converter (TDC) for producing a digital TDC output by quantizing a time difference between said RF clock and said shifted reference clock; wherein a range of said TDC covers significantly less than a full range of said RF clock period. An associated method is also provided.

Abstract: A clock regeneration circuit includes: a signal input terminal; a D flip-flop circuit; a reset signal generation circuit; a delay circuit; a comparator; a first capacitor; and a feed back circuit. The signal input terminal is inputted with a pulse width modulation signal. The D flip-flop circuit includes a clock terminal, an output terminal, and a reset terminal. The reset signal generation circuit is configured to input a reset signal generated in synchronization with the pulse width modulation signal to the reset terminal at a first time. The delay circuit is configured to delay the pulse width modulation signal. The feedback circuit includes a current source having a control terminal. The feedback circuit is configured to change one of charge rise time and discharge fall time in response to the signal of the comparator to control duty cycle of the signal of the comparator.

Abstract: Supply voltage sequencing circuitry includes a first sequencer (10-1) that produces an active level of a Power Good signal PG if a first supply voltage VOUT1 exceeds an upper threshold V90% while a control signal EN_PG is active, and produces an inactive level of PG if EN_PG is inactive. The PG level is latched when a control signal EN is inactive. A Power Down signal PD is produced if VOUT1 is less than a lower threshold V10% while EN is inactive. An active level of PD is produced when EN is active. A power-up sequence of supply voltages VOUT1, VOUT2, and VOUT3 monitored by the first sequencer and similar second (10-2) and third (10-3) sequencers, respectively, is determined by connection of PG of each of the first and second sequencers to control the supply voltage monitored by the next sequencer.

Abstract: Process, voltage and temperature corners of an on-chip device under calibration are obtained by comparing the outputs of different on-chip components such as active on-chip components and passive-on chip components in response to an input. A first on-chip delay line including a number of active devices, which generate an array of outputs D[ ]) at different stages of the delay. A second on-chip delay line generates a single output (CLK). A DFF array samples the array of outputs (D[ ]) with the single output clock CLK. The different delay variations in different process and temperature corners cause different outputs from the DFF array. The different outputs from the DFF array provide information about the process and temperature corner that can be for rapid calibration of the on-chip device under calibration within one cycle of the CLK.

Abstract: A method of estimating mismatches of a time-to-digital converter (TDC) includes: capturing phase error samples; calculating difference between the phase error samples and an expected value of the phase error samples; and adjusting correction gain of the TDC based on the calculating step. Another method of estimating mismatches of a TDC includes: capturing TDC output code samples; storing a plurality of accumulation values corresponding to different TDC values respectively, wherein each accumulation value records a number of times a TDC value is carried by the TDC output code samples; calculating a desired value based on the accumulation values; calculating difference between the accumulation values and the desired value; and adjusting correction gain of the TDC based on the calculating step.

Abstract: Disclosed is a frequency synthesizer including first and second shift register circuits 3a and 3b each for outputting PLL setting data on a rising edge of a load enable signal, first and second fractional modulators 4a and 4b each for generating dividing number control data on the basis of the PLL setting data in synchronization with a reference signal, and first and second fractional PLL synthesizers 5a and 5b each for generating a high frequency signal according to the PLL setting data, the reference signal, and the dividing number control data. By controlling the timing of the load enable signal, the frequency synthesizer carries out phase control between the high frequency signals generated by the first and second fractional PLL synthesizers 5a and 5b.

Abstract: A frequency synthesizer for generating a low noise and low jitter timebase of a reference signal generates first and second output signals a difference frequency that is low enough for use in sub-scanning is implemented with a first incrementer, having a preset increment and a preset end value E1 controlling a first fractional divider and a second incrementer having a preset increment and a present end value E2 controlling a second fractional divider, wherein each of the incrementers is clocked from the output signal of each fractional divider so that, when the end value E1, E2 is reached, an end signal is output and the incrementers are reset to a carryover value as a new starting value and the end signal is switched between the division factors of the fractional dividers so that the switching sequence of the end signal is periodic with the output signals of the fractional dividers.

Abstract: In forming a frequency synthesizer by using PLL using processing of digital signals, an A/D converting unit is not required. By the integration of a digital value that depends on a set frequency, a saw-tooth wave serving as a phase signal is generated. A frequency signal output from a voltage-controlled oscillator is input via a frequency divider to an edge detecting unit, which then detects a rising edge or a falling edge of the frequency signal to generate a rectangular-wave signal that depends on a frequency of the frequency signal. Then, a latched circuit latches a value of the saw-tooth wave in response to the rectangular-wave signal, and this value is integrated in a loop filter and the resultant is used as a control voltage of the voltage-controlled oscillator.

Abstract: The present invention discloses a noise filtering fractional-n frequency synthesizer and an operating method thereof. The noise filtering fractional-n frequency synthesizer comprises a filter, a frequency calibration loop, a phase calibration loop and a digitally controlled delay line. The filter receives a first frequency division signal and generates a filtered signal. The frequency calibration loop is coupled to the filter and generates a first control signal. The phase calibration loop is coupled to the filter and the frequency calibration loop, and generates a second control signal. The digitally controlled delay line is coupled to the phase calibration loop and receives the second control signal. Thus, quantization noise of the fractional-n frequency synthesizer can be reduced, and phase noise of the fractional-n frequency synthesizer can be improved. In addition, the system remains locked after the filter outputs the signal.

Abstract: A switching control circuit controls a switching circuit based on decoded signals obtained by decoding several input signals. The switching control circuit is includes a decoder circuit that outputs decoded signals obtained by decoding coded input data signals. The switching control circuit includes a driver circuit that generates control signals for controlling the switching circuit based on the decoded signals. The switching control circuit is provided with a synchronous control circuit that synchronizes the input signals before outputting them for decoding.

Abstract: A method for reducing spurious for a clock distribution system, the method including a) providing a system controller, b) providing clock distribution system, c) inputting characteristics of the clock distribution system in advance of operation thereof, d) calculating an expected level of the integer boundary spurious as a function of a fractional offset value, e) selecting an integer boundary solution based on the fractional offset value being within a preferred predetermined region, and f) programming the master clock subsystem and the one or more fractional synthesizers with the integer boundary solution, and g) repeating steps d) through f) as needed.

Abstract: A method for reducing noise in a frequency synthesizer includes selecting a design variable k, calibrating a feedback time delay (Td), such that Td=kTVCO, where TVCO is the period of the synthesizer output signal. The method further includes estimating an instantaneous quantization error to a number of bits equal to q, defining a reference bias current of Icp/(k2q), where Icp is a charge pump current signal, and applying the estimated instantaneous quantization error to a current array to produce a down modification signal (?I). The current array is biased by the reference bias current. The down modification signal (?I) is summed with the charge pump current signal Icp to modulate a down current portion of the charge pump current signal Icp.

Abstract: Locked loops, delay lines, delay circuits, and methods for delaying signals are disclosed. An example delay circuit includes a delay line including a plurality of delay stages, each delay stage having an input and further having a single inverting delay device, and also includes a two-phase exit tree coupled to the delay line and configured to provide first and second output clock signals responsive to clock signals from inputs of the delay stages of the plurality of delay stages. Another example delay circuit includes a delay line configured to provide a plurality of delayed clock signals, each of the delayed clock signals having a delay relative to a previous delayed clock signal equal to a delay of a single inverting delay device. The example delay circuit also includes a two-phase exit tree configured to provide first and second output clock signals responsive to the delayed clock signals.

Abstract: A frequency synthesizer includes an oscillator for providing an RF clock, a phase shifter coupled to said oscillator for providing a shifted RF clock by changing phase of said RF clock, and a time-to-digital converter (TDC) coupled to said phase shifter for quantizing a time difference between a frequency reference clock and said shifted RF clock, wherein a range of said TDC covers significantly less than a full range of said RF clock period. An associated method is also provided.

Abstract: The invention describes methods and systems for digital synthesis of electric signals. According to the invention, one or more bit-patterns are provided, each indicative of a rectangular waveform having a characteristic frequency. Further to determining a selected signal frequency to be synthesized, a selected bit-pattern associated therewith is obtained. Bits of the selected bit-pattern are cyclically serialized to generate a substantially rectangular waveform signal comprising the characteristic frequency. Then, the signal is filtered to suppress spurious frequencies outside a certain unfiltered frequency band which corresponds to the selected bit-pattern to thereby obtain a filtered signal with prominent frequency component corresponding to the selected signal frequency.

Abstract: A first plurality of clock signals including a first clock signal and a second clock signal is received, the first and second clock signal out of phase with each other. A second plurality of clock signals comprising a third clock signal and a fourth clock signal is received, the third and fourth clock signals out of phase with each other. A plurality of enable signals are received. A fifth clock signal is determined based on the first plurality of clock signals and the plurality of enable signals. A sixth clock signal is determined based on the second plurality of clock signals and the plurality of enable signals. A seventh clock signal is determined based on the fifth clock signal and the sixth clock signal.

Abstract: A frequency synthesizer generates a wide range of frequencies from a single oscillator while achieving good noise performance. A cascaded phase-locked loop (PLL) circuit includes a first PLL circuit with an LC voltage controlled oscillator (VCO) and a second PLL circuit with a ring VCO. A feedforward path from the first PLL circuit to the second PLL circuit provides means and signal path for cancellation of phase noise, thereby reducing or eliminating spur and quantization effects. The frequency synthesizer can directly generate in-phase and quadrature phase output signals. A split-tuned ring-based VCO is controlled via a phase error detection loop to reduce or eliminate phase error between the quadrature signals.

Abstract: Systems, methods, and circuits provide a digital frequency synthesizer where the output of the frequency synthesizer is a fractional factor of an input signal frequency. The digital frequency synthesizer may comprise a time to digital converter. A ramp offset signal may be added to the output of the time to digital converter. The ramp offset signal may be added to the output of a TDC until a reference dock signal reaches a value of pi. At such a point, the reference clock signal may be switched and the ramp offset signal may be restarted. As such, a frequency offset may be introduced at the input of the time to digital converter where the frequency offset may be modified by changing the slope of the ramp offset signal.

Abstract: Systems, methods, and circuits provide a digital frequency synthesizer where the output of the frequency synthesizer is a fractional factor of an input signal frequency. The digital frequency synthesizer may comprise a time to digital converter. A ramp offset signal may be added to the output of the time to digital converter. The ramp offset signal may be added to the output of a TDC until a reference dock signal reaches a value of pi. At such a point, the reference clock signal may be switched and the ramp offset signal may be restarted. As such, a frequency offset may be introduced at the input of the time to digital converter where the frequency offset may be modified by changing the slope of the ramp offset signal.

Abstract: There is provided a signal generator outputting an analog frequency signal based on a digital value according to a set frequency, which provides excellent noise characteristics, requires no ROM table corresponding to waveform data, and has a simple configuration. A digital signal having a digital value according to a set frequency is integrated to generate a waveform in a sawtooth shape, a waveform in a triangular wave shape is generated based on the waveform, and this waveform output is differentiated and then D/A converted and integrated. A comparator using, for example, the voltage at a midpoint of the triangular wave as a threshold value is used for the integrated output, and a frequency signal of an objective frequency is obtained from the comparator.

Abstract: An output circuit of a charge mode sensor includes a second resistor and an operational amplifier. The second resistor connects an output portion of the charge mode sensor and a ground. The operational amplifier is configured to output a detection signal that varies in accordance with an amount of charge kept in the charge mode sensor. The operational amplifier includes an inverting input portion, a non-inverting input portion, and an output portion. The inverting input portion is connected to the output portion of the charge mode sensor via a sensor cable. The non-inverting input portion is connected to a reference voltage. The output portion is connected to the inverting input portion via a first resistor.

Abstract: Implementations of a high gain range transmitter with variable-size mixers are described.

Abstract: A clock signal generator having first and second coarse delay circuits connected in series delays pulses of a reference signal having period TP to produce pulses of the clock signal. The first coarse delay circuit delays pulses of the reference signal with a delay resolution of TP/N seconds over a range spanning TP seconds to produce pulses of an output signal. The second coarse delay circuit delays pulses of the output signal of the first coarse delay circuit over a range spanning TP seconds with a delay resolution of TP/M seconds to provide pulses of the clock signal with a timing resolution of TP/(M*N) seconds when the integers N and M are relatively prime.

Abstract: Systems and methods for improving the timing alignment of 25% duty cycle non-overlapping waveforms are provided. A representative system includes a waveform synthesizer that generates a plurality of 25% duty cycle input waveforms and inverters that receive the input waveforms at the inputs of the inverters and invert the input waveforms, producing a plurality of inverted waveforms at the outputs of the inverters. The system also includes NOR gates that receive the plurality of inverted waveforms at the inputs of the NOR gates and pass through one of the inverted waveforms at the outputs of the NOR gates responsive to three inverted waveforms of the plurality of inverted waveforms being at logic “0”; and mixers having inputs that receive the pass-through waveform and a first radio frequency (RF) signal, wherein the mixers combine the pass-through waveform and the RF signal into an output signal.

Abstract: A synthesizer including an oscillator for outputting an oscillation signal based on an output signal from a comparator, a frequency divider for dividing a frequency of an output signal from the oscillator based on control from a controller, and a temperature sensor for detecting an error between a preset frequency and a frequency based on a reference oscillation signal. The comparator compares an output signal from the frequency divider with an output signal from a MEMS oscillator and outputs a signal indicating the comparison result to the oscillator. The controller changes the frequency division ratio of the frequency divider based on an output signal from the temperature sensor and changes the frequency division ratio in a state in which the frequency division ratio is kept at the past value. Thus, phase noise deterioration in the synthesizer can be suppressed.

Abstract: A frequency synthesizer for generating a low noise and low jitter timebase of a reference signal generates first and second output signals a difference frequency that is low enough for use in sub-scanning is implemented with a first incrementer, having a preset increment and a preset end value E1 controlling a first fractional divider and a second incrementer having a preset increment and a present end value E2 controlling a second fractional divider, wherein each of the incrementers is clocked from the output signal of each fractional divider so that, when the end value E1, E2 is reached, an end signal is output and the incrementers are reset to a carryover value as a new starting value and the end signal is switched between the division factors of the fractional dividers so that the switching sequence of the end signal is periodic with the output signals of the fractional dividers.

Abstract: It is difficult to implement a conventional phase lock loop circuit in a sink device within an HDMI system because the low frequency input causes the conventional phase lock loop circuit to absorb unnecessary noise during a long waiting period. Therefore, the present invention provides a low jitter clock regenerator comprises: an input clock; a divider to divide said input clock into a slower clock; a phase lock loop circuit to regenerate said slower clock to a reference clock; and a parameter transformer to tune said divider and said phase lock loop circuit to increase the adjustment speed of said phase lock loop circuit. The present invention also provides a method to reorganize parameters in order to create new parameters which are better suitable for a clock recovery circuit in a sink device within an HDMI system.

Abstract: A digital waveform synthesizer (1) is implemented as a single chip integrated circuit on a single chip (2) and comprises a direct digital synthesizer (10) which produces a synthesized output signal waveform on an output terminal (4) which is substantially phase and frequency locked to the phase and frequency of an externally generated input signal applied to an input terminal (5).

Abstract: A frequency synthesizer includes an oscillator for providing an RF clock, a phase shifter coupled to said oscillator for providing a shifted RF clock by changing phase of said RF clock, and a time-to-digital converter (TDC) coupled to said phase shifter for quantizing a time difference between a frequency reference clock and said shifted RF clock, wherein a range of said TDC covers significantly less than a full range of said RF clock period. An associated method is also provided.

Abstract: A frequency synthesizer includes an oscillator for providing an RF clock, a phase shifter arranged to provide a shifted reference clock by changing phase of a frequency reference clock, and a time-to-digital converter (TDC) for producing a digital TDC output by quantizing a time difference between said RF clock and said shifted reference clock; wherein a range of said TDC covers significantly less than a full range of said RF clock period. An associated method is also provided.