Abstract: A direct digital synthesizer capable of generating a desired frequency with small circuitry, low power consumption, and no spurious components. It includes an accumulator for accumulating a frequency control word for each pulse of a clock signal, a D/A converter for converting the accumulation value of the accumulator to an analog voltage, an integrator for smoothing the output of the D/A converter, a comparator for comparing the output of the integrator with a reference voltage, and for producing pulses at timings at which the output of the integrator reaches the reference voltage while the accumulation value of the accumulator is increasing, and a pulse generator for producing pulses in synchronism with the rising edges of the output of the comparator. The output pulses of the pulse generator constitute an output of the direct digital synthesizer.

Abstract: A fractional-N frequency synthesizer comprises a voltage-controlled oscillator (107) for generating an output signal (F.sub.o) in response to a control voltage derived by a digital-to-analog converter (105) from a digital error signal (e). The error signal is derived by a differencing device (103) which subtracts a digital signal (D.sub.o) representing the actuated frequency of the output signal from an input signal (F.sub.d) having the desired frequency for the output signal. The digital signal representing the output signal frequency is derived by a frequency discrimination device (101) which determines the instant frequency of the analog output signal and provides a corresponding digital representation with zero static frequency error. In preferred embodiments, the frequency discrimination device is a delta-sigma frequency synthesizer in combination with a decimator (102). This frequency synthesizer configuration avoids deficiencies due to non-linearity and noise sensitivity of analog phase detectors.

Abstract: A direct digital-to-analog microwave frequency signal synthesizer device which employs both wideband and narrowband direct digital frequency synthesizer (DDFS) circuitry to improve frequency and phase agility, reduce spurious performance, and minimize direct analog circuitry. A clock output having an extremely precise and highly stabilized frequency is fed to the wideband DDFS circuit and to the narrowband DDFS circuit. One or the other is selectively enabled by control logic circuitry. When the former is enabled, precision, high frequency resolution, low spurious, fast frequency switching is achieved at the microwave output. When the latter is enabled, precision, high frequency and phase resolution, low spurious, is achieved, providing frequency chirp, and frequency phase control at the microwave output. The output of the wideband DDFS circuit is processed to reduce the spurious response and up-converted, while the output of the narrow band DDFS circuit is directly up-converted.

Abstract: A voltage-to-frequency converter having an analog-to-digital converter, based on analog components, for converting samples of an analog signal into corresponding digital words and a digital-to-frequency converter, based on digital components, for converting the digital words into a train of pulses having a pulse repetition frequency related to the analog signal. With such an arrangement, the digital-to-frequency converter and the analog-to-digital converter are adapted to operate at different rates. Therefore, the analog-to-digital converter may be optimized at one operating rate while the digital-to-frequency converter is adapted to operate at a higher operating rate and over a wide range of operating rates. This arrangement thereby enables a slower, analog component based, analog-to-digital converter to be used fabricated with CMOS technology along with the higher, variable operating rate, digital component based, digital-to-frequency converter.

Abstract: A frequency synthesizer which uses a direct digital synthesizer (DDS) to generate a highly accurate periodic signal of a frequency selected from a plurality of reference frequencies. The DDS output signal is bandpass filtered utilizing a clean-up phase lock loop (PLL) to produce a spectrally pure reference signal and promote overall fast settling time. A second or primary phase lock loop, having a much faster settling time than the first PLL, adjusts the frequency of the reference signal generated by the clean-up PLL. In one embodiment, the DDS frequency synthesizer has a digital to analog (DAC) converter coupled to the clean-up PLL. Another embodiment uses a modified DDS (without a DAC or lookup table) and feeds the most significant bit (MSB) or overflow bit from the DAC accumulator into the "clean-up" PLL. In both embodiments, the resulting synthesizer has high spectral purity, fine frequency resolution and a fast settling time.

Abstract: A system for synthesizing a waveform includes waveform synthesis circuitry that generates digital data for each of a set of waveform pulses having preselected slopes at zero-crossing. A sequencer tracks the history of information contained in a data signal and selects a sequence of the waveform pulses in response to the history such that the sequence conveys the history of information while minimizing mismatches between the slopes of adjacent waveform pulses in the sequence.

Abstract: An oscillator includes a frequency-controllable clock generator, and a digital oscillator responsive to a clock generated by the clock generator for oscillating a data sequence at a period in proportion to the clock and also discretely controllable in accordance with a frequency switching signal.

Abstract: The object of the present invention is to provide a clock synthesizer IC which can produce clock signals with much lower radiated EMI.

Abstract: A frequency multiplying device which multiplies the frequency of an externally-supplied reference signal PREF includes a digitally-controlled oscillation circuit, which includes a ring oscillator formed of thirty-two inverting circuits in a ring configuration which are adapted to generate sixteen clock signals having a period that is thirty-two times the inversion time of each inverting circuit and a phase interval that is twice the inverting circuit inversion time, and produces an output signal POUT having a period that corresponds to frequency control data CD at a resolution of the phase difference time of the clock signals, a counter/data-latch circuit which counts the clock signal RCK released by the ring oscillator within one period of the reference signal PREF and delivers the frequency control data CD of the count value to the digital oscillation circuit, and a control circuit which controls the operation of the circuits so that the oscillation output signal POUT having the frequency of the reference s

Abstract: An architecture and system for the implementation of an all digital frequency synthesizing system is described. The frequency synthesizing system has a count series retention table that contains a series of count integers that are selected by a count signal that chooses which series of the integers are to be linked to a periodic input reference frequency counter. The periodic input reference frequency counter will count a number of periods of a periodic input reference frequency and when the counter has reached the number of counts that is equal to the number of the count integer, the periodic output frequency will be toggled from logic level to another logic level. A new periodic output frequency period can be chosen by selecting a new series of count integers in the count retention table. This architecture is structured such that it can be implemented in an automated logic design system.

Abstract: A semiconductor memory device capable of reducing a delay in the conversion of an input chip enable signal having a TTL level, providing a quick chip enable access and avoiding an increase in current consumption even when the quick chip enable access is made possible. the semiconductor memory device in one embodiment includes an input buffer outputting a signal having a CMOS level in response to a chip enable signal having a TTL level and having a plurality of transistors whose gate widths am set to first dimensions and a second input buffer activated in response to both an input signal having a TTL level other than the chip enable signal and the signal having the CMOS level and having a plurality of transistors whose gate widths are set to second dimensions smaller than the first dimensions.

Abstract: A frequency synthesizer (100, 500) provides multiple selectable voltage controlled oscillator (VCO) frequency ranges. A VCO control circuit (114) controls the selectable VCO frequency ranges based on lock conditions of selected VCOs within a VCO array (112) or a single variable VCO circuit (502), to provide an extended tuning range to the frequency synthesizer (100, 500).

Abstract: A hybrid frequency synthesizer combining a direct frequency synthesizer and a PLL synthesizer are disclosed. The direct frequency synthesizer includes a first and second phase accumulator, the second phase accumulator inputting K/N phase data and operating at M times faster than the first phase accumulator, a 360 degree detector adding the outputs of the first and second phase accumulators and detecting a point in time at which the added values become 360 degrees, which point in time is provided to the initialization circuit. The initialization circuit initializes the state of the first and second phase accumulators and controls the output timing of the first phase accumulator so as to synthesize the next period of the output frequency at the initialized time. Accordingly, the present invention simplifies the construction, and is economical.

Abstract: A digitally controlled oscillator in a digital phase-locked loop provides an additional output signal which indicates the time difference between clock pulses output from the digitally controlled oscillator and clock pulses of an ideal clock signal of the same average frequency. This additional signal is called a residue signal. This residue signal may then be used to extrapolate or interpolate outputs of continuously variable interpolation or decimation filters using the output clock signal of the digital phase-locked loop generated according to the digitally controlled oscillator. Because the residue signal may be used in interpolation or decimation filters, it is also applicable to analog-to-digital converters, digital-to-analog converters and sample rate converters which use such filters. The digital phase-locked loop circuit is simpler than previous circuits because a conventional overflowing accumulator may be used, which is a first order system, rather than a higher order multi-bit noise shaper.

Abstract: A method for a frequency synthesizer with adaptive loop bandwidth is disclosed, which is adjusted by the improved frequency synthesizer includes a phase-locked loop and a phase-locked loop adjustment circuit. The phase-locked loop has loop characteristics including a loop bandwidth, a natural frequency, a damping factor, and the like. The phase-locked loop adjustment circuit is adjusted in response to a change in output frequency.

Abstract: A semiconductor memory device which is capable of reducing a delay in the conversion of an input chip enable signal having a TTL level, providing a quick chip enable access and avoiding an increase in current consumption despite the quick chip enable access. The semiconductor memory device in one embodiment includes an input buffer outputting a signal having a CMOS level in response to a chip enable signal having a TTL level, and having a plurality of transistors whose gate lengths are set to first dimensions, and a second input buffer activated in response to both another input signal having a TTL level and the signal having the CMOS level, and having a plurality of transistors whose gate lengths are set to second dimensions greater than the first dimensions.

Abstract: A phase-locked loop circuit includes a voltage-controlled oscillator, a pre-scaler, a main counter, a shift register, and a phase comparison section. The oscillation frequency of the voltage-controlled oscillator is controlled on the basis of phase different information. The pre-scaler frequency-divides an oscillation frequency output from the voltage-controlled oscillator by one of frequency division ratios of 1/j (j is a positive integer) and 1/(j+1) which is selected in accordance with an external control signal. The main counter frequency-divides a frequency division output from the pre-scaler by a frequency division ratio of n (n is a positive integer). The shift register generates .alpha. (.alpha. is an integer equal to or larger than two) time series pulse strings which are synchronized with the output from the pre-scaler and have phases sequentially delayed by one period on the basis of a frequency division output from the main counter.

Abstract: A frequency multiplier circuit generates an supplemental high-frequency timing signal from a single, low-frequency current-controlled oscillator (CCO). The current-controlled oscillator (CCO) generates a controlled discharge current and a controlled bias current which are controlled in parallel to substantially eliminate inaccuracies in a characteristic frequency-current curve of the current-controlled oscillator. The frequency multiplier circuit generates a high-frequency timing signal using the digitally-controlled CCO and avoids the usage of a phase-locked loop (PLL) technique. Specifically, a frequency multiplier includes a current-controlled oscillator having a plurality of input lines connected to receive a digital current select signal and having an output terminal connected to carry a timing signal at a current-controlled oscillator frequency f.sub.CCO set in accordance with the current select signal.

Abstract: A timing generating circuit (9) receives a reference signal (f.sub.REF) and an operation control signal (S.sub.0) as inputs and outputs a generation control signal (S.sub.1). The generation control signal (S.sub.1) is inputted to the prescaler (31), the programmable divider (41) and a phase comparator (51). The generation control signal (S.sub.1) goes "H" when the operation control signal (S.sub.0) goes "H" and then the reference signal (f.sub.REF) is counted predetermined times, and a raw signal (f.sub.RAW) is divided to start generating a signal to be measured (f.sub.0) after the generation control signal (S.sub.1) goes "H", so that a phase difference .delta. between the reference signal (f.sub.REF) and the signal to be measured (f.sub.0) at the start is constant irrespective of the timing of the operation control signal (S.sub.0) attaining "H". Accordingly, it is not necessary to set the timing of the operation control signal (S.sub.

Abstract: A frequency synthesizer circuit for the front end of an RF system. The frequency synthesizer uses two pulse-swallow phase-locked loops in a synthesizer architecture that produces an output frequency that is a function of the two reference frequencies used as inputs into the two phase-locked loops. As a result, the frequency synthesizer can be incremented in steps equal to the differential of the reference frequencies of the two phase-locked loops, while the frequency outputs of each of the phase-locked loops can be incremented in much larger steps. This enables the two phase-locked loops to employ relatively large bandwidths, thereby achieving a faster signal lock as well as a better suppression of the voltage controlled oscillator (VCO) phase noise in each loop. The use of a dual loop synthesizer architecture allows for feedback correction of the VCO phase noise outside the loop bandwidth.

Abstract: Within the differential detection demodulator, the received signal is first quantized by a limiter amplifier 10 and then subjected to frequency conversion by a frequency converter 50 including: an exclusive OR element 51; a running average generator 52 consisting of a shift register 53 and an adder 54; and a comparator 55. In response to the output of the frequency converter 50, the phase comparator 60 outputs a relative phase signal representing the phase shift of the received signal after frequency conversion relative to the phase reference signal. The phase comparator 60 includes: an exclusive OR element 61; an absolute phase shift measurement means 62 consisting of an adder 63 and D flip-flop arrays 64 and 65; and a D flip-flop 66 serving as a phase shift polarity decision means.

Abstract: A voltage-controlled phase shift apparatus having an unlimited range for producing an output signal that varies in phase from an input signal by a predetermined phase difference. The phase shift apparatus includes a first delay circuit coupled to receive the input signal, the first delay circuit for outputting a first intermediate signal that is .alpha. degrees out of phase with the input signal, a second intermediate signal that is .beta. degrees out of phase with the first intermediate signal, a third intermediate signal that is 180 degrees out of phase with the first intermediate signal, and a fourth intermediate signal that is 180 degrees out of phase with the second intermediate signal.

Abstract: A phase-locked loop wherein the output signal is effectively sampled at an increased rate from conventional phase-locked loops, allowing for a greater increase in the ratio of the output frequency to the input frequency while reducing the possibility of jitter or failure to lock. Multiple differently phased reference signals and correspondingly phased feedback signals are produced. The comparison of the feedback signals and the reference signals produce multiple error signals which are combined to adjust the oscillation frequency of the voltage-controlled oscillator.

Abstract: The clock generator of this invention includes: an input shutoff control circuit for receiving a base clock and a reference clock and outputting a first signal and a second signal in response to a reset signal, a phase comparator for outputting a phase difference signal indicating a phase difference between the first signal and the second signal; a voltage control oscillator for outputting a frequency variable clock in correspondence with the phase difference signal; and a voltage fixing control circuit for controlling a voltage of the phase difference signal in response to the reset signal, wherein, when the reset signal is in a first level, the input shutoff control circuit: outputs the base clock to the phase comparator as the first signal and outputs the reference clock to the phase comparator as the second signal, and the voltage fixing control circuit holds the voltage of the phase difference signal, and when the reset signal is in a second level different from the first level, the input shutoff control

Abstract: Based on a phase lock loop structure, having a reference signal generator (1), a first phase detector (2), a low pass filter (3), a VCO (4) and a frequency divider (5), in order to achieve a faster channel switching an maintain the design of the filters to be as simple as possible, a second phase detector (6) is provided that receives the reference signal (9) and a second output signal (11) coming from the frequency divider (5) and shifted 90.degree. with respect to its other output signal (10), and that generates a second phase error signal (13), in quadrature with the first phase error signal (12), that is filtered by a second low pass filter (7) thereby generating a second filtered phase error signal (15). The two filtered phase error signals (14,15) are provided to a quadratic correlator (8) whose output is provided to the VCO (4). Its amplitude is proportional to the difference of frequencies between the reference signal (9) and any of the output signals (10,11) from the frequency divider (5).

Abstract: In a digital control pulse generator including a ring oscillator composed of multiple inversion circuits connected in a ring for circulating a pulse, a counter and selectors which turn data of a flip-flop to high when a counted value of the pulse from a terminal of the ring oscillator becomes a value corresponding to ten high order bits of control data, a pulse selector for taking out a clock of the flip-flop from the inversion circuit at the position specified by four bit control data and a delay line and logical product circuit which turn an output signal of the system to a high level for a predetermined time when the output of the flip-flop turns high, a register and adder accumulate the four low order bits of the control data every time the output signal turns high to update the data four bit data. As a result, the ring oscillator may be continuously operated and an oscillation cycle proportional to the control data may be set.

Abstract: A signal source provides an output signal which can sweep over a broad frequency range in a well-controlled manner. The signal source includes a voltage controlled oscillator (VCO) producing the output signal and a waveform synthesizer producing a reference signal. The VCO output signal is phase locked to the reference signal. To make the VCO signal continuously sweep over a broad frequency range, the reference signal sweeps repeatedly over a narrow frequency range. During each sweep of the reference signal, the VCO frequency tracks an integer harmonic of the reference signal frequency. The frequency and phase of the reference signal for each successive sweep are abruptly reset at the beginning of each sweep selected such that the VCO signal frequency locks to another integer harmonic of the reference signal frequency and does not change.

Abstract: A numerically controlled oscillator (10) includes a difference engine (12) that receives a numerator signal (14) and a numerator minus denominator signal (16). The numerator signal (14) and the numerator minus denominator signal (16) represent constant input values for a desired fractional relationship between a sine wave output signal (34) and a sample clock input signal (20) of numerically controlled oscillator (10). The difference engine (12) generates a difference output signal (18) that is received by a phase adder (22) for adding either a one or a zero to a combination of the delta phase input signal (24) and a phase accumulator output signal (26). The difference engine (12) optimally distributes ones and zeros so as to minimize phase jitter in the output signal (34).

Abstract: A synthesizer based upon direct-digital frequency synthesizer techniques of simplistic design and minimized spurious signal levels. The output signals of two frequency hopped direct-digital frequency synthesizers are combined with the resultant signal having a greatly suppressed spurious signal level due to the channel spacing variation of the spur. Alternate embodiments concern the number and functional location of digital-to-analog converters, varying the clock signal and the use of high-pass filters.

Abstract: A digitally-controlled phase-locked loop oscillating circuit includes a signal period detector which detects the period of an input signal. A control data generator generates control data based on this period. The control data is used to drive a variable frequency oscillator which generates an output pulse synchronized with the input pulse. This output pulse is generated by alternately driving a digitally-controlled oscillator with either the most significant bits of the control data, or an increment of the most significant bits of the control data responsive to the least significant bits of the control data. A period divider divides the period of the output pulse and applies it to a phase comparator, which compares its phase with that of the input signal. The control data generator generates the control data responsive to the phase comparison result.

Abstract: A phase-locked loop frequency synthesizer with adjustable frequency has blanking circuits to remove a predetermined number of pulses per second from a signal applied to an associated frequency divider. Each blanking circuit comprises a latch circuit operated by a signal of predetermined latch frequency to disable the associated frequency divider a number of times per second equal to the predetermined latch frequency. A counter circuit coupled to the latch circuit and adjustably set by an associated selector controls the latch circuit and enables the frequency divider said number of times per second after a predetermined number of pulses of a signal supplied to the frequency divider according to the setting of the associated selector. The number of pulses per second removed by the blanking circuit is thus controlled by the setting of the associated selector multiplied by the number of times per second the associated latch circuit is operated.

Abstract: There is disclosed a sine wave generating circuit including a counter (11) for counting clocks (CLK) to provide count results (B0 to B4), a control timing generating circuit (12) for converting the count results (B0 to B4) into switching control signals (D0 to D10), a synchronous circuit (13) for adjusting the timing of the switching control signals (D0 to D10) to provide switching control signals (Q0 to Q10), a weighted resistor voltage-dividing circuit (14) for voltage-dividing potentials V.sub.D2 and V.sub.S2 by means of resistors to transmit the divided potentials sequentially to a low pass filter (15) in accordance with the switching control signals (Q0 to Q10) given from the synchronous circuit (13), and the low pass filter (15) formed of a switched capacitor having a transmission zero point which is a frequency (fCLK) of the clock (CLK). Since the resistors are set such that the divided potentials are values for a sine wave, the sine wave has high accuracy and low distortion factor.

Abstract: A semiconductor memory device which is capable of reducing a delay in the conversion of an input chip enable signal having a TTL level, providing a quick chip enable access and avoiding an increase in current consumption despite the quick chip enable access. The semiconductor memory device in one embodiment includes an input buffer outputting a signal having a CMOS level in response to a chip enable signal having a TTL level, and having a plurality of transistors whose gate lengths are set to first dimensions, and a second input buffer activated in response to both another input signal having a TTL level and the signal having the CMOS level, and having a plurality of transistors whose gate lengths are set to second dimensions greater than the first dimensions.

Abstract: A method for generating a digital sine wave signal having a predetermined sampling rate includes generating a pulse train with an alternating or constant amplitude sign, at a sampling frequency having a predetermined sampling rate frequency divided by 2.sup.n. An envelope curve is generated. The sampling rate is doubled. The doubling of the sampling rate is repeated until generation of a desired sine wave signal in an unfiltered spectrum of the generated signal. Undesired frequency components are filtered out. The sampling rate is optionally re-increased by oversampling a previously generated signal. A circuit configuration for carrying out the method includes a unit for generating digital sampling values. A filter for generating an envelope curve is connected downstream of the unit for generating digital sampling values. Units for raising a sampling frequency are connected downstream of the filter for generating an envelope curve. A digital filter filters the generated digital sampling values.

Abstract: A frequency synthesizer (107) utilizes a variable oscillator (114) the output of which is used as the frequency synthesizer output (115) and is fed to a digital divider (108). The output of the digital divider (108) feeds one input of a phase comparator (109). The other input of the phase comparator (109) is fed from a reference oscillator (116). A phase comparator (109) output controls the variable oscillator (114). The digital divider (108) has a division ratio that is varied with time by a multi accumulator fractional-N division system (112) such that the effective division ratio may be varied by non-integer steps. Due to the time varying division sequence applied to the digital divider (108) there is a residual spurious level on the output signal (115). A second digital sequence from the multiple accumulator fractional. N-division system (112) is generated to reduce this spurious level and is applied to the output of the phase comparator (109).

Abstract: An apparatus (500) for generating first and second output signals having predetermined frequency shifts relative to a frequency provided by a reference signal is included in a system comprising a phase-locked loop (206) coupled to the reference signal for generating the first and second output signals. The apparatus (500) includes pulse deletion circuitry (204) coupled to the reference signal and the phase-locked loop (206) for deleting pulses from the reference signal at a first deletion rate to generate the first output signal and for deleting pulses from the reference signal at a second deletion rate to generate the second output signal.

Abstract: A phase lock loop frequency synthesizer is applied to radio communication devices or the like, in order to reduce frequency error at a time of frequency changing, and considerably reduce a frequency changing time. At the time of frequency changing, a first loop filter performs frequency coarse adjustment, and charges or discharges a capacitor in a second loop filter to voltage corresponding to target frequency. Further, a controller feeds a voltage controlled oscillator with a frequency fine control data so as to output the target frequency, and controls a loop filter in a phase lock loop to be switched over from the first loop filter to the second loop filter.

Abstract: A saw-tooth waveform signal generating circuit (3) generates a saw-tooth waveform signal d in response to a timing signal b derived from a reference clock a. A voltage comparator (4) slices the saw-tooth waveform signal with a reference voltage to shape the waveform thereof, thereby producing a synthesizer output e having a rectangular waveform. A counter (5) adds or subtracts a predetermined value every time a reference clock arrives. The count of the counter (5) is converted to an analog value by a DAC (6) and then is applied to, for example, the saw-tooth waveform signal generating circuit as a bias. As a result, the voltage for causing the saw-tooth waveform signal to start rising or falling is manipulated to allow the voltage comparator to slice the saw-tooth waveform signal at any desired timing. Hence, a synthesizer output can be produced in any desired phase.

Abstract: A frequency synthesizer has the configuration of a phase locked loop (PLL) having a voltage controlled oscillator (VCO) generating an output signal, a phase detector for outputting a control signal to the VCO, and circuitry coupled to an output port the VCO for offsetting the frequency of a sample of the output signal. The synthesizer includes a sampling mixer operative with a source of reference signal and interconnecting the offset circuitry with the phase detector. The sampling mixer mixes the offset sample with the reference signal to output a comb frequency spectrum of signals differing in frequency from each other by multiples of the reference frequency. A filter selects a signal outputted by the sampling mixer at one of the comb frequencies for application to the phase detector. The phase detector is operative with a source of input signal having an input signal frequency for phase locking with the signal selected by the filter.

Abstract: A frequency synthesizer provides a synthesized signal. The synthesizer includes an oscillator that supplies a fast clock signal to a divider programmable by a digital data. The most significant bits of the digital data are provided to the programmable divider, and the least significant bits are provided to an accumulator that cooperates with the programmable divider to increment by one unit its division rank when the accumulator overflows. The synthesizer further includes a generator for generating n increasing delay phases of the synthesized signal; a comparator for comparing the content of the accumulator with n ranges of possible increasing values; and circuits for selecting, as the synthesized signal, the phase whose rank corresponds to the rank of the range within which the content of the accumulator is comprised.

Abstract: A digital pulse shaping and phase modulation network is used for reducing out-of-band spectral energy. This network is used in conjunction with a NCO (numerically controlled oscillator) which includes a linear phase input port. This circuit converts rectangular data pulses into a user programmed shape. The shape pulses are then modulated onto the carrier via the linear phase port. Depending on the preprogrammed pulse shape, the out-of-band spectral energy is significantly reduced.

Abstract: A phase lock loop (PLL) circuit and method in which a PLL circuit locks on a variable input phase by providing an instantaneous phase value of a signal from an oscillator at periodic intervals, and by providing phase corrective signals to the oscillator at the same periodic intervals by comparing an instantaneous value of the variable phase to the corresponding instantaneous value of the oscillator signal phase, the phase corrective signals adjusting the phase of the oscillator signal to the predetermined phase. The PLL circuit may also lock on a predetermined frequency by providing frequency corrective signals until a difference between the predetermined frequency and the frequency of oscillator signal is smaller than a predetermined threshold.

Abstract: A frequency multiplier includes a ring oscillator having a number of logic gates arranged in a plurality of rings. Control inputs enable the selection of individual gates so as to connect them into the ring or, conversely, remove them from the ring. As additional gates are removed, the combined delay imposed by the gates remaining in the ring is reduced and the frequency of the oscillator increases. A variable delay element, preferably a group of tri-state inverters connected in parallel, is connected between two of the gates. The oscillator is fine tuned by controlling the delay inserted by the variable delay element. The frequency multiplier also includes a frequency comparator. A reference frequency is passed through a divide-by-K unit and the output of the ring oscillator is passed through a divide-by-N unit, N being greater than K.

Abstract: An adjustable digital synthesizer has frequency increments of a selected step size. The adjustable digital synthesizer includes a digital accumulator having N stages. The digital accumulator counts at a predetermined clock frequency such that, in response to each clock, the accumulator increments the step size determined by the digital input. The accumulator counts to 2.sup.Nth state and wraps around in response to an overflow. An adder, responsive to the overflow, adds an offset to the accumulator, the offset being a function of the difference between 2.sup.Nth times the minimum step size and the desired clock frequency.

Abstract: A fully-symmetric high-speed CMOS frequency synthesizer which exhibits minimum dead-zone effects is disclosed. A fully-symmetric phase-frequency detector and a fully differential charge-pump filter combined with a voltage-controlled oscillator are key elements of the invention described.

Abstract: A frequency synthesizer for generating a sinusoidal analogue signal comprises a digital signal generator for generating a substantially triangular digital signal. A digital to analogue converter (DAC) receives the digital signal. The DAC has a non-linear transfer function shaped to generate a sinusoidal analogue signal.

Abstract: A novel RS latch for use in asynchronous designs has been provided. The RS latch is made scannable by the use of additional circuitry which provides a basis for a scan chain signal to propagate in and out the scannable RS latch. Such a scannable RS latch greatly facilitates the testing of the asynchronous design.

Abstract: This invention provides for an enabling circuit that ensures a positive turn-on of semiconductor switches configured for the generation of a synthesized waveform, thereby eliminating misfiring of the switches due to electronic noise or logic malfunction. The circuit is configured to separately compare a sample waveform with a positive reference voltage and a negative reference voltage. The two results are directed to separate logic AND gates which have respective control signal inputs that regulate the formation of the positive and negative portion of a synthesized waveform. The output signals from the two AND gates connect to logic means to control the firing of the semiconductor switches.

Abstract: A digital frequency generating device is comprised of a first digital frequency generator which generates a first output signal at a first frequency and a second digital frequency generator which generates a second output signal at a second frequency independent of the first frequency. Both the first and the second frequency generators run continuously and either can be connected to the generating device output by means of a multiplexer. Apparatus is provided to synchronize the two generators so that a continuous phase transition is maintained when the generating device output switches from the first output signal to the second output signal. This arrangement allows the device output to be shifted from a first frequency to a second frequency and then return to the first frequency output while maintaining the phase position of the first frequency output and is particularly useful in nuclear magnetic resonance applications.

Abstract: A synthesized jitter generator employing a novel digital architecture is provided. The apparatus provides period synthesis and controlled sinusoidal and non-sinusoidal jitter modulation functions of a square wave provided at its output. The architecture consists of a coupling of an N+M bit digital accumulator and an N bit synchronous counter to an N bit magnitude compare circuit. The output of the magnitude compare strobes the accumulator when the two inputs are equal in magnitude causing the accumulator to increment synchronously. The output of the magnitude compare is also a digital waveform whose average period is precisely defined by the input word to the accumulator.