Abstract: A method for the control of an electronic circuit of the type includes at least one access pin to receive and/or deliver control signals, includes the generation, in a control unit, of control signals from data elements received serially through a data transfer input/output device. The method also includes the following steps: (1) extracting a control word included in the data received serially; and (2) decoding the control word extracted in the previous step in order to perform an operation, as a function of the value of the control word, thus modifying the logic state of at least one control signal.

Abstract: A method for synthesizing a clock signal, said clock signal being locked to a reference clock signal, said method providing for using a third clock signal, operating at a higher frequency. The method provides the steps of: measuring the reference clock signal (CK_REF) by means of the third clock signal (CK_HIGH), operating at a higher frequency, obtaining a measured value (MES) of the reference clock signal (CK_REF) frequency; comparing the measured value (MES) with a nominal value; obtaining a correction value (CRR) as a function of the measured value (MES) and storing said correction value (CRR); using said correction value (CRR) for driving a digital controlled oscillator (OC) that outputs the synthesized clock signal (CK_SYN).

Abstract: An electronic system, such as a video decoder (80), includes a clock generator circuit (22, 22′) based upon a phase-locked loop (PLL) (25). The PLL (25) includes a voltage controlled oscillator (VCO) (30) that produces a plurality of evenly-spaced output phases, each of a locked frequency relative to a reference clock (CREF). A frequency synthesis circuit (27) receives a frequency selection value on control lines (FREQ) that include an integer and a fraction portion. The integer and fraction portion of the frequency selection value are added to the current contents of a register (40) that stores the previous integer value used to select the corresponding phase from VCO (30) for application to the clock input of a toggle flip-flop (36) from which the output clock (COUT) is generated. Use of the fraction portion permits a time-averaged clock frequency to be produced with more precision than the multiple phases output by the VCO (30).

Abstract: An apparatus according to a preferred embodiment of the present invention includes two memories each storing different octants of a sine (or cosine) waveform. The sine and cosine waveforms may be concurrently generated by alternately accessing each memory in succession. It is unnecessary to access one memory concurrently, so that both waveforms may be concurrently generated without requiring either two accesses to the same memory or a doubled memory size.

Abstract: A method and apparatus for synthesizing high-frequency signals is disclosed that overcomes integration problem associated with prior implementations while meeting demanding phase noise and other impurity requirements. In one embodiment, a phase-locked loop (PLL) frequency synthesizer is disclosed having a voltage controlled oscillator (VCO) with a variable capacitance that includes a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance, and the continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance. In a further detail, wireless communication frequency synthesizer for generating multiple band high-frequency signals is disclosed having a first VCO selectable for a first frequency band and a second VCO selectable for a second frequency band.

Abstract: A switched converter uses two series connected complementary CMOS devices and has a square wave source for activating one CMOS device while deactivating the other; and a break before make circuit connected between the square wave source and said complementary CMOS devices to ensure that one device is substantially completely off before the other device turns on. The switched converter is programmable as to frequency, phase and duty cycle.

Abstract: A signal generator and a method of generating a signal are disclosed that offsets phase and frequency of the output signal relative to the input signal by small increments, providing high resolution. The signal generator utilizes numerically controlled oscillators to instantly and independently offset phase and/or frequency.

Abstract: A digital frequency synthesizer comprises means for the generation of the samples of a digital signal to be converted into an analog signal encoded on N bits as a function of a frequency control word, means for the generation of a noise signal encoded on N bits, and a digital-analog converter, the useful signal and the noise signal being truncated to M bits before being added up by an adder. The result of the addition is converted into analog signal form by the digital-analog converter. The generated noise has at least a noise density substantially equal to a law of equiprobability, this density being zero outside a given space. Application especially to direct digital synthesis, for example in the field of radar techniques or that of instrumentation.

Abstract: A digital phase synthesizer includes a source of successive phase data signals. An interpolator generates successive edge placement data signals in response to each of the successive phase data signals. A phase modulator generates an output clock signal having edges placed at times determined by the successive edge placement data signals. Similarly, a digital phase analyzer includes a source of an serial binary input signal having edges. A phase demodulator generates successive data signals representing the location of each edge of the serial binary input signal. A decimator generates phase data signals at a lower rate than the edges of the serial binary input signal.

Abstract: An inexpensive numerically-controlled fast frequency-hopping microwave synthesizer. A voltage-controlled oscillator (VCO) output phase remains locked to an internal direct digital synthesizer (DDS) reference signal over the entire output frequency band, which is an order of magnitude larger than the internal sampling clock frequency. A “Nyquist-boundary hopping” scheme compares signals from an alias band of the DDS with signals from an alias band of the sampled VCO output to derive an output phase error signal, which is forced to zero in a manner that locks the VCO output phase to the DDS output phase over a frequency hop-distance greater than the DDS bandwidth. Accordingly, in a single second, the synthesizer can hop phase-continuously in a single clock cycle to each of hundreds of thousands of different microwave output frequencies with relatively low clock rates (up to 100 MHz) commensurate with silicon application-specific integrated circuits (ASICs).

Abstract: A frequency correction circuit includes a temperature sensor (100) disposed to measure temperature and produce temperature signals representing sensed temperatures. A data supplier (110) stores information items, receives digital input signals representing and produces a digital output information signal representing an item selected in accordance with the digital input signal. A control circuit (120) receives the temperature signals and receives the digital output information signal. The control circuit (120) produces control signals based on the temperature signals. A clock circuit (150) is disposed to generate a reference frequency signal. A digital synthesizer (130) receives the reference frequency signal and the control signals. The digital synthesizer produces an output frequency signal as directed by the control signals received from the control circuit (120).

Abstract: A frequency synthesizer using a multiphase reference signal source consists of three portions: a basic phase locked loop including a variable frequency oscillator, a loop filter, a phase detector, and a frequency divider; a generating circuit including a multiphase reference signal source for providing a reference signal to the basic phase locked loop; and a frequency discriminator and phase modulator. The frequency discriminator facilitates detection of whether the main loop of the frequency synthesizer is approaching a phase locking state for a proper change of the loop bandwidth. The phase modulator is employed to change the output phase of the reference signal source in order to speed up phase locking and make it applicable to creating signals with a rapid frequency switching speed, frequency tuning capability, and fine channel resolution.

Abstract: A fractional synthesis approach and arrangement are presented which achieve fine frequency resolution with low phase noise while at the same time retaining a high phase comparison frequency/fast frequency changing speed. An output signal having a desired output frequency is generated by a voltage controlled oscillator (VCO). An output divider divides the output frequency by an output divisor N to produce an output pulse train. The output divisor N may be equal to an output integer N or the output integer plus one N+1, for example, and may change during the generation of a single output frequency. For different desired output frequencies, the value of the output integer N may be varied. A reference divider divides a reference frequency by a reference divisor M to produce a reference pulse train. The reference divisor M may be equal to a reference integer M or the reference integer plus one M+1, for example, and may change during the generation of a single output frequency.

Abstract: A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. These signal transitions are counted over a predetermined time period to establish the period of the oscillator. The period of the oscillator is then related to the average signal propagation delay through the test circuit. The invention can be applied to synchronous components that might fail to oscillate by connecting the asynchronous set or clear terminal to the output terminal so that the oscillator oscillates at a frequency determined by the clock-to-out delay of those components.

Abstract: A phase comparator compares the phases of first and second signals with each other. The phase comparator has a first control circuit, a second control circuit, and a phase comparator unit. The first control circuit divides the frequency of the first signal by n in response to a third signal where n is an integer equal to or larger than 2. The second control circuit divides the frequency of the second signal by n in response to the third signal. The phase comparator unit compares the phases of signals provided by the first and second control circuits with each other. The phase comparator unit is capable of correctly comparing the phases of even high-speed signals with each other, and therefore, is applicable to a DLL circuit that operates on high-speed clock signals.

Abstract: A programmable delay generator comprises a first ramp wave generator and a second ramp wave generator, each having the same structure as each other, each of them operating with external common clock pulses, and each of them providing potential gradient and final potential incorporated with an external set data; a comparator for comparing an output (Vs) of the first ramp wave generator and an output (Vk) of the second ramp wave generator so that an output pulse is provided when the outputs of two ramp wave generators coincide with each other; said first ramp wave generator providing a first ramp voltage (Vs) upon receipt of a first set data (S) at a predetermined time (t0); said second ramp wave generator providing a threshold voltage (Vk) upon receipt of a second set data (K) at a time which preceds at least one clock time (T) than said predetermined time (t0); said comparator providing an output pulse delayed by delay time (td) which is proportional to ratio (K/S) of said second set data (K) and said first s

Abstract: A system and method for reducing the computational complexity of the calculations performed by a Numerically Controlled Oscillator (NCO). Through exploitation of mathematical symmetries and other techniques, the size of a lookup table of sinusoidal values employed by the NCO to approximate sinusoids may be reduced by the combination of different frequency shifts.

Abstract: A method and device for frequency synthesizing, in which the digital frequency synthesizer includes a clock pair having two similar ring-oscillators to separately generate a search frequency and an output frequency, a frequency tracking unit, and a clock controlling unit. The frequency-search method includes two stages: one stage is the coarse search stage based on the "Prune-and-Search", and other stage is the fine search stage based on the "fixed-step" algorithm. In order to determine which search scheme is used to search the target frequency and to determine the lock status, two cost functions for search and lock-in are derived. These two cost functions define the search threshold and the lock threshold, and these thresholds define the cost window and the lock window. If the frequency error is higher than both the search and lock thresholds, a coarse search is activated to estimate the correct frequency.

Abstract: In a PLL circuit, a phase comparator compares phases between a data signal train and a regenerated clock generated within the PLL circuit based on a clock with which the data signal train is synchronizing, and outputs a phase error signal. A frequency comparator compares frequencies between the data stream signal and the regenerated clock and outputs a frequency error signal. When the frequency difference between the both is large, only the frequency system loop operates to carry out a frequency pull in operation of the regenerated clock. When the frequency difference becomes smaller than a predetermined value, an operation by the phase system loop is added to carry out a phase pull in operation. When the phase difference becomes a predetermined value, the phase is locked. When the frequency difference exceeds the predetermined value again during the phase locked period, the operation of the phase system loop is suspended and only the frequency system loop carries out the frequency pull in operation.

Abstract: An all-digital frequency synthesizing system that will eliminate spurious frequencies that degrade the overall performance of the generation of a binary waveform. The frequency synthesizing system has a count series retention table that contains a series of count integers that are selected by a count signal that chooses which series of the integers are to be linked to a periodic reference counter. The periodic reference counter will count a number of periods of a periodic reference frequency and when the counter has reached the number of counts that is equal to the number of the count integer, the periodic output signal will be toggled from logic level to another logic level. A new periodic output signal period can be chosen by selecting a new series of count integers in the count retention table. A count compiler will create the series of count integers retained in the count retention table.

Abstract: A digital controlled oscillation circuit which has a wide oscillation frequency range and continuous and smooth transition of the oscillation frequency and can prevent occurrence of jitter: in which provision is made of a first delay circuit for delaying a first signal by a control signal and outputting the same as a first delay signal; a second delay circuit for delaying a second signal by the control signal and outputting the same as a second delay signal; an RS FF which switches a first output signal from low to high and switches a second output signal from high to low and outputs the same when receiving as its input the first delay signal, while switches the first output signal from high to low and switches the second output signal from low to high and outputs the same when receiving as its input the second delay circuit; and first and second switching detection circuits for generating first and second delay circuits when detecting that the first and second output signals switch from high to low.

Abstract: A circuit and method for generating waveforms when synthesizing musical sounds. In one embodiment, the invention provides a multiplexer/shifter which modifies the phase angle input according to the particular waveform desired. Boolean logic gates further modify the multiplexer/shifter output based on the two most significant bits of the phase angle input and according to the particular waveform desired. Finally, a multiplier multiplies the multiplexer/shifter output with the output of the Boolean logic gates to produce the desired waveform. The invention may employ banks of exclusive OR gates and AND gates as the Boolean logic. Another embodiment of the invention provides a waveshaping method where a desired waveform is generated from a phase angle input. The phase angle input is multiplexed/shifted based on the particular waveform desired.

Abstract: A frequency divider includes a mixer having a first input connectable to a reference oscillator and a second input connectable from the reference oscillator through a frequency synthesizer to the second input of the mixer. The mixer provides an output signal to a filter, which provides a frequency divider output. The frequency synthesizer provides an output signal having a frequency of (N+1)/N or (N-1)/N times the input F.sub.IN from the reference oscillator. With the frequency synthesizer providing the signal F.sub.IN (N+1)/N, or F.sub.IN (N-1)/N, the output of the mixer provides the signal having the frequency F.sub.IN /N and can utilize a single filter to eliminate undesired mixer outputs. Further, the frequency synthesizer can be configured to utilize an oscillator which operates over the same frequency range as the reference oscillator.

Abstract: In order to use a digital oscillator to generate a target frequency ZT with a "high" or "low" level constant in time from a working clock by variable division by a first division factor, two divider circuits which can be respectively triggered by the positive or the negative edges of a working clock, and to which a control word can be directed alternately by means of a first controlled switch, and which are connected on their output sides to a second controlled switch to obtain a clock pulse. To that end each divider circuit has a logic module which detects the occurrence of the edge of the control word and stores this event, with this event triggering a division by a second division factor.

Abstract: An improved circuit and technique for obtaining phase-coherent synthesis using a direct digital synthesizer (DDS). In the phase-coherent frequency synthesis device of the invention, a computational engine constructed from a large programmable gate array, a digital signal processing microprocessor, or a number of discrete digital logic blocks generates information sent to the DDS for generating an output frequency, .function..sub.out, which is in phase with all previous outputs of the device at the same frequency.

Abstract: A direct digital frequency synthesizer includes inputs for a reference clock signal and a control word, and an output for a synthesized clock signal. A phase accumulator coupled to the input for the control word and the reference clock signal has an output for a phase control signal. A phase shifter has inputs for the reference clock signal and the phase control signal and an output coupled to the output for the synthesized clock signal. The control word can be used to adjust the output frequency and phase of the synthesized clock signal.

Abstract: A frequency synthesizer comprises a direct digital frequency synthesizer (DDFS), which provides in-phase and quadrature sinewave signals at a preset frequency from digital analogue converters respectively, and a balanced mixer. The balanced mixer provides an output signal having a carrier frequency twice that provided by DDFS and reduced levels of spurious signals. A signal having a desired frequency is generated by controlling the DDFS to generate sinewave output signals at half the desired frequency. The reduced levels of spurious signals obtained by the arrangement allows improved signals for use in, for example, local oscillator applications.

Abstract: A radio-frequency signal generator has a voltage-controlled oscillator for producing a radio-frequency signal. A frequency divider with a fixed division ratio has an input connected to the voltage-controlled oscillator and an output supplying a first clock signal. A first accumulator aggregates a first reference signal under the control of the first clock signal. A second accumulator aggregates a second reference signal under the control of a second clock signal. The aggregated signals are subtracted from one another, filtered through a digital filter, weighted and subsequently converted into an analog signal. The analog signal is filtered by an analog filter and fed to the voltage-controlled oscillator.

Abstract: A method for frequency modulation synthesis and apparatus for performing the method. The method uses additions rather than multiplies and therefore saves the space and cost of multipliers in circuit implementations. The method saves further resources by using the coordinate rotation digital computer (CORDIC) algorithm to acquire sine values as opposed to an extensive sine look-up table. The method can be implemented with either a dedicated digital circuit or a programmed special purpose processor such as a digital signal processor. The hardware for implementing the method is normally integrated onto a semiconductor device.

Abstract: A direct digital synthesizer circuit and method for reducing the harmonic content in a synthesized output signal. The direct digital synthesizer generates first and second address signals driving first and second sine look-up read only memory (sine ROM) circuits. The first and second sine ROMs generate first and second digital sine wave signals which are offset in phase from one another by 180 degrees. The first and second digital sine wave signals are converted to first and second analog sine wave signals. The first and second analog sine wave signals are combined in a subtractor circuit. As a result of the phase relationship between the first and second analog sine wave signals, the fundamental component of these signals are emphasized by subtraction while the second harmonic component of theses signals are simultaneously de-emphasized.

Abstract: In a data synchronization circuit for obtaining a clock synchronized with bits of received data to submit the received data to retiming, it is achieved that a phase synchronization without use of a feedback loop configuration giving rise to oscillations is performed. The received data are devided according to the frequency in a frequency dividing circuit. This frequency divided output and the respective n-phase clocks are compared in phase to generate a specific signal to specify one of n-phase clocks having predetermined phase relations to the frequency divided output. While, on the other hand, the change points of the frequency divided output are synchronized with the extracted clock of a clock selector to average the specific signal with the timing of this change point synchronization signal. One of n-phase clocks is extracted in conformity with the state of this averaged output to make an extracted clock and to subject the received data to retiming in a flip-flop by using this clock.

Abstract: A direct digital frequency synthesizer outputting a sine signal is disclosed, comprising an accumulator, a symmetry circuit, a coarse circuit, a fine circuit and a sign circuit, wherein the accumulator sequentially outputs a sample address according to a frequency control signal. The symmetry circuit takes the complement of the sample address according to a first clock, the period of the first clock being twice the period of the first MSB of the sample address, to obtain a symmetric sample address represented by N bits. The coarse circuit connected to the symmetry circuit outputs the first M MSBs of the symmetric sample address as the first M MSBs of the sine signal. The fine circuit predicts the last N-M LSBs of the sine signal from the last N-M LSBs of the symmetric sample address according to the first M MSBs of the symmetric sample address of the coarse circuit.

Abstract: A direct digital frequency synthesizer featuring an accumulator having a modulo overflow signal addressing a multiplexer. The multiplexer receives a series of delay signals generated from digital circuits. The delay signals establish the phase of a reference oscillator. The number of units of delay are sufficient to resolve expected jitter. The accumulator is a digital counter which increments by only a single digit for each count, such as a Gray code counter. In one embodiment, the delay signals are generated by a charge pump feeding individual logic circuits driving integrated capacitors in a loop. Feedback to the charge pump establishes that the total delay will subdivide a single clock cycle of the reference clock. In a second embodiment, a single shifter or several shifters, with output in phase reversal relation, subdivide a single clock cycle. A clock multiplier and divider are used to assure the synchronism of each clock cycle with the total number of units of delay.

Abstract: The invention concerns a method and apparatus to synthesize a frequency employing digital phase words to represent successive phase values. A digital dither signal generator is used to generate a succession of dither words which are summed with the phase words to form address words. The address words are used to address a store to convert the address words to waveform values. The periodic quantisation noise introduced by the digital process is made more random by means of the dither words thereby reducing the quantisation noise components while accepting an increased total noise power. The synthesizer is of particular advantage when used to generate the reference frequency for a frequency multiplier implemented as a phase lock loop. By making the dither sequence repetition frequency outside the phase lock loop bandwidth, the spurious components are removed from the frequency range of interest.

Abstract: A wave shaping circuit for a semiconductor device testing apparatus reduces discrepancies in timing of signals by shortening lengths of signal transmission paths. The scale of the circuit is restrained by reducing the number of connecting lines between a modulation waveform generator and buffer circuits. A set signal and a reset signal generated by the modulation waveform generator are input to a first wave shaping SR register which produces a single pattern waveform to be applied to devices under test. The single pattern waveform is multiplied n-fold by the buffer circuit. Signals from the buffer circuit are received by invert/noninvert circuits which provide invert signals and noninvert signals. Differential circuits receive the invert/noninvert signals to generate set signals and reset signals having minimal discrepancies in timing which are input to second wave shaping SR registers.

Abstract: A frequency synthesizer is supplied with an input signal of frequency .function..sub.i to provide an output signal .function..sub.o where .function..sub.o=.function..sub.i M/N and M and N are integers. The input signal is first applied to a divider circuit for division by M/K where K is an integer and the resultant is applied as inputs to a phase locked loop. The phase locked loop includes a ring oscillator of frequency .function..sub.i N/M, a frequency multiplier circuit for multiplying by K, and a frequency divider circuit for dividing by N. The ring oscillator uses a combinational logic circuit that combines the outputs of four differential delay elements to produce a frequency multiplication of four.

Abstract: The invention relates to a circuit for frequency synthesis, comprising: a digital controlled oscillator, comprising (a) a clock generator; an accumulator circuit to which the signal from the clock generator is fed; and a control digit feed circuit for feeding to the digital oscillator a signal representing a control digit; and (b) a phase-locked loop which is connected to the carry output terminal of the accumulator circuit and which is provided with a phase detector, a low-pass filter and a controlled oscillator, wherein the carry output terminal is connected to the phase detector. The digital controlled oscillator is preferable adapted to generate a signal representing a remainder, wherein a correction circuit is arranged for deriving a correction signal from the remainder. The correction circuit is connected to a combination circuit connected to one of the inputs of the phase detector or to a combination circuit incorporated in the phase-locked loop. The circuits can also be connected in cascade.

Abstract: A phase-locked loop frequency synthesizer system is provided using fractional frequency division and a fractional control number for phase modulating an output of the frequency synthesizer using an incoming information signal. The apparatus includes a delta-sigma converter which adjusts a divisor of the frequency divider by operating upon a magnitude modulated fractional frequency control number. The system further includes a differentiator which provides the magnitude modulated input stream to the delta-sigma modulator by modulating the fractional control number with detected differences in the incoming information signal.

Abstract: A digital waveform oscillator generates digitized waveforms without distortion using a lookup table. The frequencies which may be generated using direct lookup tables at their fundamental table frequencies are increased according to this invention by including multiple cycles of the waveform within a single table. The selection of a table length L and a number of cycles N to be stored in a lookup table is done in a manner to optimize corresponding values of the frequencies to be generated and the sample rate.

Abstract: The present invention relates to methods and devices for generating cycled waveforms of nonsingle period, and more particularly to an improvement from the one-way counter used by conventional cycled waveform generator of nonsingle period into an up-down counter or a programmable up-down counter, along with an adder/subtracter. Thus, only the varied values in waveform relative to a DC level have to be filled into a table, and then the varied values in waveform (i.e. the digital waveform sampling values) are input into said adder/subtracter to obtain a periodic digital values by adding/subtracting with a predetermined DC level. Finally, cycled waveforms of nonsingle period are obtained by digital-to-analog converting of said digital values. With the methods and devices of the present invention, not only the fillings in said table can be decreased to reduce the cost, but also the DC output level can be fixed or adjusted arbitrarily for convenient signal processing.

Abstract: A semiconductor memory device capable of reducing a delay in the conversion of an input chip enable signal having a TTL level, providing a quick chip enable access and avoiding an increase in current consumption even when the quick chip enable access is made possible. The semiconductor memory device in one embodiment includes an input buffer outputting a signal having a CMOS level in response to a chip enable signal having a TTL level and having a plurality of transistors whose gate widths are set to first dimensions and a second input buffer activated in response to both an input signal having a TTL level other than the chip enable and the signal having the CMOS level and having a plurality of transistors whose gate widths are set to second dimensions smaller than the first dimensions.

Abstract: A frequency synthesizer comprises a voltage controlled oscillator (VCO) with an output frequency f.sub.out that is dependent on a VCO-control voltage input. A divide-by-k counter is connected to receive the output frequency f.sub.out and to output a pair of in-phase and quadrature phase signals f.sub.k. A vector modulator is connected to receive the in-phase and quadrature phase signals f.sub.k and the output frequency f.sub.out, and outputs a single sideband (SSB) modulated output f.sub.n comprising only one of the sum (f.sub.out +f.sub.k) or difference (f.sub.out -f.sub.k) products. A divide-by-n counter is connected to receive the modulated output f.sub.n and to output a feedback frequency sample f.sub.f. And a phase detector is connected to receive the feedback frequency sample f.sub.f and to compare it with a reference frequency f.sub.r. A phase error output signal is provided for the VCO-control voltage input.

Abstract: An input expansion for a crosspoint switch module incorporates a plurality of crosspoint switch ICs within the switch module so that the crosspoint switch module may receive a plurality of input differential signals. The crosspoint switch module includes a module driver circuit which, when enabled by a module enable signal, couples a differential current signal to an output. Each crosspoint switch includes an emitter follower configured transistor circuit for receiving one of the input differential signals and providing an output differential signal and a switch transistor circuit configured as a saturated switch for receiving the output differential signal and providing the differential current signal when enabled by a switch enable signal. Only one of the crosspoint switches is enabled at a time so that only one of the crosspoint switches carries current.

Abstract: A fractional frequency synthesizer (100) includes a symmetrical divider (165) having an output frequency signal (135) fractionalized based on half cycles of its input frequency signal (130). The divider (165) is provided with a divisor (145) that varies based on half cycles of the output signal. Preferably, the divider (165) operates to selectively add or subtract an increment, corresponding to one half cycle of the input frequency signal (130), to a half cycle of the output frequency signal (135).

Abstract: A frequency synthesizer has multiple modes of operation including a relatively short-duration frequency seek mode and a relatively long-duration normal mode. The synthesizer responds to a reference frequency signal and produces a periodic signal at a frequency that is a rational number times the frequency of the reference frequency signal. The synthesizer comprises a VCO, a feedforward state machine, a feedback state machine, a phase comparator, controllable gain circuitry between the phase comparator and the VCO, and logic circuitry that coordinates the operation of the feedforward and feedback state machines during the seek mode.

Abstract: A method and apparatus for frequency synthesis replaces a conventional divide-by-N counter with a low-power binary ripple counter (108). The method and apparatus employs a difference comparison scheme (114) that provides arbitrarily precise channel spacing, and allows loop sample rate to be selected independent of channel spacing.

Abstract: The invention relates to a clock signal frequency multiplier circuit. The circuit multiplies the speed of a clock signal of an integrated circuit (IC) by a factor N to generate a times-N clock signal. The circuit first receives a clock signal. Next, the circuit replicates the clock signal into a plurality of N component signals. Each Jth component signal is delayed from the (J-1)th component signal by 1/N cycles, where J equals 1 to N. The (J=1)th component signal is the clock signal. The N component signals are referred to as phase-shifted components. Finally, the circuit logically combines the phase-shifted components into a times-N clock signal.

Abstract: A variable frequency synthesis apparatus and method use a phase prediction signal to enable integer division in the feedback path of a phase-lock-loop to provide an output signal at a rational frequency multiple of an applied reference signal. A fixed integer divide ratio is maintained within each period of the reference signal. The output signal provided by a variable frequency oscillator is frequency divided and is phase compared to the reference signal. The phase comparison produces a predictable, time-varying phase difference signal based on a known frequency difference between the output signal and the reference signal. The phase prediction signal cancels the predictable phase difference signal and isolates an phase error signal used to steer, or adjust, the frequency of the oscillator to precisely equal the rational frequency multiple of the applied reference signal when the phase error signal is minimized.

Abstract: A system for synthesizing a waveform that employs combinatorial logic to generate digital data for each of a set of preselected waveform. The system includes circuitry for selecting a sequence of the preselected waveform pulses in response to a data signal and circuitry for converting the digital data for the sequence of the preselected waveform pulses into the waveform.

Abstract: A frequency multiplying device which multiplies the frequency of an externally-supplied reference signal PREF includes a digitally-controlled oscillation circuit, which includes a ring oscillator formed of thirty-two inverting circuits in a ring configuration which are adapted to generate sixteen clock signals having a period that is thirty-two times the inversion time of each inverting circuit and a phase interval that is twice the inverting circuit inversion time, and produces an output signal POUT having a period that corresponds to frequency control data CD at a resolution of the phase difference time of the clock signals, a counter/data-latch circuit which counts the clock signal RCK released by the ring oscillator within one period of the reference signal PREF and delivers the frequency control data CD of the count value to the digital oscillation circuit, and a control circuit which controls the operation of the circuits so that the oscillation output signal POUT having the frequency of the reference s