Abstract: An output circuit receives a data signal biased within a first voltage range associated with a first power supply voltage and generates an output signal on an output node biased within a second voltage range in response to the data signal, the second voltage range is associated with a second power supply voltage greater than the first power supply voltage. The output circuit generates pull-up and pull-down signals that are within the first voltage range in response to the data signal. The output circuit includes an output driver circuit including a pull-up circuit and a pull-down circuit. The pull-up circuit, when activated, generates the output signal indicative of the second power supply voltage in response to a modified pull-up signal being the pull-up signal level-shifted to a third voltage range. The pull-down circuit, when activated, generates the output signal being the ground potential in response to the pull-down signal.

Abstract: The present invention provides a circuit including an output buffer, a tracking circuit and a pre-driver, where the output buffer includes at least one P-type transistor and at least one N-type transistor, the at least one P-type transistor is coupled between a supply voltage and a pad, and the at least one N-type transistor is coupled between a ground voltage and the pad. In the operations of the circuit, the tracking circuit is configured to generate a tracking signal control signal according to a voltage level at the pad, and the pre-driver is configured to generate a control signal to control the at least one P-type transistor or the at least one N-type transistor according to the tracking signal.

Abstract: The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output. This decreases the amplitude voltage of a circuit (a shift register circuit, a decoder circuit, or the like) which outputs the signal input to the level shifter. Consequently, power consumption of the circuit can be reduced. Alternatively, a voltage applied to a transistor included in the circuit can be reduced. This can suppress degradation of the transistor or damage to the transistor.

Abstract: A gate driver with reduced voltage fluctuations driving a display device generates pulse signals shifted in a specified phase. The gate driver includes connected unit circuits. Each unit circuit includes an output terminal, input and output transistors, and a holding module. First and second control signals, alternating oppositely between high and low states, govern the two transistors. The input transistor is controlled by a first control signal and outputs a high level voltage to a first node based on a trigger signal. The output transistor outputs the shifted pulse signal synchronously with a clock control signal, based on the high level voltage of the first node. Initially, the trigger signal is low and the first and second control signals are high. The holding module outputs the low level voltage to the output terminal based on the first control signal and the second control signal.

Abstract: A semiconductor device includes transistor cells and enhancement cells. Each transistor cell includes a body zone that forms a first pn junction with a drift structure. The transistor cells may form, in the body zones, inversion channels when a first control signal exceeds a first threshold. The inversion channels form part of a connection between the drift structure and a first load electrode. A delay unit generates a second control signal which trailing edge is delayed with respect to a trailing edge of the first control signal. The enhancement cells form inversion layers in the drift structure when the second control signal falls below a second threshold lower than the first threshold. The inversion layers are effective as minority charge carrier emitters.

Abstract: A semiconductor device includes a first integrated chip; a second integrated chip; a plurality of reference through-chip vias formed through the first and second integrated circuit chips; and at least a normal through-chip via formed through the first and second integrated circuit chips, wherein the first integrated circuit chip comprises: a plurality of reference sourcing circuits suitable for sourcing a reference current to the respective reference through-chip vias; and at least a sourcing circuit suitable for sourcing the reference current to the normal through-chip via, and wherein the second integrated circuit chip comprises: a plurality of reference sinking circuits suitable for sinking currents flowing through the respective reference through-chip vias; a line suitable for electrically coupling the plurality of reference through-chip vias; a comparison voltage generation circuit suitable for generating a plurality of comparison voltages based on a voltage of the line; at least a sinking circuit suitab

Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for powering up a charge pump converter and providing protection and soft-start circuitry therefor. One example charge pump converter generally includes a first transistor and a second transistor coupled in series between an input voltage node and an output voltage node of the charge pump converter, a first capacitive element having a first terminal coupled to a node between the first and second transistors, and a first switch coupled to the input voltage node, the first switch being configured to selectively enable a first drive circuit having an output coupled to a control terminal of the second transistor.

Abstract: A hybrid output driver is disclosed that supports high-voltage signaling and low-voltage signaling. The high-voltage signaling is powered by a high-power supply voltage that is greater than a low-power supply voltage that powers the low-voltage signaling.

Abstract: Example embodiments of the present disclosure relate to a line driver apparatus. In some example embodiments, an apparatus is provided. The apparatus includes a capacitive feed-through module and a driving module. The capacitive feed-through module includes a first pre-driver operable to receive input differential signals and delayed signals of the input differential signals, generate first drive signals from the input differential signals and the delayed signals, and equalize the first drive signals. The capacitive feed-through module also includes a capacitance reducing module arranged between the first pre-driver and transmission lines and operable to reduce parasitic capacitance at the transmission lines in response to the first drive signals. The driving module is coupled to the transmission lines and operable to generate output differential signals from the input differential signals for transmission on the transmission lines.

Abstract: A transmitter of the present disclosure includes: an output terminal; a driver that performs transition of a voltage of the output terminal among a plurality of voltages; and a controller that controls the driver to cause transition start timing in one voltage transition in voltage transition among the plurality of voltages to be later than transition start timing in another voltage transition.

Abstract: A circuit or associated system or method comprises a first driver including a first transistor bank and a first resistor connected in series between a first predetermined voltage and an output pad, the first transistor bank including a first driver transistor and a plurality of first calibration transistors, wherein the plurality of first calibration transistors are respectively controlled based on a combination of bits of a first calibration code and on an output of at least one first logic gate.

Abstract: A hybrid output driver is disclosed that supports high-voltage signaling and low-voltage signaling. The high-voltage signaling is powered by a high-power supply voltage that is greater than a low-power supply voltage that powers the low-voltage signaling.

Abstract: An input signal is split onto a first data path and a second data path. Values of the input signal above a threshold voltage level are propagated on the second data path and not on the first data path. The propagation of the signal from the input signal terminal through the first data path or the second data path is selectively controlled using two reference bias voltages generated based on a level of the signal.

Abstract: A bridge output circuit includes: a voltage-controlled first transistor provided between a first power supply terminal and an output terminal; a voltage-controlled second transistor provided between the output terminal and a second power supply terminal having a potential lower than the potential of the first power supply terminal; a first OFF detection circuit detecting whether the first transistor is in an OFF state based on a gate voltage of the first transistor; a second OFF detection circuit detecting whether the second transistor is in an OFF state based on a gate voltage of the second transistor; and an output control circuit performing a first source transition operation of turning off the second transistor and then turning on the first transistor, and then performing a second source transition operation of turning off the first transistor and then turning on the second transistor.

Abstract: Implementations described herein relate to circuits and techniques increasing transmitter output speed. In some implementations, a circuit is described using a pull-up data path comprising a first flying capacitor, a first buffer, a thin-oxide PMOS device, and a thick-oxide PMOS device, a pull-down data path comprising a second flying capacitor, a second buffer, a thin-oxide NMOS device, and a thick-oxide NMOS device, wherein the pull-up data path and the pull-down data path are operatively connected to a core data output signal line.

Abstract: A sensing circuit and a touch sensor including the same are disclosed. The sensing circuit includes a current provider configured to provide a first current between a first power source and a first node and a second current between the first node and a second power source, a bias unit configured to output first and second outputs to first and second output nodes, and a current-to-voltage converter configured to mirror the first and second currents and to output a sensing voltage. The bias unit includes a differential amplifier, first and second output transistors, and a current mirror. A first input terminal of the differential amplifier receives a reference voltage and a second input terminal of the differential amplifier is connected to a second node corresponding to a connection node of the first and second output transistors.

Abstract: A circuit includes a first power transistor including a first control input and first and second current terminals. The circuit includes a second power transistor including a second control input and third and fourth current terminals. Third current terminal couples to the first current terminal, and the fourth current terminal couples to the second current terminal at an output node. An error amplifier generates an error signal based on a difference between a reference voltage and an output voltage on the output node. An adaptive buffer couples to an output of the error amplifier and couples to the first and second control inputs. The adaptive buffer causes the first power transistor to be on through a range of output current and to cause the second power transistor to be on through some, but not all, of the range of output current.

Abstract: An apparatus is provided which comprises: a first inverter to receive a clock; a pass-gate coupled to the first inverter; a second inverter coupled to the pass-gate and to provide an output clock; and a device coupled to the second inverter and the pass-gate, wherein the transistor and the pass-gate are controllable by a logic that depends on logic values of at least two signals (e.g., an enable and the clock).

Abstract: Apparatuses and methods for power regulation based on input power using circuitry are disclosed herein. An example apparatus may include a reference circuit configured to receive a first voltage and a second voltage and to provide an output reference voltage at an output node having a value equal to the second voltage subtracted from the first voltage. The reference circuit may be configured to mirror a current of a first circuit coupled between the second voltage and a reference voltage through a second circuit coupled between the first voltage and the output node. The example apparatus may further include a power circuit configured to provide a third voltage based on the output reference voltage. The third voltage may have a value that is equal to the output reference voltage.

Abstract: The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output. This decreases the amplitude voltage of a circuit (a shift register circuit, a decoder circuit, or the like) which outputs the signal input to the level shifter. Consequently, power consumption of the circuit can be reduced. Alternatively, a voltage applied to a transistor included in the circuit can be reduced. This can suppress degradation of the transistor or damage to the transistor.

Abstract: Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.

Abstract: A voltage boost circuit for eDram using thin oxide field effect transistors (FETs) is disclosed. The voltage boost circuit includes a boost capacitor which is precharged with a precharge voltage in a precharge stage and which provides a boosted supply voltage to a thin oxide FET during a pump phase. The voltage boost circuit further include a drive capacitor which provides a turn on voltage to the thin oxide FET so that the boosted supply voltage can pass to an output node in the pump phase.

Abstract: A display device may include a plurality of rows of pixels configured to display image data on a display and a first gate driver circuit. The first gate driver circuit may couple a first voltage source to a first node associated with a first gate of a first switch upon receipt of a start signal or a gate signal from another gate driver circuit and couple a first clock signal to a first gate line via the first switch after a first voltage of the first node exceeds a threshold. The threshold is associated with activating the first switch, such that the first gate line is configured to couple to a first row of the plurality of rows of pixels. The first gate driver circuit may then couple a second voltage source to the first node based on a second clock signal, such that the second voltage source discharges the first node.

Abstract: An apparatus comprising is disclosed. The apparatus a driver circuit configured to selectively provide a first supply voltage to an output node in a first operating mode and to selectively provide a second supply voltage to the output node in a second operating mode, based on one or more enable signals.

Abstract: A Schmitt trigger circuit includes a first circuit; a second circuit; a first switch; a third circuit; and a second switch. The first circuit output the output signal of a second or first logical level. The second circuit is coupled to a first potential node at a first end, and sends a current between the first end and a second end based on the output signal. The first switch electrically couples or uncouples the second end and a first node based on a selection signal. The third circuit is coupled to a second potential node at a third end, and sends a current exclusively with the second circuit between the third end and a fourth end based on the output signal. The second switch electrically couples or uncouples the fourth end and the first node based on the selection signal.

Abstract: A unit circuit 11 of a shift register is provided with a transistor Tr8 having a drain terminal connected to a node N2, a source terminal to which an off potential is applied, and a gate terminal connected to an output terminal OUT, in order to stabilize a potential of the node N2. The unit circuit 11 is further provided with a transistor Tr9 having a drain terminal connected to the output terminal OUT, a source terminal to which the off potential is applied, and a gate terminal to which an initialization signal INIT is supplied. With this, when performing an initialization, it is possible to control the potential of the node N2 to be a desired level and initialize the shift register certainly, irrespective of a state of the transistor Tr8 before the initialization.

Abstract: Described embodiments provide circuits, systems and methods for generating a sensing signal in response to the ambient condition, comparing the sensing signal to a threshold hysteresis range to generate a digital signal, and upon powering on the sensor, determining whether the sensing signal is within the threshold hysteresis range and, if the sensing signal is within the threshold hysteresis range, setting the digital signal to a predetermined level based on a hysteresis restoration state associated with sensor before the sensor is powered off.

Abstract: A receiver circuit may be provided. The receiver circuit may include a delay circuit and a synchronization circuit. The delay circuit may variably delay a data strobe signal based on a delay select signal. The synchronization circuit may generate internal data from data in synchronization with the variably delayed data strobe signal.

Abstract: There is provided a CMOS inverter circuit device. The CMOS inverter circuit device includes a delay circuit unit configured to generate different charge and discharge paths of each gate node of a PMOS transistor and an NMOS transistor respectively at the time that an input signal transitions between high and low levels. Therefore, the present examples minimize or erase generation of a short circuit current made at the time that the input signal transition. The examples may simplify circuit architecture, and may make a magnitude of a CMOS inverter circuit device smaller.

Abstract: A semiconductor device includes: a bootstrap capacitor charged via a diode when a low-side switching device is ON, a resulting charge voltage being applied to a high-side driver circuit when the low-side switching device is OFF; a supplementary bootstrap capacitor charged when the low-side switching device is OFF; a Zener diode that regulates a charge voltage of the supplementary bootstrap capacitor; and a control circuit that applies the charge voltage of the supplementary bootstrap capacitor to the high-side driver circuit via a switch circuit when the charge voltage of the bootstrap capacitor decreases to less than a prescribed voltage while a high-side switching device is ON.

Abstract: The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output. This decreases the amplitude voltage of a circuit (a shift register circuit, a decoder circuit, or the like) which outputs the signal input to the level shifter. Consequently, power consumption of the circuit can be reduced. Alternatively, a voltage applied to a transistor included in the circuit can be reduced. This can suppress degradation of the transistor or damage to the transistor.

Abstract: A transistor monolithically integrated in a semiconductor body includes a first sub-transistor and a second sub-transistor that both include a first and second load contacts and a control contact for controlling an electric current through a load path. The first load contact of the first sub-transistor is electrically connected to the first load contact of the second sub-transistor and the second load contact of the first sub-transistor is electrically connected to the second load contact of the second sub-transistor. A control circuit is configured to cause the first sub-transistor to switch from a first state to a second state at a first point of time and to cause the second sub-transistor to switch from the first state to the second state at a second point of time subsequent to the first point of time.

Abstract: A device (100) for activating an electrical consumer (105) includes a controllable current source (140) for providing a control current, a switching unit (115) for controlling a consumer current as a function of the control current, and a sampling unit (145) for determining a time delay between an activation of the current source (140) and the enabling or interruption of the current flow by the switching unit (115). Furthermore, a processing unit (135) is provided, which is configured to determine that the current source (140) is defective if the time delay lies outside a predetermined range.

Abstract: An inverter phase leg has upper and lower gate drive circuits supplying gate drive signals to upper and lower transistors. Each gate drive circuit includes an active clamp for selectively deactivating the upper and lower transistors. The transistors are comprised of semiconductor devices, each having respective gate, source, and emitter terminals. Each emitter terminal is connected to a respective output electrode structured to enhance a common source inductance between the respective gate and emitter terminals. Each emitter terminal is further connected to a respective Kelvin emitter electrode substantially bypassing the respective output electrode. Each respective active clamp is connected between the respective gate terminal and Kelvin emitter electrode so that the active clamping function remains effective in the presence of the enhanced common source inductance.

Abstract: A CMOS output circuit includes a first P-MOSFET having a source connected to a power supply terminal, a drain connected to an output terminal, and a back gate connected to a first potential terminal; a first N-MOSEFET having a drain connected to the output terminal, a source connected to the ground terminal, and a back gate connected to a second potential terminal; a first potential switching portion arranged to switch whether to connect the first potential terminal to the power supply terminal or to the output terminal; a second potential switching portion arranged to switch whether to connect the second potential terminal to the ground terminal or to the output terminal; a first gate switching portion arranged to switch whether or not to short-circuit the gate of the first P-MOSFET to the first potential terminal; a second gate switching portion arranged to switch whether or not to short-circuit the gate of the first N-MOSFET to the second potential terminal; a first driver arranged to drive the gate of the

Abstract: A power circuit includes a power transistor flowing a power current to a ground according to the voltage of a driving node, a driving circuit, and a pre-driver. The driving circuit includes a high-side transistor providing a supply voltage to the driving node according to a high-side voltage of a high-side node, a low-side transistor coupling the driving node to the ground according to a first internal signal, and a charge pump coupled to the high-side node and the driving node and generating the high-side voltage that exceeds the supply voltage according to the first internal signal. The pre-driver generates the first internal signal according to a control signal. The pre-driver is configured to improve driving capability of the control signal.

Abstract: Apparatuses and methods for power regulation based on input power using circuitry are disclosed herein. An example apparatus may include a reference circuit configured to receive a first voltage and a second voltage and to provide an output reference voltage at an output node having a value equal to the second voltage subtracted from the first voltage. The reference circuit may be configured to mirror a current of a first circuit coupled between the second voltage and a reference voltage through a second circuit coupled between the first voltage and the output node. The example apparatus may further include a power circuit configured to provide a third voltage based on the output reference voltage. The third voltage may have a value that is equal to the output reference voltage.

Abstract: To provide an electronic circuit and the like capable of extending the life greatly even when the transistors constituting the electronic circuit have property fluctuation. The electronic circuit includes switching-target circuits and a switching circuit for switching the switching-target circuits to an operating state from a stop state. The switching-target circuits include the switching-target circuit in an operating state and the switching-target circuit in an initial-to-stop state. Property fluctuation is generated in the transistors forming the switching-target circuits and the switching target due to an electric stress applied to the transistors. The switching circuit switches the switching-target circuit in the initial-to-stop state to an operating state by the transistor of the switching circuit.

Abstract: A transmit driver or transmitter is provided to generate an output data signal based on different input modes, such as low speed (LS), full speed (FS), high speed (HS), and high speed interconnect (HSIC) modes of a Universal Serial Bus (USB) standard. The transmit driver includes a rail voltage generator for generating a rail voltage for a set of transmit driver slices based on the selected mode. The transmit driver includes a bias voltage generator for generating a bias voltage based on the selected mode for protecting transistors in the transmit driver slices from over-voltage stress. The transmit driver includes a predriver and level shifter for generating input signals for the transmit driver slices to set the output impedance of the transmit driver and the slew rate of the output data signal. The transmit driver includes an emphasis equalizer for providing controllable emphasis equalization to the output data signal.

Abstract: An output circuit includes a first transistor, a second transistor, an operational amplifier that outputs a control voltage, and a switch circuit that controls voltage output in accordance with a control signal. When the control signal is in a first state, the switch circuit supplies the control voltage to the gate of the first transistor to turn on the first transistor and electrically connects the drain of first transistor to the operational amplifier so that a first output voltage is output from the drain of the first transistor. When the control signal is in a second state, the switch circuit supplies the control voltage to the gate of the second transistor to turn on the second transistor and electrically connects the drain of the second transistor to the operational amplifier so that a second output voltage is output from the drain of the second transistor.

Abstract: A drive circuit includes a control circuit configured to output a polarity signal for controlling ON/OFF of a driving switch, a pulse transformer, electrically connected to the control circuit, configured to transmit the polarity signal, and a discharge circuit, electrically connected to the pulse transformer and a gate terminal of the driving switch, configured to discharge an electric charge accumulated in the gate terminal based on the polarity signal. When the polarity signal having a first polarity is applied to the gate terminal through the pulse transformer, the driving switch is switched to and maintained in an ON state by accumulating the electric charge in the gate terminal. When the polarity signal having a second polarity different from the first polarity is applied to the discharge circuit through the pulse transformer, the driving switch is switched to an OFF state by discharging the electric charge by the discharge circuit.

Abstract: An electrical waveform generating circuit has a pair of Pulse Amplitude Controlled Switching Current Sources (PACS). A gate pulse driver circuit is coupled to an input of each of the pair of PACS for sending gate pulses for driving the pair of PACS. A digital-to-analog converter (DAC) circuit is coupled to the gate pulse driver circuit for controlling amplitudes of the gate pulses. A transducer is coupled to the PACS.

Abstract: A system includes a signal generator and a signal combiner. The signal generator is configured to output a first signal having a first frequency and to output one or more signals having the first frequency and having phases shifted relative to the first signal by predetermined amounts. The signal combiner is configured to combine the first signal and the one or more signals to output a frequency multiplied second signal having a second frequency. The second frequency is greater than the first frequency.

Abstract: A gate drive circuit includes first and second transistors for turning on and off semiconductor switching devices. The circuit includes a DC power supply for driving the first and second transistors. The gate drive circuit further includes a third transistor, a fourth transistor, and a DC power supply being a power supply for the third and fourth transistors with a voltage value lower than the voltage value of the DC power supply, thereby making lower the impedance of the path of a current flowing from the DC power supply to the gates of the switching devices through the third transistor than the impedance of the path of a current flowing from the DC power supply to the gates of the switching devices through the first transistor.

Abstract: The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output. This decreases the amplitude voltage of a circuit (a shift register circuit, a decoder circuit, or the like) which outputs the signal input to the level shifter. Consequently, power consumption of the circuit can be reduced. Alternatively, a voltage applied to a transistor included in the circuit can be reduced. This can suppress degradation of the transistor or damage to the transistor.

Abstract: A voltage level shifting circuit with an input terminal and an output terminal. The level shifting circuit has a field-effect transistor (FET) switch with a gate attached to the input terminal, a drain attached to the output terminal and a source attached to a current changing mechanism. The current changing mechanism includes a current mirror circuit having an output connected between the source and an electrical earth. The output of the current mirror circuit is preferably adapted to change a current flowing between the drain and the source based on an input voltage applied to the gate.

Abstract: A bus driver is provided that can withstand over voltages being applied to its output terminal without the protection circuit detracting from the voltage swing that can be provided by the driver. The circuit arrangement also allows transistors having good on state resistance and large tolerance of drain-to-source voltages to be used.

Abstract: A power converter with a dynamic preload. The power converter includes a magnetic component coupled between an input and an output of the power converter. The output of the power converter has an output voltage for providing power to a load. A switch is adapted to control current through the magnetic component according to on and off times of the switch. A dynamic preload circuit is coupled to the output of the power converter. The dynamic preload has loading characteristics that are adjusted responsive to a signal indicative of an output voltage at the output of the power converter.

Abstract: Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.

Abstract: An integrated circuit (“IC”) includes an input receiver with multiple hysteresis levels. An exemplary input receiver may be an input buffer with a Schmitt trigger that has multiple hysteresis windows between different high and low input voltages. This circuit may improve the input noise immunity of the external input signals and timing by allowing for a selection one of the plurality of levels depending on parameters of the input (e.g. noise level).