Abstract: A PMOS output stage and an NMOS output stage of which output impedances are controlled in accordance with impedance codes, a gate control part which drives output transistors held by the PMOS output stage and the NMOS output stage, and a slew rate control part which generates bias voltages to control driving ability of the gate control part based on an input current are included, and manufacturing variability of an input current circuit generating an input current is corrected by using the impedance code by the slew rate control part.

Abstract: An electronic circuit includes a first transistor device with a control terminal and a load path. A drive circuit includes an input terminal and an output terminal. The output terminal is coupled to the control terminal of the first transistor device. The drive circuit is operable to drive the first transistor device dependent on an input signal received at the input terminal. A polarity detector is coupled in parallel with the load path of the first transistor device. The polarity detector includes a second transistor device and a current detector. The second transistor device includes a load path connected to the load path of the first transistor device. The current detector includes a sense path in series with the load path of the second transistor device and an output connected to the input terminal of the drive circuit.

Abstract: A multi-chip system may include a plurality of chips, and a channel shared by the plurality of chips. At least one of the plurality of chips includes a transmission circuit configured to transmit a signal to the channel. Drivability of the transmission circuit is adjusted based on a number of the plurality of chips.

Abstract: An overdrive circuit includes a pull-up circuit and a pull-down circuit. The pull-down circuit includes first, second and third transistors electrically connected in cascode between an output node and a low voltage supply node. A capacitor is electrically connected from a gate electrode of the third transistor to a gate electrode of the first transistor. A first mono-directional bias device is electrically connected from a drain electrode of the first transistor to a gate electrode of the first transistor. A second mono-directional bias device is electrically connected from the gate electrode of the first transistor to a source electrode of the first transistor.

Abstract: A method and circuit for implementing protection for complementary metal oxide semiconductor (CMOS) output drivers, and a design structure on which the subject circuit resides are provided. An output driver stage transistor stack includes a plurality of series connected PFETs series connected with a plurality of series connected NFETs connected between upper and lower voltage supply rails. A pair of offset DC voltage levels provides respective gate voltages of an intermediate PFET and an intermediate NFET in the output driver stage transistor stack. A pair of pre-driver circuits receiving voltage level translated logic signals drive respective gate inputs of the upper PFET and the lower NFET in the output driver stage transistor stack. A voltage feedback circuit provides respective gate voltages of the PFET and NFET connected together in the output driver stage transistor stack.

Abstract: An integrated circuit includes an output buffer and a control circuit. The output buffer has a signal input, a signal output, and a set of control inputs. The output buffer has an output buffer delay, and a driving strength adjustable in response to control signals applied to the set of control inputs. The control circuit is connected to the set of control inputs of the output buffer. The control circuit uses first and second timing signals to generate the control signals, and includes a reference delay circuit that generates the first timing signal with a reference delay, and a delay emulation circuit that generates the second timing signal with an emulation delay that correlates with the output buffer delay.

Abstract: A differential output circuit has a current source, a voltage source, first paired transistors which, in a first operating mode, switch that current from the current source should be flown to which of paired output terminals, depending on logic levels of differential input signals, and is always turned off in a second operating mode, second paired transistors which, in the second operating mode, switch which of the paired output terminals should be applied with a voltage correlated with a voltage of the voltage source, depending on the logic levels of the differential input signals, and configured to be always turned off in the first operating mode, third paired transistors which, in the second operating mode, pass the current inputted into one of the paired output terminals toward a predetermined reference potential, and is always turned on in the first operating mode, and paired impedances.

Abstract: In accordance with an embodiment, a method of operating a gate driving circuit includes monitoring a signal integrity at an output of the gate driving circuit. If the signal integrity is poor based on the monitoring, output of the gate driving circuit is placed in a high impedance state and an external signal integrity failure signal is asserted.

Abstract: A switching control circuit controls a switching circuit based on decoded signals obtained by decoding several input signals. The switching control circuit is includes a decoder circuit that outputs decoded signals obtained by decoding coded input data signals. The switching control circuit includes a driver circuit that generates control signals for controlling the switching circuit based on the decoded signals. The switching control circuit is provided with a synchronous control circuit that synchronizes the input signals before outputting them for decoding.

Abstract: The present disclosure discloses methods and circuits to reduce power consumption of switching circuits comprising two or more units by applying charge sharing/reuse of capacitive loads between the units. The units are stacked in a way that, if an output potential of a unit is to be lowered and an output potential of a neighboring unit is to be lifted, a charge of the unit to be lowered is reused by transferring it to the unit to be lifted depending on input signals of the units. In case of input signals having an arbitrary relationship a storage unit is placed at a junction of two neighboring units to store the charge temporarily until a neighboring unit is to be lifted.

Abstract: An embodiment of an apparatus is disclosed. For this embodiment, an output driver and a bias voltage controller are included. The bias voltage controller is coupled to provide first and second bias voltages to the output driver. The bias voltage controller comprises a bias generator coupled to a first voltage supply, a second voltage supply, and a ground node. The bias generator has a first bias node for sourcing the first bias voltage. The first voltage supply is configured to provide a higher voltage level than the second voltage supply. A resistor-divider network is coupled to the first voltage supply and the ground node. A watch dog circuit is coupled to the resistor-divider network, bias generator, and the ground node. A comparison circuit is coupled to the bias generator and the second voltage supply. The comparison circuit has a second bias node for sourcing the second bias voltage.

Abstract: A gate drive circuit of the present invention is a gate drive circuit for driving an insulated gate switching element, which comprises a control drive circuit for applying a driving voltage to a control terminal of the switching element at a predetermined timing, and a voltage monitoring circuit for monitoring both a first voltage which is a power supply voltage of the control drive circuit and a second voltage which negatively biases the control terminal of the switching element, and in the gate drive circuit, the control drive circuit cuts off an output when at least one of the first and second voltages monitored by the voltage monitoring circuit becomes lower than a threshold value. It is an object of the present invention to provide an insulated gate switching element which can suppress wrong ON.

Abstract: A switching-element drive circuit that is configured to be applied to a power converter includes: a switching element; and a control unit that controls an operation of the switching element. The control unit includes a drive-voltage control unit that is configured to be capable of changing a switching speed of the switching element based on a power supply current.

Abstract: One aspect is a circuit having an input configured to receive an input signal, and an actuation output configured to be connected to an actuation terminal of a transistor. A measurement arrangement is configured to ascertain at least one of a load current through a load path of the transistor, and a load voltage across the load path of the transistor and to provide a measurement signal that is dependent on at least one of the load current and the load path voltage. An actuation current source is configured to receive the measurement signal and to provide an actuation current at the actuation output, the actuation current having a current level dependent on the measurement signal.

Abstract: A Local Interconnect Network (LIN) driver circuit employs a charging/discharging current applied to the gate of a driver transistor coupled to an LIN bus. The charging current includes a constant charging current and an additional soft charging current, whereas the discharging current includes a constant discharging current and an additional soft discharging current. As a result of the soft charge/discharge components, there is a significant reduction in electromagnetic emission on the LIN bus.

Abstract: A switching circuit for switching electric potentials, such as a capacitive high voltage load in an X-ray generator is structured into plural stages having an electronic switch, wherein the electronic switches of the different stages are arranged in series, in order to form a series conduction line for switching the electric potentials. The plural stages draw energy from the series conduction line during the time period when the series conduction line is blocked and charge an energy storage. This stored energy can be utilized for closing the series conduction line and maintaining this closed state. Further, disclosed is a method for discharging an electric load by means of a switching circuit. Also disclosed are a high voltage generator, an X-ray generator and a medical imaging system, each having such a switching circuit.

Abstract: An embodiment of a pre-emphasis circuit, an embodiment of a method for pre-emphasizing complementary single-ended signals, an embodiment of a transmitter, and an embodiment of a communication system.

Abstract: Disclosed herein are an output driving circuit and a transistor output circuit. The output driving circuit includes: a reference voltage generating unit generating a reference voltage; a level shift unit including a transistor latch and turning off a first transistor of a driving circuit or driving the first transistor; a driving circuit unit including the first transistor that is driven to apply power to a gate of an output transistor and a second transistor that is driven complementarily to the first transistor to lower a gate voltage of the output transistor and drive the output transistor; and an withstand voltage protecting unit that is driven by receiving a reference voltage and includes a first withstand voltage protecting unit for protecting transistors of the transistor latch and the first transistor for stable operations thereof and a second withstand voltage protecting unit for protecting the output transistor for a stable operation thereof.

Abstract: A floating gate driver uses a single-end level shifter to translate a set signal and a reset signal induced by a rising edge and a falling edge of a switch signal to a common output terminal to generate an output voltage for a bistable circuit to generate a level shifted switch signal. Under control of a well transient detect signal asserted by detecting noise in the output voltage, a masking circuit between the single-end level shifter and the bistable circuit masks noise in the output voltage. This configuration has lower area penalty and better noise immunity.

Abstract: Apparatus for a wireless tachometer receiver. The wireless tachometer receiver includes a receiver and a signal conditioner that drives a conventional tachometer. Conventional tachometers require an input consisting of pulses at the operating voltage of the vehicle, which is typically 12 Vdc. Conventional receivers have an alternating current output that is substantially less than the operating voltage of the vehicle, which is insufficient to trigger the tachometer reliably. The signal conditioner converts the receiver output to a signal that allows for reliable operation of the conventional tachometer. In one embodiment, the signal conditioner is an amplifier that has a gain to drive the amplifier output between zero and the operating voltage of the vehicle. In another embodiment, the signal conditioner is a step-up transformer that has a ratio sufficient to produce an output at the operating voltage of the vehicle.

Abstract: A high voltage electrical switch including: a plurality of series connected semiconductor switches; a plurality of rectifiers wherein each rectifier is connected to a semiconductor switch control input of one of the semiconductor switches; a radio frequency signal generator; and a plurality of galvanic isolators, wherein each galvanic isolator connects the radio frequency signal generator to one of the plurality of rectifiers, wherein the plurality of semiconductor switches are isolated from one another.

Abstract: A gate driving circuit includes a pull-up control part, a pull-up part, a carry part, a first pull-down part and a second pull-down part. The pull-up control part applies a carry signal from a previous stage to a first node. The pull-up part outputs an N-th gate output signal based on a clock signal. The carry part outputs an N-th carry signal based on the clock signal in response to the signal applied to the first node. The first pull-down part includes a plurality of transistors connected to each other in series. The first pull-down part pulls down a signal at the first node to a second off voltage in response to a carry signal of a next stage. The second pull-down part pulls down the N-th gate output signal to a first off voltage in response to the carry signal of the next stage.

Abstract: A switch controller is provided that uses one or more capacitors to generate a slow turn on/slow turn off switch control signals to suppress audible switching noise in an audio switch. In some embodiments, an analog inverter and a capacitor are used to generate the switch control signals, while in other embodiments two capacitors are used to generate the switch control signals. To conserve power between switching states, routing logic is provided that ties the switch control signals to respective voltage rails and disables selected portions of the switch controller.

Abstract: Described herein is a wireless transceiver and related method that enables ultra low power transmission and reception of wireless communications. In an example embodiment of the wireless transceiver, the wireless transceiver receives a first-reference signal having a first-reference frequency. The wireless transceiver then uses the first-reference signal to injection lock a local oscillator, which provides a set of oscillation signals each having an oscillation frequency that is equal to the first-reference frequency, and each having equally spaced phases. Then the wireless transceiver combines the set of oscillation signals into an output signal having an output frequency that is one of (i) a multiple of the first-reference frequency (in accordance with a transmitter implementation) or (ii) a difference of (a) a second-reference frequency of a second-reference signal and (b) a multiple of the first-reference frequency (in accordance with a receiver implementation).

Abstract: An output buffer is disclosed. The output buffer includes an input-stage circuit, an output-stage circuit and a compensation circuit. The compensation circuit includes a capacitor, a first switch, a second switch, a third switch, and a fourth switch. The input-stage circuit receives a differential input signal and outputting a response signal. The output-stage circuit receives the response signal and outputting an output signal. The first switch controls a connection between the input-stage circuit and a first terminal of the capacitor. The second switch controls the connection between an output terminal of the compensation circuit and a second terminal of the capacitor. The third switch controls the connection between the input-stage circuit and the second-terminal of the capacitor. The forth switch controls the connection between the output terminal of the compensation circuit and the first terminal of the capacitor.

Abstract: An on-die termination circuit includes a reference period signal generation circuit that generates a reference period signal according to a level of a reference voltage, a first period signal generation circuit that generates a first period signal according to a voltage level of a pad, a period comparison circuit that compares a period of the first period signal with a period of the reference period signal and count a plurality of driving signals, and a driver circuit that drives the pad in response to the plurality of driving signals.

Abstract: A power device includes a switching device having a control terminal and an output terminal; and a driving circuit configured to provide a driving voltage to the control terminal such that a voltage between the control terminal and the output terminal remains less than or equal to a critical voltage. A rise time required for the driving voltage to reach a target level is determined according to current-voltage characteristics of the switching device. And, when the voltage between the control terminal and the output terminal exceeds the critical voltage, leakage current is generated between the control terminal and the output terminal.

Abstract: An output driver circuit includes a driving control signal generation block configured to compare a power supply voltage and a reference voltage and generate first and second driving control signals and first and second inverted driving control signals; a preliminary driving block configured to drive a pull-up driving signal and a pull-down driving signal with driving strengths set according to the first and second driving control signals and the first and second inverted driving control signals; and a driving block configured to drive output data in response to the pull-up driving signal and the pull-down driving signal.

Abstract: A low voltage isolation switch is suitable for receiving from a connection node a high voltage signal and transmitting said high voltage signal to a load via a connection terminal. The isolation switch includes a driving block connected between first and second voltage reference terminals and including a first driving transistor coupled between the first voltage reference (Vss) and a first driving circuit node and a second driving transistor coupled between the driving circuit node and the second supply voltage reference. The switch comprises an isolation block connected to the connection terminal (pzt), the connection node, and the driving central circuit node and including a voltage limiter block, a diode block and a control transistor. The control transistor is connected across the diode block between the connection node and the connection terminal and has a control terminal connected to the driving central circuit node.

Abstract: An integrated circuit chip includes: an internal circuit; a data output circuit configured to output a data packet of the internal circuit in response to a strobe signal; an oscillator configured to generate a first clock signal; a divider configured to divide the first clock signal and generate a second clock signal; and a strobe signal supply unit configured to supply the second clock signal as the strobe signal during an initial period of transmission of the data packet and supply the first clock signal as the strobe signal after the initial period.

Abstract: A semiconductor device includes a driver circuit having an output resistance that is controllable responsive to a resistance control signal and a calibration circuit configured to duplicate a resistance behavior of the driver circuit and to generate the resistance control signal responsive to the duplicated resistance behavior. The driver circuit may include a first variable resistor and may be configured to couple an output node to a power supply node via the first variable resistor responsive to an input signal The calibration circuit may include a second variable resistor that is a duplicate of the first variable resistor. The calibration circuit may further include a current source circuit and may be configured to couple the second variable resistor between the power supply node and the current source circuit and to generate the resistance control signal responsive to a voltage of the second variable resistor.

Abstract: There are provided a gate driver circuit and an operating method thereof. The gate driver circuit includes an output signal generating unit including a plurality of switch devices generating output signals, a selecting circuit unit generating a plurality of control signals according to a set selection state, and a plurality of driving circuit units receiving a reference signal and the plurality of control signals to control the plurality of switch devices, wherein the plurality of switch devices determine a level of the output signal by the plurality of control signal.

Abstract: An integrated circuit chip includes: an internal circuit; a data output circuit configured to output a data packet of the internal circuit in response to a strobe signal; an oscillator configured to generate a first clock signal; a divider configured to divide the first clock signal and generate a second clock signal; and a strobe signal supply unit configured to supply the second clock signal as the strobe signal during an initial period of transmission of the data packet and supply the first clock signal as the strobe signal after the initial period.

Abstract: A signal transmission system (10) includes a signal generator circuit (12); a signal regenerator circuit (14) coupled to the signal generator circuit by conductive lines (16, 18). The signal regenerator circuit receives input signals from the signal generator circuit on the conductive lines, and the regenerator circuit includes cascoded transistors (39, 41) and level-shifting circuits (26) coupled to the cascoded transistors. The cascoded transistors amplify the input signals to provide amplified signals. The level-shifting circuits shift a voltage level of the amplified signals to provide level-shifted signals.

Abstract: A signal processing circuit of the present invention includes: first and second input terminals; an output terminal; a bootstrap capacitor; a first output section connected to the second input terminal and the output terminal; a second output section connected to the first input terminal, a first power source, and the output terminal; and an electric charge control section for controlling the electric charge of the bootstrap capacitor, the electric charge control section being connected to the first input terminal, the electric charge control section and the first output section being connected to each other via a relay section for either electrically connecting the electric charge control section and the first output section to each other or electrically blocking the electric charge control section and the first output section from each other, the electric charge control section including a resistor connected to a second power source.

Abstract: An output circuit for a bus whose output node is connected to a bus, including a first current source connected to a first reference potential, a first semiconductor switching element connected between the first current source and the output node, a current control circuit for controlling the first semiconductor switching element such that the first current source and the output node are connected when a voltage of the output node is lower than a reference voltage, and the first current source and the output node are disconnected when a voltage of the output node is higher than the reference voltage, and a voltage generating circuit which is connected between the output node and a second reference potential, and includes a second semiconductor switching element turned on/off based on an output control signal.

Abstract: A floating gate driver uses a single-end level shifter to translate a set signal and a reset signal induced by a rising edge and a falling edge of a switch signal to a common output terminal to generate an output voltage for a bistable circuit to generate a level shifted switch signal. Under control of a well transient detect signal asserted by detecting noise in the output voltage, a masking circuit between the single-end level shifter and the bistable circuit masks noise in the output voltage. This configuration has lower area penalty and better noise immunity.

Abstract: A driver circuit includes a driver output stage and an operational amplifier. The driver output stage has a high-level voltage input and a low-level voltage input, and is operable to generate an output voltage responsive to a gate voltage applied to the driver output stage. The operational amplifier is operable to regulate the gate voltage applied to the driver output stage so that the output voltage corresponds to a control signal input to the operational amplifier. A first supply voltage connected to the high-level voltage input of the driver output stage is higher than a maximum value of the control signal, and a second supply voltage connected to the low-level voltage input of the driver output stage is lower than a minimum value of the control signal.

Abstract: A drive circuit is provided with a charge pump including a capacitor. The capacitor of the charge pump is configured to be charged in the first stage and to be connected with the gate terminal of the switching device in the second stage. The charge pump is configured to be able to adjust a charging voltage charged in the capacitor according to an order signal.

Abstract: A driving circuit of a schottky type transistor includes an input terminal supplied with an input signal, and an output terminal connected to a gate of the schottky type transistor. The driving circuit outputs a first voltage lower than a breakdown voltage of the schottky type transistor to the output terminal at the time of rising of the input signal, and thereafter supplies a second voltage higher than the breakdown voltage to a resistance connected to the output terminal.

Abstract: To provide a semiconductor device with reduced power consumption that includes a selection transistor. To provide a semiconductor device capable of high-speed operation without increasing a power supply potential. A buffer circuit connected to a gate line has a function of generating a potential higher than a high power supply potential by using the high power supply potential and outputs the potential in response to a selection signal. Specifically, a bootstrap circuit boosts a high power supply potential that is input to an inverter that is the closest to an output side in the buffer circuit. Further, the bootstrap circuit boosts the potential when the gate line is selected, and does not boost the potential when the gate line is not selected.

Abstract: A method of driving an output terminal to a voltage, in which an input signal is received, an appropriate output voltage and output voltage range are determined based on the input signal, an output driver is configured to a first mode and the output driver drives the output terminal to a voltage within the voltage range, the output driver is configured to a second mode and the output driver drives the output terminal to a voltage approximately equal to the appropriate output voltage.

Abstract: A high-speed current-mode clock driver includes feedback circuitry to maintain the voltage swing of a biasing node within a defined range. The current-mode clock driver includes a PMOS and an NMOS transistor receiving an oscillating signal at their gate terminals. The drain terminals of the PMOS and NMOS transistors are respectively coupled to input terminals of first and second variable conductivity circuits whose output terminals are coupled to a common node. A control circuit increases the conductivities of the first and second variable conductivity circuits in response to decreases in voltage swing of the common node, and decreases the conductivities of the first and second variable conductivity circuits in response to increases in voltage swing of the common node. The first and second variable conductivity circuits are optionally PMOS and NMOS transistors respectively.

Abstract: A circuit includes: a pull down circuit including a first PFET and a second PFET connected in series between a pad of a USB circuit and ground; and a pull up circuit including a first NFET and a second NFET connected in series between the pad and a supply voltage. The circuit includes: a third PFET connected to a gate of the first PFET and a gate of the second PFET; a third NFET connected to a gate of the first NFET and a gate of the second NFET; a fourth PFET connected to the first NFET and the second NFET; and a fourth NFET connected to the first PFET and the second PFET. A pad voltage has a nominal minimum and maximum. Each of the first PFET, the second PFET, the first NFET, and the second NFET has a nominal voltage less than the pad voltage nominal maximum.

Abstract: A gate driving apparatus according to the embodiment includes a first switching device, a second switching device that outputs a signal to charge a capacitance of the first switching device, a third switching device connected in parallel to the second switching device to prevent a drop of a voltage output from the second switching device, and a fourth switching device that outputs a signal to discharge the capacitance of the first switching device. An NMOS transistor is used as a main switching device and a PMOS transistor connected in parallel to the NMOS transistor is used as a sub-switching device, so that the chip size is reduced without dropping the output voltage of the gate driving apparatus. The loss of the switching device is prevented by preventing the output voltage of the gate driving apparatus from being dropped.

Abstract: An input/output (I/O) driver is disclosed that employs a compensation circuit to limit the voltages across devices of the driver from exceeding a defined threshold to allow lower voltage devices to implement the operation of the driver. In particular, the driver employs a pull-up circuit including first and second switching devices coupled between a first voltage rail and an output of the driver. The driver employs a pull-down circuit including third and fourth switching devices coupled between the output and a second voltage rail. The I/O driver employs a compensation circuit configured to apply a compensation voltage to the node between the first and second switching devices and to the node between the third and fourth switching devices at the appropriate times to maintain the respective voltages across the second and third switching devices at or below a defined threshold, such as a reliability limit, during the operation of the driver.

Abstract: A signal output circuit includes a signal transfer unit configured to transfer a signal of a first line to a pull-up line during an activation period of a first clock, transfer the signal of the first line to a pull-down line during a deactivation period of a second clock, transfer a signal of a second line to the pull-up line during a deactivation period of the first clock, and transfer the signal of the second line to the pull-down line during an activation period of the second clock; and an output driving unit configured to pull-up drive an output node in response to a signal of the pull-up line and pull-down drive the output node in response to a signal of the pull-down line, wherein the first clock and the second clock have the activation periods longer than the deactivation periods.

Abstract: A high voltage waveform is generated that is similar to a low voltage input waveform. The high voltage waveform is a series of pulses that are applied directly to the device. An error signal controls the frequency, magnitude, and duration of the pulses. A feedback signal derived from the high voltage waveform is compared with the input waveform to produce the error signal.

Abstract: In accordance with an embodiment, a circuit for driving a switch includes a driver circuit. The driver circuit includes a first output configured to be coupled to a gate of the JFET, a second output configured to be coupled to a gate of the MOSFET, a first power supply node, and a bias input configured to be coupled to the common node. The switch to be driven includes a JFET coupled to a MOSFET at a common node.

Abstract: A half bridge method and apparatus that provides a desired output using pulse width modulation and the predicted condition of a power supply is disclosed. The power supply is operatively connected to a first one the switch drivers of the switching elements of the half bridge. The condition of the power supply is predicted using of a model of power supply operating parameters. This model is used in conjunction with a signal applied to a second one of the switch drivers of the switching elements of the half bridge to determine whether an operating criterion for the power supply is satisfied. If the condition is satisfied then a signal to the first one of the switch drivers is enabled.