Abstract: A circuit is disclosed, in accordance with some embodiments. The circuit includes a transistor stage, a resistive element, a first tunable capacitive element and a second tunable capacitive element. The transistor stage includes a first input/output terminal and a second input/output terminal. The resistive element is connected to the transistor stage. The first tunable capacitive element is connected in parallel with the resistive element. The second tunable capacitive element is connected to the second input/output terminal of the transistor stage. The first tunable capacitive element and the second tunable capacitive element are configured to be selectively turned on and off to provide different frequency responses.

Abstract: An electrostatic actuator includes a fixed electrode and a movable electrode arranged to face the fixed electrode. The movable electrode is configured to be displaceable with respect to the fixed electrode and a fixed portion. An attractive force acts between the movable electrode and the fixed portion. In the electrostatic actuator, a non-linear vibration of the movable electrode when a voltage is applied to the fixed electrode and the movable electrode is reduced by the attractive force acting between the movable electrode and the fixed portion.

Abstract: A voltage converter arrangement includes a clocked voltage converter capable of generating an output voltage on the basis of an input voltage. The voltage converter arrangement further includes a first input regulating element connected between a first input voltage node and a second input voltage node, the second input voltage node having a reference potential. The first input regulating element is configured to allow a current flow so as to counteract fluctuations in the input current of the voltage converter arrangement. A corresponding method is also described.

Abstract: A liquid ejecting apparatus includes an integrated circuit, and a feedback circuit that feeds back a feedback signal. The integrated circuit includes a modulation circuit that output a modulation signal, a constant voltage output circuit that outputs a DC voltage signal, and an input terminal to which the feedback signal is input. The modulation circuit and the constant voltage output circuit are electrically coupled to the input terminal, a first line segment located between the input terminal and the constant voltage output circuit in a first straight line connecting the input terminal and the constant voltage output circuit at a shortest distance does not intersect the modulation circuit, and a second line segment located between the input terminal and the modulation circuit in a second straight line connecting the input terminal and the modulation circuit at a shortest distance does not intersect the constant voltage output circuit.

Abstract: A system includes a switching converter with an output inductor. The switching converter also includes a switch set with a switch node coupled to the output inductor. The switching converter also includes a first drive stage coupled to the switch set. The switching converter also includes a second drive stage coupled to the switch set. The switching converter also includes a controller coupled to the first drive stage and the second drive stage. The controller includes a supply voltage detector circuit. The controller also includes a level shifter coupled to an output of the supply voltage detector circuit. The controller also includes a selection circuit coupled between the level shifter and the second drive stage.

Abstract: An electronic device is provided. The electronic device includes a receiving circuit configured to wirelessly receive power and output AC power, a rectifying circuit configured to rectify the AC power from the receiving circuit, wherein the rectifying circuit may include a first P-MOSFET configured to transfer a positive amplitude of power to an output terminal of the rectifying circuit while the AC power has the positive amplitude and to prevent transferring a negative amplitude of power to the output terminal of the rectifying circuit while the AC power has the negative amplitude, and a forward loss compensating circuit connected with the first P-MOSFET configured to reduce a threshold voltage of the first P-MOSFET while the AC power has the positive amplitude.

Abstract: A line driver circuit is configured to provide a high spurious free dynamic range output and includes first and second output transistors and a control circuit. The first output transistor is controllable to pull an output node to a logic high state, and the second output transistor is controllable to pull the output node to a logic low state. The first control circuit is connected to a control input of the first output transistor and configured to establish a control signal at the control input of the first output transistor while the second output transistor is in a low impedance operating state to reduce an imbalance in turn-on delay between the first output transistor and the second output transistor.

Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

Abstract: A system may include first and second node, switch, driver, capacitor, and second driver. The first node may be at first voltage. The second node may be at second voltage. The switch may be coupled to the second node and output of the second driver and configured to receive input at third voltage and voltage at fourth voltage and to provide the input to the second node when the fourth voltage is greater than the third voltage. The driver may be coupled to the first and second nodes and configured to receive driver input and to generate intermediate voltage based on the driver input. The capacitor may be coupled to the driver to shift the intermediate voltage. The second driver may be coupled to the second node and the driver and configured to receive second driver input and the shifted intermediate voltage to generate the voltage at the fourth voltage.

Abstract: An electronic device for communicating with an external device includes a connector, a controller, a first switch element, a second switch element, a first voltage source, a second voltage source, a third voltage source, and a fourth voltage source. When the external device is coupled to the connector, the connector receives a device existence voltage from the external device. The controller generates a first control signal and a second control signal according to the device existence voltage. The first switch element couples the first voltage source or the second voltage source to the connector according to the first control signal. The second switch element couples the third voltage source or the fourth voltage source to an output node according to the second control signal.

Abstract: According to a first example aspect there is provided a charge pump circuit that includes a first chopper circuit configured to switch first and second chopper circuit outputs between first and second chopper circuit inputs at a chopping frequency, wherein successive input signals at the first chopper circuit input are output alternatively at the first and second chopper circuit outputs in successive cycles of the chopping frequency and successive input signals at the second chopper circuit input are output alternatively at the second and first chopper circuit outputs in successive cycles of the chopping frequency. A differential charge pump is configured to receive the signals output from the first and second chopper circuit outputs and produce corresponding first and second charge pumped signals.

Abstract: An input buffer circuit is disclosed, which relates to a technology for a receiver circuit including a plurality of input buffers having different characteristics. The input buffer circuit includes a first buffer configured to output a first input signal by buffering a command address received based on a flag signal, a second buffer configured to output a second input signal by buffering the command address based on the flag signal, a first delay matching circuit configured to output a first matching signal by delaying the first input signal by a first delay time, a second delay matching circuit configured to output a second matching signal by delaying the second input signal by a second delay time, and a selection circuit configured to select any one of the first matching signal and the second matching signal based on a selection signal.

Abstract: A multifunctional infrared (IR) module is configured for multiple IR applications without an additional microcontroller to be integrated into a computing device and is able to utilize voltage control instead of current control. The multifunctional IR module includes an IR light emitting diode (LED), and an IR receiver (e.g., photodiode or phototransistor). In one embodiment, the multifunctional IR module includes a resistor that is connected to the cathode of the IR LED and the drain of a transistor, with the source of the transistor grounded. In some embodiments, the multifunctional IR module additionally includes a red LED. Various configurations of the multifunctional IR module are able to perform one or more of the following functions: IR in (receiving IR signals), IR out (generating IR signals), heart rate sensing, SpO2 (oxygen saturation) sensing, distance/proximity detection, gesture detection, LED control, and ambient light detection.

Abstract: A secondary protection IC is connected in parallel with a rechargeable battery and controls the charge and discharge of the rechargeable battery separately from a primary protection IC. The secondary protection IC includes a detection circuit that detects an overcharge or overdischarge of the rechargeable battery, a regulator that stabilizes the voltage of the rechargeable battery and outputs the stabilized voltage to the outside of the rechargeable battery, and a control terminal that controls the regulator with a control signal. Each of the detection circuit and the regulator performs a normal operation or stops operating based on the voltage of the rechargeable battery and the control signal.

Abstract: A charge pump and a differential phase locked loop incorporating the charge pump. The charge pump includes a differential charge pump and an auxiliary charge pump. The differential charge pump has differential inputs and primary and mirror outputs. The differential charge pump is responsive to a down signal at the differential inputs to provide a negative current at the primary output and a positive current at the mirror output, and further responsive to an up signal at the differential inputs to provide a positive current at the primary output and a negative current at the mirror output. The auxiliary charge pump has differential inputs and an auxiliary output coupled to the mirror output of the differential charge pump. The differential charge pump is responsive to the down signal at the differential inputs to provide a negative current at the auxiliary output, and responsive to the up signal at the differential inputs to provide a positive current at the auxiliary output.

Abstract: A current mode logic buffer includes a differential pair of input transistors comprising a first input transistor and a second input transistor, a first output load resistor coupled in series with the first input transistor, a second output load resistor coupled in series with the second input transistor, a first output at a first node between the first output load resistor and the first input transistor, a second output at a second node between the second output load resistor and the second input transistor, a first hold capacitor configured to provide a semi-constant voltage source to the first output via a first low-resistance path, and a second hold capacitor configured to provide a semi-constant voltage source to the second output via a second low-resistance path.

Abstract: A system comprises a transmitter coupled to a receiver through a plurality of transmission lines, wherein the transmitter comprises a continuous time linear equalizer and a voltage mode driver. The continuous time linear equalizer comprises a differential input stage, a RC degeneration network coupled to the differential input stage and a current source coupled to the differential input stage. The continuous time linear equalizer and the voltage mode driver share a same input port and a same output port.

Abstract: An apparatus and method (4,5,6,7,2) for capacitive measurement of electrophysiological signals (1) suppresses or reduces motion artifacts by providing a feedback mechanism. An average voltage between a capacitive sensor electrode (1) and the body (3) is controlled so as to reduce or minimize motion-induced signals.

Abstract: Various implementations include circuits, devices and/or methods that enable the repeated generation of controlled surges with lower risk of component failure. Some implementations include a discharge control assembly including a discharge circuit and a controller. In some implementations, the discharge circuit is selectively connectable to a driver circuit, and the discharge circuit is configured to provide a dominant discharge path for the driver circuit when the driver circuit is effectively decoupled from a first load in order to decay an electrical condition of the driver circuit produced prior to the driver circuit being effectively decoupled from the first load. In some implementations, the controller is configured to selectively connect the driver circuit to a combination of the discharge circuit and the first load, and in at least one combination the discharge circuit is effectively coupled to the driver circuit when the first load is effectively decoupled from the driver circuit.

Abstract: The present invention has an object to provide a semiconductor device that has protective functions and is capable of achieving miniaturization and cost reduction. A semiconductor device according to the present invention includes a switching element, a drive circuit, and a control circuit. When a high-level drive control signal is output from the drive circuit, the control circuit stops driving of the switching element and charges an electric charge storing capacitor. When a low-level drive control signal is output from the drive circuit, the control circuit drives the switching element using electric charges stored in the electric charge storing capacitor.

Abstract: A semiconductor device includes: a main driving unit configured to receive an output data and to drive the received data to a data output pad; a pre-emphasis data generation unit configured to compare a delayed data obtained by delaying the output data by one data period with the output data, to delay the comparison result by one data period, and to output the delayed data as pre-emphasis data; and a pre-emphasis driving unit configured to receive the pre-emphasis data and to drive the received data to the data output pad.

Abstract: The disclosed embodiments provide a circuit for driving a capacitive load. The circuit includes a first inductor with an input terminal and a load terminal, wherein the load terminal is coupled to the capacitive load. The circuit also includes four or more switching devices. The switching devices may hold a voltage on the load terminal at zero volts. Next, the switching devices may charge the capacitive load through the first inductor until the voltage on the load terminal reaches a first input voltage supplied by a voltage source. The switching devices may then hold the voltage on the load terminal at the first input voltage. Finally, the switching devices may discharge the capacitive load through the first inductor until the voltage on the load terminal reaches zero volts.

Abstract: A capacitive load drive circuit includes first and second capacitive loads, first and second connection path selection sections, and a voltage generation section. The first capacitive load and the second capacitive load are configured to charge and discharge in accordance with a drive signal. The first connection path selection section is configured to selectively supply a plurality of voltages to the first capacitive load, the first connection path selection section being arranged so as to correspond to the first capacitive load. The second connection path selection section is configured to selectively supply a plurality of voltages to the second capacitive load. The second connection path selection section is arranged so as to correspond to the second capacitive load. The voltage generation section is configured to generate and supply the voltages shared by the first connection path selection section and the second connection path selection section.

Abstract: A tunable buffer circuit has a first tunable buffer cell receiving an input signal. A first transmission line is coupled to the first tunable buffer cell. A second tunable buffer cell is coupled to the first transmission line. A center frequency and bandwidth of the second tunable buffer cell is matched to a center frequency and bandwidth of the first tunable buffer cell to achieve low phase noise with low power. Additional transmission lines and tunable buffer cells can be cascaded in the tunable buffer circuit. Each tunable buffer cell has first and second transistors including first and second conduction terminals and control terminal coupled for receiving the input signal. An inductor and tunable capacitor are coupled between the first conduction terminals of the first and second transistor. A digital signal adjusts the tunable buffer cells in response to an RSSI which monitors the output for proper signal strength.

Abstract: An output driver circuit includes first, second, third, and fourth transistors having a common current path, wherein a gate of the first transistor receives a first switching signal, a gate of the second transistor receives a first reference voltage, a gate of the third transistor receives a second reference voltage, and a gate of the fourth transistor receives a second switching signal, and wherein a first capacitor is coupled between the gate of the first transistor and the gate of the third transistor, a second capacitor is coupled between the gate of the second transistor and the gate of the fourth transistor, and an output signal is provided at a node coupling the second and third transistors.

Abstract: A method for driving a piezoelectric transducer is provided. An input signal is received. At least one of a plurality of modes is selected for a buck-boost stage from a comparison of a desired voltage on a capacitor to a first threshold and a second threshold, where the desired voltage is determined from the input signal. The piezoelectric transducer is then driven substantially within the audio band using the desired voltage on the capacitor using an H-bridge that changes state with each zero-crossing.

Abstract: Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.

Abstract: An output buffer has a first transistor and a voltage mitigation second transistor. The first transistor is configured to generate a voltage value corresponding to the power-supply voltage in response to an input signal. The second transistor is provided between an output line and the first transistor. A gate terminal of the second transistor is applied with a power-supply bias voltage which turns the second transistor on and makes a voltage between gate and source terminals of the second transistor constant in accordance with a power-supply voltage.

Abstract: A semiconductor device includes a normal code generation unit capable of generating a normal code, a test code output unit capable of storing a plurality of preliminary test codes to output a test code in response to a test control signal, and a reference voltage generation unit capable of generating a normal reference voltage in a normal operation mode and generating a test reference voltage in a test operation mode in response to the normal code and the test code.

Abstract: Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.

Abstract: A driving circuit includes a common well. The driving circuit further includes a first output buffer having a bulk connected to the common well, the first output buffer having a first terminal configured to receive a first signal, and having a second terminal connected to the common well. The driving circuit further includes a second output buffer having a bulk connected to the common well, the second output buffer having a first terminal configured to receive the first signal, wherein a second terminal of the second output buffer disconnected from the common well. The driving circuit further includes a first driver connected to the second terminal of the first output buffer and a second driver connected to the second terminal of the second output buffer.

Abstract: Described is an apparatus which comprises: a first node to provide an un-gated power supply; a second node to provide a threshold dependent supply; an inverter with an input and an output, the inverter coupled to the first and second nodes, the inverter to receive the un-gated power supply at its power supply node, and to receive the threshold dependent supply for supplying ground supply at its ground node; and a transistor with its gate terminal coupled to the output of the inverter, the transistor to provide gated power supply to one or more logic units.

Abstract: A semiconductor device and a power voltage supply circuit for a test operation of a semiconductor system including the semiconductor device. The semiconductor device receives first and second power supply voltages in a normal operation mode from an external device and receives the first power supply voltage in a test operation mode. The semiconductor device includes a voltage level setting unit configured to set a power connection node at a voltage between a voltage level of a first power supply voltage terminal and a voltage level of a ground voltage terminal according to an operation mode signal, and a voltage driving unit configured to drive a second power supply voltage terminal with the first power supply voltage in the test operation mode, wherein the driving power is controlled according to the voltage level of the power connection node.

Abstract: A buffer control circuit includes a current supply unit configured to supply current and adjust the current in response to codes, an amplifying buffer configured to operate using the current and output a value obtained by comparing a reference potential and the reference potential, a second buffer configured to buffer an output of the first buffer, and a code generation unit configured to generate the codes in response to an output of the second buffer.

Abstract: A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled. Reducing early-edge jitter reduces the power and circuit complexity otherwise needed to turn the system on quickly.

Abstract: A load driving device includes a pulse driving circuit which has a capacitor between an output terminal and a ground potential, a level detection circuit which detects whether an output terminal voltage on the output terminal of the pulse driving circuit is at high level or at low level, a switching discharge unit for forming a discharge path through which electric charges charged in a capacitor are discharged by switching of a switch from a non-discharge side to a discharge side, and switching the switch to the discharge side over a discharge maintenance time in a state where the application of a pulse voltage by the pulse driving circuit stops and the output terminal voltage is maintained at high level, a post-discharge detection unit, and a determination unit.

Abstract: A drive control apparatus for a semiconductor device having a diode and a transistor includes: a current detection device of a current flowing through the diode; and a control device, which applies a gate drive voltage to the semiconductor device when an on-instruction signal is input. The control device compares the current detection signal with a current threshold value during a first period, in which the on-instruction signal is input, after a second period has elapsed from gate drive voltage application time, or gate drive voltage shut-off time. A transient variation is generated on the current detection signal in the second period. The control device shuts off the gate drive voltage when the current detection signal is equal to or larger than the current threshold value. The control device applies the gate drive voltage when the current detection signal is smaller than the current threshold value.

Abstract: A multi-chip system may include a plurality of chips, and a channel shared by the plurality of chips. At least one of the plurality of chips includes a transmission circuit configured to transmit a signal to the channel. Drivability of the transmission circuit is adjusted based on a number of the plurality of chips.

Abstract: A liquid discharge apparatus includes a discharge section, a charge supply source, first and second signal paths, a control signal generation section and a connection path selection section. The discharge section includes a nozzle configured and arranged to discharge a liquid, a pressure chamber in communication with the nozzle, and a piezoelectric element provided for the pressure chamber. A first voltage is applied by the charge supply source through the first signal path. A second voltage higher than the first voltage is applied by the charge supply source through the second signal path. The control signal generation section is configured to supply a control signal. The connection path selection section is configured to use the first or second signal path to electrically connect the piezoelectric element and the charge supply source in accordance with a voltage of the control signal and a holding voltage of the piezoelectric element.

Abstract: A switching control circuit controls a switching circuit based on decoded signals obtained by decoding several input signals. The switching control circuit is includes a decoder circuit that outputs decoded signals obtained by decoding coded input data signals. The switching control circuit includes a driver circuit that generates control signals for controlling the switching circuit based on the decoded signals. The switching control circuit is provided with a synchronous control circuit that synchronizes the input signals before outputting them for decoding.

Abstract: In accordance with an embodiment, a method of operating a gate driving circuit includes monitoring a signal integrity at an output of the gate driving circuit. If the signal integrity is poor based on the monitoring, output of the gate driving circuit is placed in a high impedance state and an external signal integrity failure signal is asserted.

Abstract: Operation of a digital power amplifier for power amplification of a modulated signal is stopped in a period in which a voltage value of a drive signal applied to a capacitive load is constant, to thereby suppress power loss. The power amplification is stopped either when half a period of time when the modulated signal in a first voltage state maintains the first voltage state elapses or when half a period of time when the modulated signal in a second voltage state which is lower in voltage than the first voltage state maintains the second voltage state elapses. Accordingly, when electric current does not flow in a inductor of a low pass filter, it is possible to stop the power amplification. Thus, it is possible to prevent generation of voltage fluctuation in the drive signal due to an electromotive force caused by a self-induction phenomenon of the inductor.

Abstract: Disclosed herein are a tunable capacitance control circuit and a tunable capacitance control method. The tunable capacitance control method is a tunable capacitance control method by a tunable capacitance control circuit including an MIM capacitor, a plurality of FET switches, and a control unit, wherein the control unit outputs control signals allowing only one of the plurality of (n) FET switches to be switched on and the remaining (n?1) FET switches to be switched off to the plurality of FET switches, thereby obtaining a desired tunable capacitance value.

Abstract: Recycling energy in a clock distribution network is provided. A circuit includes a clock driver associated with a clock signal and having an output connected to a first load capacitance. The circuit also includes a second load capacitance connected in parallel with the first load capacitance. The circuit further includes a power transfer circuit including an inductor and a transmission gate connected in series between the first load capacitance and the second load capacitance. The power transfer circuit controls a flow of energy between the first load capacitance and the second load capacitance based on the clock signal.

Abstract: There are provided a gate driver circuit and an operating method thereof. The gate driver circuit includes an output signal generating unit including a plurality of switch devices generating output signals, a selecting circuit unit generating a plurality of control signals according to a set selection state, and a plurality of driving circuit units receiving a reference signal and the plurality of control signals to control the plurality of switch devices, wherein the plurality of switch devices determine a level of the output signal by the plurality of control signal.

Abstract: An integrated circuit chip includes: an internal circuit; a data output circuit configured to output a data packet of the internal circuit in response to a strobe signal; an oscillator configured to generate a first clock signal; a divider configured to divide the first clock signal and generate a second clock signal; and a strobe signal supply unit configured to supply the second clock signal as the strobe signal during an initial period of transmission of the data packet and supply the first clock signal as the strobe signal after the initial period.

Abstract: An integrated circuit chip includes: an internal circuit; a data output circuit configured to output a data packet of the internal circuit in response to a strobe signal; an oscillator configured to generate a first clock signal; a divider configured to divide the first clock signal and generate a second clock signal; and a strobe signal supply unit configured to supply the second clock signal as the strobe signal during an initial period of transmission of the data packet and supply the first clock signal as the strobe signal after the initial period.

Abstract: Systems provide for a test system for capacitors in a digitally controllable oscillator (DCO). The system includes: capacitor toggling logic configured to switch on and off a selected one of the capacitors at a modulation frequency; a tone generator configured to generate a tone; a mixer configured to receive the tone and an output carrier signal from the DCO while the capacitor toggling logic is switching the selected one of the capacitors on and off and to output an intermediate frequency signal having FM sidebands based on the modulation frequency and relative capacitor size; and an evaluation circuit configured to evaluate a frequency deviation associated with the selected one of the capacitors based on at least one of the FM sidebands.

Abstract: A gate driving apparatus according to the embodiment includes a first switching device, a second switching device that outputs a signal to charge a capacitance of the first switching device, a third switching device connected in parallel to the second switching device to prevent a drop of a voltage output from the second switching device, and a fourth switching device that outputs a signal to discharge the capacitance of the first switching device. An NMOS transistor is used as a main switching device and a PMOS transistor connected in parallel to the NMOS transistor is used as a sub-switching device, so that the chip size is reduced without dropping the output voltage of the gate driving apparatus. The loss of the switching device is prevented by preventing the output voltage of the gate driving apparatus from being dropped.

Abstract: A high voltage waveform is generated that is similar to a low voltage input waveform. The high voltage waveform is a series of pulses that are applied directly to the device. An error signal controls the frequency, magnitude, and duration of the pulses. A feedback signal derived from the high voltage waveform is compared with the input waveform to produce the error signal.