With Logic Or Bistable Circuit Patents (Class 327/12)
  • Patent number: 10423247
    Abstract: A position detection apparatus of the electrostatic coupling type is provided, to detect not only a position of a pointer but also information other than the position information such as, for example, pointer pressure or side switch information. The pointer transmits two codes such that a pressure applied to a pen tip is associated with a time difference between the two codes. A position detector carries out a correlation matching operation between signals generated in reception conductors and correlation calculation codes corresponding to the two codes, to thereby detect a position on a sensor section pointed to by the pointer from a result of the correlation matching operation and based on at least one of the codes.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: September 24, 2019
    Assignee: Wacom Co., Ltd.
    Inventors: Yasuo Oda, Sadao Yamamoto, Yoshihisa Sugiyama
  • Patent number: 10389368
    Abstract: Aspects of the present disclosure include a dual path phase locked loop (PLL) circuit with a switched capacitor filter topology along with systems, method, devices, and other circuits related thereto. The dual path PLL circuit includes an integral path and a proportional path. Both the integral path and proportional path include a charge pump and a loop filter. The outputs of a phase frequency detector (PFD) are sent to both charge pumps. The output of the integral path charge pump is connected to a capacitor, and the voltage on capacitor is used as the integral path control voltage for a voltage-controlled oscillator (VCO). A switched capacitor network is connected to the output of the proportional path charge pump and used to generate the proportional path control voltage for the VCO. Together, the two control voltages dictate the VCO's output frequency.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: August 20, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Fuyue Wang, Ling Chen, Thomas Evan Wilson, Jianyun Zhang, Eric Harris Naviasky
  • Patent number: 10225115
    Abstract: A system and a method for detecting a low-frequency periodic signal (LFPS) include at least one comparator performing a threshold comparison on an analog input signal over a period of time. A sampling circuit generates digital signals by sampling an output of the at least one comparator. A digital detection circuit applies a set of detection rules to the digital signals. The detection rules are configured to detect a presence or an absence of an LFPS based on predefined criteria concerning characteristics of the digital signals.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: March 5, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Mathieu Gagnon, Santiago Luis Bortman, Eric Harris Naviasky, Guillaume Fortin, Julien Faucher
  • Patent number: 10148259
    Abstract: A skew control loop circuit for controlling a skew between a plurality of digital signals, and a semiconductor device, and a method of operation, for the same, may be provided. The skew control loop circuit comprises a skew detector for detecting a phase difference between the digital signals, a skew control circuit adapted for controlling an operation of the skew control loop circuit. The skew control circuit is operable in a first operating mode and in a second operating mode. The skew control loop circuit comprises also an enable input of the skew detector, wherein the enable input is adapted for receiving an enable input signal, generated by the skew control circuit, wherein the enable input is adapted for selectively enable or disable a phase detection operation of the skew detector, and wherein the enable input signal is only active during the first operating mode.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: December 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Andreas H. A. Arp, Fatih Cilek, Michael V. Koch, Matthias Ringe
  • Patent number: 10038450
    Abstract: A circuit for transmitting data in an integrated circuit device is described. The circuit comprises a first data width conversion circuit configured to receive a first portion of transmit data to be transmitted in parallel; a first parallel-in, serial-out circuit configured to receive an output of the first data width conversion circuit; a first reset timer configured to provide a first reset signal to enable resetting the first data width conversion circuit; a second data width conversion circuit configured to receive a second portion of the transmit data; a second parallel-in, serial-out circuit configured to receive an output of the second data width conversion circuit; and a second reset timer configured to provide a second reset signal to enable resetting the second data width conversion circuit.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: July 31, 2018
    Assignee: XILINX, INC.
    Inventor: Warren E. Cory
  • Patent number: 10030975
    Abstract: A sensor (100, 200) for measuring a variable generates a sensor signal (S), oscillates at a drive frequency (fx), and includes: a rate demodulator (135), which demodulates the sensor signal (S) by multiplying it by a first demodulation signal, in order to generate a rate signal (R1), which contains information about the measured variable to be measured; a quadrature demodulator (140), which demodulates the sensor signal (S) by multiplying it by a second demodulation signal shifted by 90° with respect to the first demodulation signal, to generate a quadrature signal (Q1); and an analysis circuit (170), which determines whether the quadrature signal (Q1) or a signal (Q2) derived therefrom is subject to a periodic oscillation and, if a periodic oscillation is present, outputs a status signal (Xst) having a value which indicates that the instantaneous rate signal (R1) is influenced by an external interference acting on the sensor (100, 200).
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: July 24, 2018
    Assignee: ROBERT BOSCH GMBH
    Inventor: Thorsten Balslink
  • Patent number: 10020840
    Abstract: Methods and devices for mitigating interference with a signal of a frequency hopping spread spectrum system are disclosed. A second signal is detected, and a property of the second signal is determined. At least one of a set of designated frequency channels used by the frequency hopping spread spectrum system is determined as having a property most similar to that of the second signal. The usage, by the frequency hopping spread spectrum system, of the at least one most similar designated frequency channel is then modified, for communication of data.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: July 10, 2018
    Assignee: Binatone Electronics Ltd
    Inventors: Heung Sang Lee, Hung Pong Chow, Wai Kuen Tin
  • Patent number: 10003343
    Abstract: A phase locked loop circuit comprising: a phase detector configured to compare the phase of an input signal with the phase of a feedback signal in order to provide an up-phase signal and a down-phase-signal; an oscillator-driver configured to: apply an up-weighting-value to the up-phase signal in order to provide a weighted-up-phase signal; apply a down-weighting-value to the down-phase signal in order to provide a weighted-down-phase signal; and combine the weighted-up-phase signal with the weighted-down-phase signal in order to provide an oscillator-driver-output-signal; and a controller configured to: set the up-weighting-value and the down-phase-weighting as a first-set-of-unequal-weighting-values, and replace the first-set-of-unequal-weighting-values with a second-set-of-unequal-weighting-values if an operating signal of the phase locked loop circuit reaches a limit-value without satisfying a threshold value.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: June 19, 2018
    Assignee: NXP B.V.
    Inventors: Kaveh Kianush, Evert-Jan Pol, Marcel Van De Gevel
  • Patent number: 9979533
    Abstract: A serial data receiver may include an edge detector and a digital integrator. The edge detector may be configured to provide one or more edge detection signals defining an edge detection indication in response to a comparison between two successive samples of a receiver input signal. The edge detection indication may represent a detected negative edge, a detected positive edge, or no detected edge. The digital integrator may be configured to provide a receiver output signal in response to integration of the one or more edge detection signals.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: May 22, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Matthew David Sienko, Meysam Azin, Weibo Hu
  • Patent number: 9853634
    Abstract: Systems and methods associated with phase frequency detection are disclosed. In one illustrative implementation, a phase frequency detection (PFD) circuit device may comprise first circuitry and second circuitry having a set input, a reset input, and an output, wherein the set input has a higher priority than the reset input, and additional circuitry arranged and operatively coupled to provide advantageous operation of the PFD circuit device. According to some implementations, for example, systems and methods with clock edge overriding reset features, extended detection range(s), and/or reduction of reverse charge after cycle slipping are provided.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: December 26, 2017
    Assignee: GSI Technology, Inc.
    Inventor: Chao-Hung Chang
  • Patent number: 9805778
    Abstract: A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system latch section latches, with a system clock, check data latched by the strobe latch section. Based on a comparison by an expected value comparison section and a determination by a delay determination section, the optimal strobe signal with the optimal delay is selected from among the delayed strobe signals produced in the strobe delay selection section. Then, data from the memory is delayed through delay circuits in a data delay selection section, thus obtaining a plurality of delayed data, and the optimal data with the optimal delay is selected from among the plurality of delayed data based on the comparison by the expected value comparison section and the determination by the delay determination section.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: October 31, 2017
    Assignee: SOCIONEXT INC.
    Inventors: Yoshihiro Kishimoto, Yoichiro Miki, Yuji Sekiguchi
  • Patent number: 9766278
    Abstract: A system and method utilize multiple, asynchronous, voltage isolated integrated power data circuits (IPDCs) to respectively determine one or more power parameters of a multi-phase power distribution system. In at least one embodiment, the power parameters represent differences between voltage phases of a multi-phase power distribution system. In at least one embodiment, the IPDCs each sense a voltage or current from a single phase of a three-phase power distribution system. Additionally, the IPDCs are electrically isolated from each other and, thus, in at least one embodiment, can utilize voltage divider or shunt resistor sensing without being subject to high voltages representative of the difference between voltage phases. Additionally, in at least one embodiment, each of the IPDCs utilizes a separate clock signal to determine phase sequence and phase angle deltas of one or more three phase voltages of the three-phase power distribution system.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: September 19, 2017
    Assignee: Cirrus Logic, Inc.
    Inventors: Bala Vishnu Shankar Rao, Roderick D. Holley, II
  • Patent number: 9768788
    Abstract: Described is a phase-locked loop with lower power charge pump. The phase-locked loop comprises: a phase frequency detector to compare a reference clock and a feedback clock and generate a pulse based on the comparison, a charge pump to provide a charge signal corresponding to the pulse, a bias generator to provide biasing for the charge pump, wherein the bias generator is operable to receive a bias enable signal from the phase frequency detector and the bias generator is disabled when the bias enable signal is not asserted, a loop filter coupled to the output of the charge pump to provide a control signal responsive to the charge signal, and a voltage-controlled oscillator (VCO), wherein the oscillating frequency of the VCO is controlled by the control signal.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: September 19, 2017
    Assignee: Intel Corporation
    Inventors: Gennady Goltman, Yongping Fan, Kuan-Yueh Shen
  • Patent number: 9692429
    Abstract: Systems and methods are disclosed relating to fields of clock/data acquisition or handling, such as clock/data locking and the like. In one exemplary implementation, phase lock loop (PLL) circuitry may comprise voltage controlled oscillator (VCO) circuitry, phase frequency detector, converting circuitry, and frequency detector (FD) circuitry that outputs a frequency difference signal proportional to frequency difference between frequencies of a feedback clock signal and a reference clock signal.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: June 27, 2017
    Assignee: GSI Technology, Inc.
    Inventor: Chao-Hung Chang
  • Patent number: 9685212
    Abstract: A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system latch section latches, with a system clock, check data latched by the strobe latch section. Based on a comparison by an expected value comparison section and a determination by a delay determination section, the optimal strobe signal with the optimal delay is selected from among the delayed strobe signals produced in the strobe delay selection section. Then, data from the memory is delayed through delay circuits in a data delay selection section, thus obtaining a plurality of delayed data, and the optimal data with the optimal delay is selected from among the plurality of delayed data based on the comparison by the expected value comparison section and the determination by the delay determination section.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: June 20, 2017
    Assignee: SOCIONEXT INC.
    Inventors: Yoshihiro Kishimoto, Yoichiro Miki, Yuji Sekiguchi
  • Patent number: 9673795
    Abstract: An integrated circuit includes a data sampler and a digital logic circuit. The data sampler provides multiple signal samples at a speed twice a symbol rate according to a local clock signal and the inverted local clock signal. The signal samples include a first symbol sample, and a second symbol sample that occurs later than the first symbol sample. The signal samples further include an interpolated sample between the first and second symbol samples. The digital logic circuit compares the first symbol sample with the interpolated sample to generate pre phase correction data, and compares the second symbol sample with the interpolated sample to generate post phase correction data. The pre phase correction data is generated earlier than the post phase correction data. The local clock signal and the inverted local clock signal have substantially a phase difference of 180 degrees.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: June 6, 2017
    Assignee: MStar Semiconductor, Inc.
    Inventors: Meng-Tse Weng, Jiunn-Yih Lee
  • Patent number: 9660719
    Abstract: A method for minimizing propagation time of at least one queued-up datalink TPDU comprises determining whether a current TPDU ready for transmission requires acknowledgement; transmitting the current TPDU, starting a retry timer, and setting a transmission count to one, when acknowledgement required; determining whether acknowledgement received after transmitting the current TPDU; determining whether a pending TPDU is awaiting transmission when acknowledgement is not received; when a pending TPDU is awaiting transmission, determining whether elapsed wait time of the current TPDU is greater than a preselected minimum; incrementing the transmission count by one when elapsed wait time is greater than the preselected minimum; determining again whether there is a pending TPDU awaiting transmission when the transmission count is less than a predetermined maximum and an inactivity timer has not expired; and when there is still at least one pending TPDU awaiting transmission, retransmitting the current TPDU and resta
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: May 23, 2017
    Assignee: Honeywell International Inc.
    Inventors: Thomas D. Judd, Thomas F. McGuffin
  • Patent number: 9596040
    Abstract: An initial phase of each output signal generated by a plurality of radio frequency (RF) front-end circuits is determined by mixing an input signal with a mixing signal in a mixer of the corresponding RF front-end circuit. To that end, a time difference for each of the plurality of RF front-end circuits is determined by measuring a time difference between a reference signal (common to all of the RF front-end circuits) and the mixing signal of each RF front-end circuit. The initial phase for each output signal is then determined based on the measured time difference for the corresponding RF front-end circuit. Determining the initial phase in this manner accounts for any uncertainty of the phase when the RF front-end circuits are activated, enabling the phase of the corresponding antenna element to be accurately controlled.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: March 14, 2017
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Samu Laaja, Jyri Sintonen
  • Patent number: 9568520
    Abstract: A frequency monitoring circuit includes a monitoring lead, a D-type flip-flop, and a one-shot. The D-type flip-flop has a switchable logic state, a clear input, and a clock input. The one-shot has an input and an output connected to the D-type flip-flop clear input. The monitoring lead connects the one-shot input to the latch clock input for switching the logic state of the D-type flip-flop based on change in voltage applied to the monitoring lead.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: February 14, 2017
    Assignee: Hamilton Sundstrand Corporation
    Inventors: Sunil S. Patel, Frank J. Ludicky
  • Patent number: 9570131
    Abstract: A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system latch section latches, with a system clock, check data latched by the strobe latch section. Based on a comparison by an expected value comparison section and a determination by a delay determination section, the optimal strobe signal with the optimal delay is selected from among the delayed strobe signals produced in the strobe delay selection section. Then, data from the memory is delayed through delay circuits in a data delay selection section, thus obtaining a plurality of delayed data, and the optimal data with the optimal delay is selected from among the plurality of delayed data based on the comparison by the expected value comparison section and the determination by the delay determination section.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: February 14, 2017
    Assignee: SOCIONEXT INC.
    Inventors: Yoshihiro Kishimoto, Yoichiro Miki, Yuji Sekiguchi
  • Patent number: 9572211
    Abstract: In a pulse width modulation light emitting diode (LED) controller an error amplifier and output load switch are synchronously controlled to prevent service life shortening current overshoot through the LEDs and slowing discharging currents causing color temperature shifting in the light output from the LEDs. A plurality of switching arrangements for the error amplifier and the compensation network may be provided in a single integrated circuit LED dimming controller, and outputs for controlling a variety of differently configured output power switch combinations for disconnecting or shorting the LEDs, or disconnecting the output capacitor during off times of the modulated dimming control signal.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: February 14, 2017
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Andreas Reiter, Sean Stacy Steedman, Lucio Di Jasio, Joseph Julicher, Yong Yuenyongsgool
  • Patent number: 9548748
    Abstract: A PLL control system is provided that implements a phase tracer module to reduce lock time and output clock jitter. A second clock signal is generated by dividing a frequency of a reference clock signal. A feedback clock signal is generated based on a high-frequency clock signal from a digitally controlled oscillator (DCO) and a PLL feedback divide number. Lead/lag determination circuitry generates a lead/lag detection result that indicates whether the feedback clock signal leads or lags the second clock signal. A skew digitizer digitizes a skew between a falling edge of the second clock signal and a rising edge of the feedback clock signal to generate a skew signal. The phase tracer module processes the lead/lag detection result and the skew signal to generate a digital control signal that controls cycle time of the DCO to change frequency of the high-frequency clock signal.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: January 17, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Zhihong Luo, Yi Liang, Xiaobo Qiu, Swee Chuen Hoo, Yeung On Au, Benjamin Shui Chor Lau
  • Patent number: 9548745
    Abstract: A phase-detector circuit is disclosed. The phase-detector circuit comprises a plurality of phase comparators which detects a phase difference between receipt data and a clock signal of a plurality of clock signals having the same frequency and phase difference of a predetermined angle with each other, and generates and outputs signals for up/down signals for synchronizing a phase. The phase comparator generates and outputs a signal for the up/down signals having a pulse width including a detected phase-time difference and a predetermined delay time.
    Type: Grant
    Filed: May 14, 2014
    Date of Patent: January 17, 2017
    Assignee: RICOH COMPANY, LTD.
    Inventor: Dan Ozasa
  • Patent number: 9509296
    Abstract: Systems and methods herein may include or involve control circuitry that detects missing edges of reference and/or feedback clocks and may block the next N rising edges of the feedback clock or reference clock, respectively. In some implementations, a phase frequency detector (PFD) circuit comprises first circuitry including an output that outputs a missing edge signal. The first circuitry may include components arranged to detect a missing rising edge of one or both of a reference clock signal and a feedback clock signal. Second circuitry is coupled to the first circuitry and may include components arranged to generate one or both of a reference clock blocking signal and a feedback clock blocking signal based on the missing edge signal. Further, in some implementations, the blocking of the next N rising edges of the opposite clock may effectively increase the positive gain of the PFD.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: November 29, 2016
    Assignee: GSI Technology, Inc.
    Inventor: Yu-Chi Cheng
  • Patent number: 9473128
    Abstract: A pulse generation circuit for outputting a pulse signal at an output terminal, including: a PMOS, an NMOS, and a logic circuit. The PMOS has a source coupled to a first reference voltage level, a drain coupled to the output terminal, and a gate that receives a first gate control signal. The NMOS has a source coupled to a second reference voltage level, a drain coupled to the output terminal, and a gate that receives a second gate control signal. The logic circuit generates the first gate control signal according to a control signal and a first delay signal and generates the second gate control signal according to the control signal and a second delay signal. The first delay signal is relevant to the second gate control signal and the control signal. The second delay signal is relevant to the first gate control signal and the control signal.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: October 18, 2016
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Shih-Cheng Wang, Shih-Chieh Chen, Jian-Ru Lin, Chih-Cheng Lin
  • Patent number: 9472254
    Abstract: A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system latch section latches, with a system clock, check data latched by the strobe latch section. Based on a comparison by an expected value comparison section and a determination by a delay determination section, the optimal strobe signal with the optimal delay is selected from among the delayed strobe signals produced in the strobe delay selection section. Then, data from the memory is delayed through delay circuits in a data delay selection section, thus obtaining a plurality of delayed data, and the optimal data with the optimal delay is selected from among the plurality of delayed data based on the comparison by the expected value comparison section and the determination by the delay determination section.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: October 18, 2016
    Assignee: SOCIONEXT INC.
    Inventors: Yoshihiro Kishimoto, Yoichiro Miki, Yuji Sekiguchi
  • Patent number: 9438253
    Abstract: A current mode logic (CML) latch that includes a first transistor coupled to a second transistor, a third transistor coupled to a fourth transistor, a first capacitor connected to the first, second, third, and fourth transistors, and a second capacitor cross-coupled with the first capacitor and connected to the third and fourth transistors. The first and second transistors are configured to receive a data signal. The third and fourth transistors are configured to receive a clock signal.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: September 6, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Mustafa Ulvi Erdogan
  • Patent number: 9413364
    Abstract: Described is an apparatus for clock synchronization. The apparatus comprises a pair of interconnects; a first die including a first phase interpolator having an output coupled to one of the interconnects; and a second die, wherein the pair of interconnects is to couple the first die to the second die.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: August 9, 2016
    Assignee: Intel Corporation
    Inventors: Shenggao Li, Stefan Rusu
  • Patent number: 9407273
    Abstract: A DLL may include a DLL training circuit that provides a feedback signal to the DLL and receives a first delay code value from the DLL that corresponds to the delay added to the feedback signal to align a leading edge transition in the feedback signal with a leading edge transition in the reference clock signal. The DLL training circuit further provides an inverted feedback signal to the DLL and receives a second delay code value from the DLL that corresponds to the delay added to the inverted feedback signal to align a leading edge transition in the inverted feedback signal with a leading edge transition in the reference clock signal. The DLL selectively adds the delay code corresponding to the temporally smaller of the first delay code value or the second delay code value to the feedback signal to align the feedback signal with the reference clock signal.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: August 2, 2016
    Assignee: Intel Corporation
    Inventors: Fangxing Wei, Michael J Allen
  • Patent number: 9397646
    Abstract: Systems and methods for delay control are described herein. In one embodiment, a delay circuit comprises a first delay path and a second delay path. The delay circuit also comprises a plurality of switches, wherein each switch is coupled between different points on the first and second delay paths, and each switch is configured to turn on or off in response to a respective one of a plurality of select signals. The delay circuit further comprises a multiplexer having a first input coupled to an output of the first delay path, a second input coupled to an output of the second delay path, and an output coupled to an output of the delay circuit, wherein the multiplexer is configured to selectively couple one of the outputs of the first and second delay paths to the output of the delay circuit in response to a second select signal.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: July 19, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Guneet Singh, Yuehchun Claire Cheng, Jan Christian Diffenderfer, Vaishnav Srinivas, Robert Won Chol Kim
  • Patent number: 9379717
    Abstract: Described is an apparatus to lower power of a charge pump. The apparatus comprises: a first delay unit to receive a reference clock, the first delay unit to provide a delayed reference clock to a first sequential unit; a second delay unit to receive a feedback clock, the second delay unit to provide a delayed feedback clock to a second sequential unit; a first logic unit to receive the reference and feedback clocks, the logic unit to perform a logical OR operation on the received reference and feedback clocks, and to generate a trigger signal for a third sequential unit; and a second logic unit to receive outputs of first and second sequential units, and to generate an output coupled to the third sequential unit.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: June 28, 2016
    Assignee: Intel Corporation
    Inventors: Gennady Goltman, Yongping Fan, Kuan-Yueh Shen
  • Patent number: 9240795
    Abstract: A system and method of calibrating a phase-locked loop (PLL) having at least a phase detector, a frequency divider and a local oscillator are provided. The disclosed example includes generating a lock window signal based on a feedback signal generated by the frequency divider where the lock window signal may form an active lock window relative to each significant edge of the feedback signal, generating a sampled window signal based on samples of the lock window signal at each significant edge of a reference signal, and estimating a phase offset between the reference signal and the feedback signal based on a number of consecutive samples of the sampled window signal that are active.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: January 19, 2016
    Assignee: Silicon Laboratories, Inc.
    Inventors: Pål Øyvind Reichelt, Øyvind Janbu
  • Patent number: 9191185
    Abstract: Certain aspects of the present disclosure provide fully differential phase detectors for use in delay-locked loops, for example. One example phase detecting circuit generally includes a first input for a reference signal; a second input for an input signal to be compared with the reference signal; a set-reset (S-R) latch having a set input, a reset input, a first output, and a second output, and a delay (D) flip-flop having a logic input, a clock input, a reset input, and a logic output. The first input is connected with S-R reset input, the second input is connected with S-R set input, the first S-R output is connected with the D clock input, and the second S-R output is connected with the D reset input. The logic output of the D flip-flop indicates whether the input signal is leading or lagging the reference signal.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: November 17, 2015
    Assignee: QUALCOMM INCORPORATED
    Inventor: Jia-yi Chen
  • Patent number: 9172361
    Abstract: A phase detector includes a phase propagator circuit including a plurality of flip-flops. Each flip-flop includes a clock input configured to receive a clock signal having a different phase relative to phases of the clock signal received by other flip-flops in the plurality of flip-flops. The phase detector further includes a phase controller coupled to the clock input of each flip-flop in the plurality of flip-flops. The phase controller is configured to provide the different phases of the clock signal to the plurality of flip-flops such that the different phases are scaled exponentially relative to one another.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 27, 2015
    Assignee: Silicon Laboratories Inc.
    Inventors: Praveen Kallam, Dennis Sinitsky
  • Patent number: 9159382
    Abstract: A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system latch section latches, with a system clock, check data latched by the strobe latch section. Based on a comparison by an expected value comparison section and a determination by a delay determination section, the optimal strobe signal with the optimal delay is selected from among the delayed strobe signals produced in the strobe delay selection section. Then, data from the memory is delayed through delay circuits in a data delay selection section, thus obtaining a plurality of delayed data, and the optimal data with the optimal delay is selected from among the plurality of delayed data based on the comparison by the expected value comparison section and the determination by the delay determination section.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: October 13, 2015
    Assignee: SOCIONEXT INC.
    Inventors: Yoshihiro Kishimoto, Yuji Sekiguchi, Yoichiro Miki
  • Patent number: 9094025
    Abstract: Systems and methods herein may include or involve control circuitry that detects missing edges of reference and/or feedback clocks and may block the next N rising edges of the feedback clock or reference clock, respectively. In some implementations, a phase frequency detector (PFD) circuit comprises first circuitry including an output that outputs a missing edge signal. The first circuitry may include components arranged to detect a missing rising edge of one or both of a reference clock signal and a feedback clock signal. Second circuitry is coupled to the first circuitry and may include components arranged to generate one or both of a reference clock blocking signal and a feedback clock blocking signal based on the missing edge signal. Further, in some implementations, the blocking of the next N rising edges of the opposite clock may effectively increase the positive gain of the PFD.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: July 28, 2015
    Assignee: GSI TECHNOLOGY, INC.
    Inventor: Yi-Chi Cheng
  • Publication number: 20150070051
    Abstract: A digital phase selector circuit that switches an output clock between N input clock phases is described. The phase selector utilizes a special output mux and switches clock phases during a safe zone to avoid glitches. The phase selector is used in the feedback path of a PLL to implement functions such as spread spectrum or fractional reference clocks. An example with N=4 and an optimized latch mux is shown.
    Type: Application
    Filed: September 6, 2013
    Publication date: March 12, 2015
    Applicant: Synopsys, Inc.
    Inventors: Skye Wolfer, David A. Yokoyama-Martin
  • Patent number: 8975924
    Abstract: A phase-frequency detector (PFD) circuit is disclosed. The PFD circuit includes a PFD portion adapted to detect frequency and phase difference of two input signals and to generate control signals according to the detected frequency and phase difference and a delay and reset portion adapted to delay the generated control signals, to generate reset signals for resetting the PFD portion based on a combination of the control signals and the delayed control signals, and to provide the generated reset signals to the PFD portion.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: March 10, 2015
    Assignee: NXP B.V.
    Inventors: Louis Praamsma, Nikola Ivanisevic
  • Patent number: 8957705
    Abstract: Described is an apparatus comprising: a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first output indicating the coarse phase difference; and a second PFD, coupled to the first PFD, to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second output indicating the fine phase difference.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: February 17, 2015
    Assignee: Intel Corporation
    Inventors: Wenyan Jia, Shenggao Li, Fulvio Spagna
  • Publication number: 20150008961
    Abstract: A phase detector includes a phase comparing circuit configured to detect and output a phase difference between a first clock signal and a second clock signal, a latch circuit configured to latch an output signal of the phase comparing circuit and output a phase detection signal, and an initial voltage control circuit configured to control an initial voltage of an input terminal of the latch circuit according to a control signal.
    Type: Application
    Filed: July 7, 2014
    Publication date: January 8, 2015
    Inventors: Young-Hoon KIM, Soo-Young JANG, Chang-Sik YOO, Chun-Seok JEONG, Kang-Seol LEE
  • Patent number: 8917113
    Abstract: A phase detection device includes a clock divider configured to divide a clock signal and generate a plurality of divided clock signals, a recoverer configured to generate a recovered clock signal having substantially the same frequency as the clock signal based on the plurality of divided clock signals, and a phase detector configured to detect a phase of the recovered clock signal in response to a data strobe signal.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: December 23, 2014
    Assignee: SK Hynix Inc.
    Inventor: Keun Soo Song
  • Patent number: 8901955
    Abstract: This disclosure provides examples of circuits, devices, systems, and methods for providing high speed operation with high noise immunity. In one implementation, a circuit includes a first buffer configured to receive an incoming signal and to generate a first output signal. The circuit also includes a second buffer configured to receive the incoming signal and to generate a second output signal. The second buffer exhibits hysteresis with lower and upper thresholds. The circuit also includes an output block configured to receive the first and second output signals and to generate a third output signal. The output block is configured to switch a logic state of the third output signal in response to a transition of a logic state of the first output signal, and to lock the logic state of the third output signal until the output block receives a transition of a logic state of the second output signal.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: December 2, 2014
    Assignee: SanDisk Technologies Inc.
    Inventor: Ekram H. Bhuiyan
  • Publication number: 20140340121
    Abstract: A phase-detector circuit is disclosed. The phase-detector circuit comprises a plurality of phase comparators which detects a phase difference between receipt data and a clock signal of a plurality of clock signals having the same frequency and phase difference of a predetermined angle with each other, and generates and outputs signals for up/down signals for synchronizing a phase. The phase comparator generates and outputs a signal for the up/down signals having a pulse width including a detected phase-time difference and a predetermined delay time.
    Type: Application
    Filed: May 14, 2014
    Publication date: November 20, 2014
    Applicant: RICOH COMPANY, LTD.
    Inventor: Dan OZASA
  • Patent number: 8866511
    Abstract: A method and a system are provided for clock phase detection. A first set of delayed versions of a first clock signal is generated and a second set of delayed versions of a second clock signal is generated. The second set of delayed versions of the second clock signal is sampled using the first set of delayed versions of the first clock signal to produce an array of clock samples in a domain corresponding to the first clock signal. At least one edge indication is located within the array of clock samples.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: October 21, 2014
    Assignee: NVIDIA Corporation
    Inventor: William J. Dally
  • Patent number: 8825424
    Abstract: An apparatus for estimating data relating to a time difference between two events includes a delay line having a plurality of stages. Each stage has a delay difference between a first delay in a first part and a second delay in a second part. This delay difference is measured by a phase arbiter in each stage, which outputs an indication signal indicating whether the first event of two events in the first part precedes or succeeds a second event of the two events in the second part. A summation device is provided for summing over the indication signals of the plurality of stages to obtain a sum value. The sum value indicates a time difference estimate.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: September 2, 2014
    Assignee: Advantest (Singapore) Pte Ltd
    Inventor: Jochen Rivoir
  • Patent number: 8823564
    Abstract: A sampling circuit includes a continuous section which is a circuit for transmitting a continuous signal; a digital section for transmitting a signal which is sampled and quantized; and a sampling and holding section for transmitting a signal which is sampled but not quantized between the continuous section and the digital section. The sampling and holding section includes capacitors for accumulating charge generated by an input signal and plural switches for accumulating the charge in the capacitors. The plural switches receive plural clock signals having different operation timings and perform an ON/OFF operation in response to the supplied clock signals.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: September 2, 2014
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Junya Nakanishi, Yutaka Nakanishi
  • Publication number: 20140240003
    Abstract: A lock-on detection circuit for a phase-locked loop includes circuitry configured to receive first up and down outputs and second up and down outputs from one or more phase detectors and to determine from the first up and down outputs and the second up and down outputs how well the phase-locked loop is locked on to a reference clock.
    Type: Application
    Filed: February 21, 2014
    Publication date: August 28, 2014
    Inventors: Fredrik Buch, Cristian Albina, Yong Yuenyongsgool
  • Patent number: 8803550
    Abstract: This disclosure provides examples of circuits, devices, systems, and methods for providing high speed operation and a high noise margin. In one implementation, a circuit includes a first buffer configured to receive an incoming signal and a control signal and to generate an output signal based on the incoming signal. The first buffer exhibits a first hysteresis range while configured in a first hysteresis state and a second hysteresis range while configured in a second hysteresis state. The first buffer is configured to transition from the first to the second hysteresis state and vice versa in response to the control signal. The circuit includes a second buffer configured to receive the incoming signal and to generate the control signal based on the incoming signal. The second buffer exhibits a third hysteresis range with a lower threshold and an upper threshold.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: August 12, 2014
    Assignee: SanDisk Technologies Inc.
    Inventor: Ekram H. Bhuiyan
  • Patent number: 8795182
    Abstract: Switching is provided in a transducer array of medical diagnostic ultrasound imaging. The switching controls the formation of macro elements or aperture for scanning a plane or volume. The switches are implemented with one or more transistors. The control causes the gates of the transistor to float during the “on” connection. While on, the switch connects, allowing ultrasound signals to pass through the switch.
    Type: Grant
    Filed: May 14, 2010
    Date of Patent: August 5, 2014
    Assignee: Siemens Medical Solutions USA, Inc.
    Inventors: Haim Shafir, Christopher M. Daft, Paul A. Wagner
  • Publication number: 20140203842
    Abstract: A phase comparison circuit includes: a first flip-flop configured to receive a data signal and a clock signal; a second flip-flop configured to receive an output signal of the first flip-flop and a signal that is an inversion of logic of the clock signal; a delay circuit configured to give delay time to the data signal, in which the delay time is equal to or longer than signal delay time from a clock terminal of the first flip-flop to a Q output terminal of the first flip-flop; a first exclusive OR circuit configured to receive an output signal of the delay circuit and the output signal of the first flip-flop; and a second exclusive OR circuit configured to receive the output signal of the first flip-flop and an output signal of the second flip-flop.
    Type: Application
    Filed: January 16, 2014
    Publication date: July 24, 2014
    Applicant: Sony Corporation
    Inventor: Kenichi Maruko