Abstract: An integrated circuit includes a first subsystem including a first clock generator configured to generate a first clock signal. The integrated circuit also includes a second subsystem including a second clock generator configured to generate a second clock signal. The first subsystem includes an edge detector configured to detect an edge of the second clock signal. The first clock generator generates the first clock signal with a selected phase relative to the second clock signal based on the edge of the second clock signal.

Abstract: Timing alignment circuits for use in synchronizing output signals of high-speed dividers and other clock generators are provided. An example timing alignment circuit includes detection circuitry to receive first and second output signals, and output an error sign signal indicating whether the second output signal leads or lags the first output signal and a divide ratio slip signal. The example timing alignment circuit also includes control and aligning circuitry. The control circuitry receives a first local sync status signal and outputs a first control signal to a first component. The aligning circuitry receives the error sign signal and the divide ratio slip signal from the detection circuitry and also receives a second local sync status signal indicating when the first and second output signals are synchronized.

Abstract: A clock circuit for clock gating using a cascaded clock gating control signal, including: a first B-latch accepting, as input, a clock gating control signal and enabled by a first clock signal; a second B-latch accepting, as input, an output from the first B-latch and enabled by a second clock signal; and a first logic outputting, based on the first B-latch, a first gated clock signal; and a second logic outputting, based on the second B-latch, a second gated clock signal.

Abstract: A clock data recovery circuit includes a bang bang phase detector receiving data and a clock signal and determining whether a phase of the clock signal leads or lags a phase of the data, a digital loop filter receiving an output of the bang bang phase detector and filtering input jitter, an accumulator accumulating an output from the digital loop filter, an encoder encoding an output of the accumulator to generate a phase interpolation code, and a phase interpolator configured to generate the clock signal with an output phase in accordance with the phase interpolation code. The digital loop filter comprises a first sigma delta modulation (SDM) arithmetic block circuit connected to the bang bang phase detector.

Abstract: A comparator circuit according to this embodiment includes: a comparator element configured to output a matching signal indicating whether or not a value of a first input signal matches a value of a second input signal; a flip-flop circuit configured to hold a data of a data input terminal based on a comparator clock signal and configured to output an enable signal for stopping an operation of the comparator element; and an internal signal generation circuit configured to output an internal signal to the data input terminal based on the matching signal and an output signal output from the flip-flop circuit.

Abstract: An integrated circuit includes a first subsystem including a first clock generator configured to generate a first clock signal. The integrated circuit also includes a second subsystem including a second clock generator configured to generate a second clock signal. The first subsystem include a clock edge selector configured to determine a phase difference between the first clock signal and the second clock signal and to select, based on the phase difference, either a rising edge or a falling edge of the second clock signal to control output of data from the first subsystem to the second subsystem.

Abstract: A semiconductor memory device includes memory cells, a first circuit that includes a first latch group including first and second data latch circuits and a second latch group including third and fourth data latch circuits, and a control circuit configured to control a write operation during which first and second data to be written into the memory cells are stored in the first and second data latch circuits, respectively, wherein the first and second data are also stored in the third and fourth data latch circuits, respectively, while the first and second data stored in the first and second data latch circuits, respectively, are being written in the memory cells.

Abstract: In various time-transfer systems, one or more fixed-position time beacons broadcast radio-frequency (RF) time-transfer messages to time-keeping modules disposed in remote radio heads and other strategic locations to achieve highly reliable and accurate synchronized time, phase, and frequency transfer over a metropolitan or other wide-field area.

Abstract: A transmitter 10B always transmits a signal (data in which a dock is embedded) generated by the serializer 11 to the communication link. The receiver 20B includes a recovery circuit 22, a deserializer 23, a selector 25, and a training signal generator 32. The training signal generator 32 generates and outputs a training signal for frequency synchronization of the recovering operation of the recovery circuit 22. The selector 25 receives the signal from the transmitter 10B via the communication link and receives the training signal output from the training signal generator 32. The selector 25 selects and outputs either the received signal or the training signal according to the level of the lock signal output from the recovery circuit 22.

Abstract: According to some embodiments, a method implemented in electronic circuitry includes: receiving a first signal having a sinusoidal waveform; receiving a second signal having a sinusoidal waveform; generating a composite signal responsive to the first and second signals; determining an orthogonality adjustment coefficient based on a duty cycle of the composite signal; and applying the orthogonality adjustment coefficient to generate an adjusted second signal that is substantially orthogonal to the first signal.

Abstract: Techniques are described for accurate tracking of a radiofrequency (RF) carrier for amplitude-modulated signals in unstable reference clock environments. For example, some embodiments operate in context of clock circuits in devices configured for near-field communication (NFC) card emulation (CE) mode. The clock circuits seek to generate an internal clocking signal by tracking a clock reference, such as an RF carrier. In some cases, the clock reference can unpredictably become unreliable for periods of time, during which continued tracking of the unreliable clock reference and/or improper reacquisition can yield appreciable frequency and phase errors in the generated internal clocking signal. Some embodiments implement phase delta detection with time limiting to limit the magnitude of such errors in the internal clocking signal introduced while tracking an unreliable clock reference. Other embodiments provide feedback-pause-control (FPC) to force proper clock reference reacquisition.

Abstract: An IC chip can include a buffer and correction module that receives a set of multiphase clock signals at a given frequency, the buffer and correction module can include a differential skew detector that detects a skew between signals of the set of multiphase clock signals. The skew detector can include a set of SR latches. Differential clock signals of the set of multiphase clock signals are input into each SR latch, and the differential clock signals of the set of multiphase clock signals are set to be 180 degrees out of phase. A voltage difference between a DC component of a first output signal and a DC component of a second output signal of a respective SR latch in the set of SR latches varies as a function of the skew between the differential clock signals of the set of multiphase clock signals.

Abstract: A clocked electronic device, such as a wireless magnetic resonance (MR) receive coil (20), comprises a wireless receiver or transceiver (30) configured to receive a propagation-delayed wireless clock synchronization signal (54) comprising first and second propagation-delayed carrier signals at respective first and second carrier frequencies separated by a frequency difference, a clock (60) comprising a local oscillator (62) driving a digital counter (64), and at least one electronic signal processing component (66) configured to perform clock synchronization. This includes determining a wrap count (k) from a phase difference (?1) between phases of the first and second propagation-delayed carrier signals, unwrapping a wrapped phase (?2,wrapped) of the propagation-delayed wireless clock synchronization signal using the wrap count to generate an unwrapped phase (?2,wrapped), and synchronizing the clock using the unwrapped phase.

Abstract: A method of date-stamping reception of digital data of a signal coherently modulating the carrier or sub-carrier, and utilizing the properties of such a modulation to improve the date-stamping thereof. Thereby accurately correcting the date-stamping of a pilot sequence (known pattern), and reducing the variance on the date-stamping of the transitions of the bits.

Abstract: A digitally controlled oscillator (DCO) that generates an output frequency clock signal without drift and can be rapidly locked to an input or reference clock is described. A variable-modulus-fixed-increment form of DCO is configured to divide the frequency of a nominally fixed frequency oscillator. A constant is derived from the ratio of a fixed increment to the desired output frequency; this constant is multiplied by the frequency of the oscillator and the modulus adjusted to keep the ratio of the input clock and the output clock constant. The frequency of the oscillator is conveniently measured by counting the number of cycles between input cycles of a reference frequency. The oscillator must be greater in frequency than the expected output and is most accurate in cases where the reference frequency is low compared to the expected output frequency.

Abstract: A system for determine presence or quality of an external timing device is provided. The system may include a circuit (e.g., in a field-programmable gate array (FPGA)) having an input, an oscillator, an edge detector, a bit counter, and a calculator element. In some examples, the input may receive an input signal under test. The oscillator may advance a timer at a known rate to facilitate generation of clock samples for the input signal under test. The edge detector may measure edges of the input signal under test based on the clock samples. The circuit may include at least one bit counter to store a count associated with the measured edges for a shorter interval timer period and a longer interval timer period. The calculator element may determine presence or quality of an external timing device based on the count.

Abstract: A phase-locked loop (PLL) includes a phase-frequency detector (PFD) having a first PFD input, a second PFD input, and a PFD output. The PFD is configured to generate a first signal on the PFD output. The first signal comprises pulses having pulse widths indicative of a phase difference between signals on the first and second PFD inputs. A low pass filter (LPF) has an LPF input and an LPF output. The LPF input is coupled to the PFD output. A flip-flop has a clock input and a flip-flop output. The clock input is coupled to the LPF output. A lock-slip control circuit is coupled to the flip-flop output and to the first PFD input. The lock-slip control circuit is configured to determine phase-lock and phase-slip based at least in part on a signal on the flip-flop output.

Abstract: TDCs for converting time periods to digital values are disclosed. An example TDC includes a ring oscillator and a residue generation circuit. Each stage of the residue generation circuit is configured to operate on outputs from two different stages of the ring oscillator. The TDC further includes a counter for counting the number of times that an output of one of the stages of the ring oscillator switches between being at a first signal level and being at a second signal level during a time period that is being converted to a digital value. The TDC also includes a combiner for generating the digital value by combining a value indicative of the number of times counted by the counter and an output of the residue generation circuit. Such a TDC may have relatively low area and low power consumption compared to the conventional TDC designs, while yielding sufficiently linear behavior.

Abstract: A ring oscillator-based analog-to-digital converter (ADC). The ring oscillator-based ADC includes a ring oscillator and a transition detector. The ring oscillator may include a set of inverters coupled in a ring wherein an output of an inverter is coupled to an input of a successive inverter in the ring. The transition detector is configured to detect transitions of outputs of the inverters by comparing outputs of two separate inverters at two consecutive time instances. The transition detector may include two sets of registers configured to store outputs of the set of inverters at two consecutive time instances, respectively, and a set of comparators configured to compare the outputs stored in the two sets of registers. Each comparator may be configured to compare an output of one inverter at a first time instance and an output of another inverter at a second time instance.

Abstract: A clock recovery circuit includes a first pulse circuit, a second pulse circuit, a state change circuit connected to the first pulse circuit and the second pulse circuit and a first delay circuit connected to the state change circuit and each of the first pulse circuit and the second pulse circuit. The first pulse circuit receives data inputs to generate a first pulse signal. The second pulse circuit receives the data inputs to generate a second pulse signal. The state change circuit receives the first pulse signal and the second pulse signal and generate a first clock signal for a first transition of one of the data inputs in a first unit interval (UI). The first delay circuit receives the generated first clock signal and mask other transitions of the data inputs in the first UI.

Abstract: An apparatus for rotary encoding includes a knob configured to be rotated. The apparatus also includes multiple switches each configured to selectively form or not form a connection based on a current rotational position of the knob. The apparatus further includes a controller configured to generate or use a digital value associated with the current rotational position of the knob. The digital value is defined by which switches have or have not formed connections. Locations where the switches form the connections are selected such that the digital values uniquely identify different rotational positions of the knob and are non-sequential as the knob is rotated.

Abstract: A system includes a plurality of delay elements configured to receive an input clock signal. The system further includes an edge transition detector coupled to the plurality of delay elements. The plurality of delay elements is configured to detect the input clock signal transitioning from one value to another value. The system also includes a circuitry configured to determine a number of delay elements of the plurality of delay elements that the input clock signal propagates through prior to the input clock signal transitioning. The system also includes a logic or controller configured to determine whether a droop event has occurred based on the number of delay elements.

Abstract: A fast phase frequency includes two fast pulsed-latches, a NAND gate, and an adjustable delay circuit, where the fast pulsed-latches include a pulse generating circuit, a reset circuit, and an output latch circuit. The pulse generating circuit is configured to generate a power supply pulse signal when a rising edge of the clock signal arrives, the power supply pulse signal causing the input of the output latch circuit to be a low level. The output latch circuit is configured to maintain its current output state when the clock signal or the reset signal is invalid, and the reset circuit is configured to set the input of the output latch circuit to be a high level. By using fast pulsed-latches with clock and reset control, the fast phase frequency detector shortens the reset loop delay and increases the maximum operating frequency of the phase frequency detector.

Abstract: A system of referenceless clock and data recovery and a frequency detector thereof has been provided. The output clock of the system initially works at the lowest frequency, the frequency of the output clock is monotonically increased in accordance with the control of the frequency detector, thereby gradually approximating a target value. The edge extraction circuit receives the data signal and the clock signal, identifies the transition edges of the signals and generates a data transition signal and a clock transition signal representing the transition edges of the data signal and the transition edges of the clock signal respectively. The edge detector then determines the data period of the data signal and the clock period of the clock signal. When the data period is smaller than half of the clock period, the edge detector generates a frequency-up signal and the frequency of the output clock is increased.

Abstract: A phase to digital converter (PDC) generates a digital output that represents a phase difference between first and second clocks. The PDC includes a gated ring oscillator (GRO), which includes N signal delay elements coupled together in a ring via a logic gate, wherein a 1st signal delay element of the ring comprises an input coupled to an output of the logic gate, and wherein a Nth signal delay element of the ring comprises an output coupled to a first input of the logic gate. A convertor is coupled to the GRO and configured to generate low order bits of the digital output based on outputs of the logic gate and the N signal delay elements. A first counter includes an input coupled to an output of one of the N signal delay elements or the logic gate, wherein the first counter is configured to generate a first digital counter value.

Abstract: A PLL uses a virtual clock signal during holdover and/or startup to maintain a closed loop for the PLL and allow for phase/frequency adjustment of the PLL output through the feedback divider during holdover/startup when reference clock(s) supplied to the PLL are unavailable. The virtual clock signal is a series of digital values separated by a time period, where the digital values indicate transitions of the virtual clock signal and the time period corresponds to a period of the virtual clock signal. A selector circuit selects as a digital reference clock signal the virtual clock signal in a holdover or startup mode and another reference clock signal in normal operation.

Abstract: A comparator circuit includes a first transistor, a second transistor, a first switch, a second switch, and a timing circuit. The first transistor and the second transistor are coupled as a differential pair and are configured to compare an input signal to a hysteresis voltage. The first switch is coupled to the first transistor and is configured to selectably enable the first transistor. The second switch is coupled to the second transistor and is configured to selectably enable the second transistor. The timing circuit is coupled to the first switch and the second switch and is configured to close the first switch responsive to a signal transition at an output of the comparator circuit and close the second switch a predetermined delay time after the first switch is closed.

Abstract: The control signal edges of pull-up and pull-down output transistors are aligned by a feedback system. The feedback system works to align the edges of these pull-up and pull-down control pulses while also reducing and/or minimizing any overlap of pull-up and pull-down control pulses. The feedback system uses a proportional feedback loop and an integral feedback loop. The proportional feedback loop controls the crossover voltages of the differential clock signals used to generate the pull-up and pull-down pulses. The integral feedback loop controls the crossover voltages of the differential clock signals output by the delay elements of a delay-locked loop. These crossover voltages are controlled by the feedback loops such that the edges of the pull-down control pulses are aligned to the edges of the pull-up control pulses (and vice versa) without creating excessive overlap.

Abstract: A method includes generating first frequency metrics for a first received network clock signal using a local reference clock signal. The method includes, in response to the first received network clock signal being available and satisfying a quality metric, generating a network delay estimate using a first error estimate based on the first received network clock signal, and updating stored frequency metrics for the first received network clock signal with the first frequency metrics. The method includes generating an output clock signal based on received packets and the network delay estimate. The first frequency metrics for the first received network clock signal may include a current average frequency count, a prior average frequency count, a standard deviation of prior average frequency counts and a multiplicative constant corresponding to a number of samples used to determine the current average frequency count, prior average frequency count, and standard deviation.

Abstract: A skew control loop circuit for controlling a skew between a plurality of digital signals, and a semiconductor device, and a method of operation, for the same, may be provided. The skew control loop circuit comprises a skew detector for detecting a phase difference between the digital signals, a skew control circuit adapted for controlling an operation of the skew control loop circuit. The skew control circuit is operable in a first operating mode and in a second operating mode. The skew control loop circuit comprises also an enable input of the skew detector, wherein the enable input is adapted for receiving an enable input signal, generated by the skew control circuit, wherein the enable input is adapted for selectively enable or disable a phase detection operation of the skew detector, and wherein the enable input signal is only active during the first operating mode.

Abstract: A skew control loop circuit for controlling a skew between a plurality of digital signals, and a semiconductor device, and a method of operation, for the same, may be provided. The skew control loop circuit comprises a skew detector for detecting a phase difference between the digital signals, a skew control circuit adapted for controlling an operation of the skew control loop circuit. The skew control circuit is operable in a first operating mode and in a second operating mode. The skew control loop circuit comprises also an enable input of the skew detector, wherein the enable input is adapted for receiving an enable input signal, generated by the skew control circuit, wherein the enable input is adapted for selectively enable or disable a phase detection operation of the skew detector, and wherein the enable input signal is only active during the first operating mode.

Abstract: A bang-bang phase detector includes set-reset latch, pulse generator, flip-flop, and pulse-width extension circuits. The set-reset latch circuit has set and reset inputs receiving input signals, and a latch output providing a latch output signal whose state varies in dependence on phases of the input signals. The pulse generator circuit generates sampling pulses at timings dependent on phase of an input signal. The flip-flop circuit has a data input, a clock input connected to the pulse generator circuit receiving the sampling pulses, and an output providing a detector output signal whose state distinguishes positive and negative phase differences between input signals. The pulse-width extension circuit connects between the latch output and data input of the flip-flop circuit, and extends width of pulses of a polarity in the latch output signal to extend range of input signal phase differences over which the detector output signal distinguishes positive and negative phase differences.

Abstract: In an embodiment, a clock synchronizing circuit includes: a phase comparator including a first circuit having a first input configured to receive a data signal; and a second circuit. The first circuit is configured to detect edges of the data signal. The second circuit includes a clock generator configured to generate a clock signal with adjustable frequency, where the phase comparator is configured to compare, after detecting an edge of the data signal, an edge of the data signal with an edge of the clock signal, and where the second circuit is configured to modify a frequency of the clock signal as a function of an output signal of the phase comparator.

Abstract: A scan chain collects scan chain data from testing of a functional circuit and outputs a scan chain signal containing the scan chain data. A voltage monitor circuit operates to compare a supply voltage against a threshold and assert a reset signal when the supply voltage crosses the threshold. The reset signal resets a flip flop circuit whose output signal controls operation of a logic circuit that blocks passage of the scan chain signal to an integrated circuit probe pad and instead applies a constant logic signal to the probe pad indicating a voltage monitoring error.

Abstract: The present invention is directed to electrical circuits. More specifically, embodiments of the present invention provide a charge pump, which can be utilized as a part of a clock data recovery device. Early and late signals are used as differential switching voltage signals in the charge pump. The first switch and a second switch are used for controlling the direction of the current flowing into the loop filter. Input differential voltages to the switches are being generated with an opamp negative feedback loop. The output voltage of the first switch and the second switch is used in conjunction with a resistor to generate a charge pump current. There are other embodiments as well.

Abstract: A frequency compensator, an electronic device, and a frequency compensation method are disclosed. The frequency compensator includes a control circuit and a frequency compensation circuit. The control circuit is configured to generate a frequency control word according to an initial frequency and an target frequency. The frequency compensation circuit is configured to receive an input signal of an initial frequency, and to generate and output an output signal of a compensated frequency according to the frequency control word and the input signal of the initial frequency.

Abstract: A digital content reproduction control signal for controlling a reproduction of digital content includes: a first control signal (SG1) having a time code signal recorded therein and having a predetermined frequency; and a second control signal (SG2) having a 2n-fold frequency of the frequency of the first control signal, n representing a natural number, in which the first control signal (SG1) and the second control signal (SG2) are combined such that zero-cross points of a waveform of the first control signal (SG1) are aligned with zero-cross points of a waveform of the second control signal (SG2) on a time axis.

Abstract: A position detection apparatus of the electrostatic coupling type is provided, to detect not only a position of a pointer but also information other than the position information such as, for example, pointer pressure or side switch information. The pointer transmits two codes such that a pressure applied to a pen tip is associated with a time difference between the two codes. A position detector carries out a correlation matching operation between signals generated in reception conductors and correlation calculation codes corresponding to the two codes, to thereby detect a position on a sensor section pointed to by the pointer from a result of the correlation matching operation and based on at least one of the codes.

Abstract: Aspects of the present disclosure include a dual path phase locked loop (PLL) circuit with a switched capacitor filter topology along with systems, method, devices, and other circuits related thereto. The dual path PLL circuit includes an integral path and a proportional path. Both the integral path and proportional path include a charge pump and a loop filter. The outputs of a phase frequency detector (PFD) are sent to both charge pumps. The output of the integral path charge pump is connected to a capacitor, and the voltage on capacitor is used as the integral path control voltage for a voltage-controlled oscillator (VCO). A switched capacitor network is connected to the output of the proportional path charge pump and used to generate the proportional path control voltage for the VCO. Together, the two control voltages dictate the VCO's output frequency.

Abstract: A system and a method for detecting a low-frequency periodic signal (LFPS) include at least one comparator performing a threshold comparison on an analog input signal over a period of time. A sampling circuit generates digital signals by sampling an output of the at least one comparator. A digital detection circuit applies a set of detection rules to the digital signals. The detection rules are configured to detect a presence or an absence of an LFPS based on predefined criteria concerning characteristics of the digital signals.

Abstract: A skew control loop circuit for controlling a skew between a plurality of digital signals, and a semiconductor device, and a method of operation, for the same, may be provided. The skew control loop circuit comprises a skew detector for detecting a phase difference between the digital signals, a skew control circuit adapted for controlling an operation of the skew control loop circuit. The skew control circuit is operable in a first operating mode and in a second operating mode. The skew control loop circuit comprises also an enable input of the skew detector, wherein the enable input is adapted for receiving an enable input signal, generated by the skew control circuit, wherein the enable input is adapted for selectively enable or disable a phase detection operation of the skew detector, and wherein the enable input signal is only active during the first operating mode.

Abstract: A circuit for transmitting data in an integrated circuit device is described. The circuit comprises a first data width conversion circuit configured to receive a first portion of transmit data to be transmitted in parallel; a first parallel-in, serial-out circuit configured to receive an output of the first data width conversion circuit; a first reset timer configured to provide a first reset signal to enable resetting the first data width conversion circuit; a second data width conversion circuit configured to receive a second portion of the transmit data; a second parallel-in, serial-out circuit configured to receive an output of the second data width conversion circuit; and a second reset timer configured to provide a second reset signal to enable resetting the second data width conversion circuit.

Abstract: A sensor (100, 200) for measuring a variable generates a sensor signal (S), oscillates at a drive frequency (fx), and includes: a rate demodulator (135), which demodulates the sensor signal (S) by multiplying it by a first demodulation signal, in order to generate a rate signal (R1), which contains information about the measured variable to be measured; a quadrature demodulator (140), which demodulates the sensor signal (S) by multiplying it by a second demodulation signal shifted by 90° with respect to the first demodulation signal, to generate a quadrature signal (Q1); and an analysis circuit (170), which determines whether the quadrature signal (Q1) or a signal (Q2) derived therefrom is subject to a periodic oscillation and, if a periodic oscillation is present, outputs a status signal (Xst) having a value which indicates that the instantaneous rate signal (R1) is influenced by an external interference acting on the sensor (100, 200).

Abstract: Methods and devices for mitigating interference with a signal of a frequency hopping spread spectrum system are disclosed. A second signal is detected, and a property of the second signal is determined. At least one of a set of designated frequency channels used by the frequency hopping spread spectrum system is determined as having a property most similar to that of the second signal. The usage, by the frequency hopping spread spectrum system, of the at least one most similar designated frequency channel is then modified, for communication of data.

Abstract: A phase locked loop circuit comprising: a phase detector configured to compare the phase of an input signal with the phase of a feedback signal in order to provide an up-phase signal and a down-phase-signal; an oscillator-driver configured to: apply an up-weighting-value to the up-phase signal in order to provide a weighted-up-phase signal; apply a down-weighting-value to the down-phase signal in order to provide a weighted-down-phase signal; and combine the weighted-up-phase signal with the weighted-down-phase signal in order to provide an oscillator-driver-output-signal; and a controller configured to: set the up-weighting-value and the down-phase-weighting as a first-set-of-unequal-weighting-values, and replace the first-set-of-unequal-weighting-values with a second-set-of-unequal-weighting-values if an operating signal of the phase locked loop circuit reaches a limit-value without satisfying a threshold value.

Abstract: A serial data receiver may include an edge detector and a digital integrator. The edge detector may be configured to provide one or more edge detection signals defining an edge detection indication in response to a comparison between two successive samples of a receiver input signal. The edge detection indication may represent a detected negative edge, a detected positive edge, or no detected edge. The digital integrator may be configured to provide a receiver output signal in response to integration of the one or more edge detection signals.

Abstract: Systems and methods associated with phase frequency detection are disclosed. In one illustrative implementation, a phase frequency detection (PFD) circuit device may comprise first circuitry and second circuitry having a set input, a reset input, and an output, wherein the set input has a higher priority than the reset input, and additional circuitry arranged and operatively coupled to provide advantageous operation of the PFD circuit device. According to some implementations, for example, systems and methods with clock edge overriding reset features, extended detection range(s), and/or reduction of reverse charge after cycle slipping are provided.

Abstract: A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system latch section latches, with a system clock, check data latched by the strobe latch section. Based on a comparison by an expected value comparison section and a determination by a delay determination section, the optimal strobe signal with the optimal delay is selected from among the delayed strobe signals produced in the strobe delay selection section. Then, data from the memory is delayed through delay circuits in a data delay selection section, thus obtaining a plurality of delayed data, and the optimal data with the optimal delay is selected from among the plurality of delayed data based on the comparison by the expected value comparison section and the determination by the delay determination section.

Abstract: Described is a phase-locked loop with lower power charge pump. The phase-locked loop comprises: a phase frequency detector to compare a reference clock and a feedback clock and generate a pulse based on the comparison, a charge pump to provide a charge signal corresponding to the pulse, a bias generator to provide biasing for the charge pump, wherein the bias generator is operable to receive a bias enable signal from the phase frequency detector and the bias generator is disabled when the bias enable signal is not asserted, a loop filter coupled to the output of the charge pump to provide a control signal responsive to the charge signal, and a voltage-controlled oscillator (VCO), wherein the oscillating frequency of the VCO is controlled by the control signal.

Abstract: A system and method utilize multiple, asynchronous, voltage isolated integrated power data circuits (IPDCs) to respectively determine one or more power parameters of a multi-phase power distribution system. In at least one embodiment, the power parameters represent differences between voltage phases of a multi-phase power distribution system. In at least one embodiment, the IPDCs each sense a voltage or current from a single phase of a three-phase power distribution system. Additionally, the IPDCs are electrically isolated from each other and, thus, in at least one embodiment, can utilize voltage divider or shunt resistor sensing without being subject to high voltages representative of the difference between voltage phases. Additionally, in at least one embodiment, each of the IPDCs utilizes a separate clock signal to determine phase sequence and phase angle deltas of one or more three phase voltages of the three-phase power distribution system.