Abstract: A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system latch section latches, with a system clock, check data latched by the strobe latch section. Based on a comparison by an expected value comparison section and a determination by a delay determination section, the optimal strobe signal with the optimal delay is selected from among the delayed strobe signals produced in the strobe delay selection section. Then, data from the memory is delayed through delay circuits in a data delay selection section, thus obtaining a plurality of delayed data, and the optimal data with the optimal delay is selected from among the plurality of delayed data based on the comparison by the expected value comparison section and the determination by the delay determination section.

Abstract: In a pulse width modulation light emitting diode (LED) controller an error amplifier and output load switch are synchronously controlled to prevent service life shortening current overshoot through the LEDs and slowing discharging currents causing color temperature shifting in the light output from the LEDs. A plurality of switching arrangements for the error amplifier and the compensation network may be provided in a single integrated circuit LED dimming controller, and outputs for controlling a variety of differently configured output power switch combinations for disconnecting or shorting the LEDs, or disconnecting the output capacitor during off times of the modulated dimming control signal.

Abstract: A PLL control system is provided that implements a phase tracer module to reduce lock time and output clock jitter. A second clock signal is generated by dividing a frequency of a reference clock signal. A feedback clock signal is generated based on a high-frequency clock signal from a digitally controlled oscillator (DCO) and a PLL feedback divide number. Lead/lag determination circuitry generates a lead/lag detection result that indicates whether the feedback clock signal leads or lags the second clock signal. A skew digitizer digitizes a skew between a falling edge of the second clock signal and a rising edge of the feedback clock signal to generate a skew signal. The phase tracer module processes the lead/lag detection result and the skew signal to generate a digital control signal that controls cycle time of the DCO to change frequency of the high-frequency clock signal.

Abstract: A phase-detector circuit is disclosed. The phase-detector circuit comprises a plurality of phase comparators which detects a phase difference between receipt data and a clock signal of a plurality of clock signals having the same frequency and phase difference of a predetermined angle with each other, and generates and outputs signals for up/down signals for synchronizing a phase. The phase comparator generates and outputs a signal for the up/down signals having a pulse width including a detected phase-time difference and a predetermined delay time.

Abstract: Systems and methods herein may include or involve control circuitry that detects missing edges of reference and/or feedback clocks and may block the next N rising edges of the feedback clock or reference clock, respectively. In some implementations, a phase frequency detector (PFD) circuit comprises first circuitry including an output that outputs a missing edge signal. The first circuitry may include components arranged to detect a missing rising edge of one or both of a reference clock signal and a feedback clock signal. Second circuitry is coupled to the first circuitry and may include components arranged to generate one or both of a reference clock blocking signal and a feedback clock blocking signal based on the missing edge signal. Further, in some implementations, the blocking of the next N rising edges of the opposite clock may effectively increase the positive gain of the PFD.

Abstract: A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system latch section latches, with a system clock, check data latched by the strobe latch section. Based on a comparison by an expected value comparison section and a determination by a delay determination section, the optimal strobe signal with the optimal delay is selected from among the delayed strobe signals produced in the strobe delay selection section. Then, data from the memory is delayed through delay circuits in a data delay selection section, thus obtaining a plurality of delayed data, and the optimal data with the optimal delay is selected from among the plurality of delayed data based on the comparison by the expected value comparison section and the determination by the delay determination section.

Abstract: A pulse generation circuit for outputting a pulse signal at an output terminal, including: a PMOS, an NMOS, and a logic circuit. The PMOS has a source coupled to a first reference voltage level, a drain coupled to the output terminal, and a gate that receives a first gate control signal. The NMOS has a source coupled to a second reference voltage level, a drain coupled to the output terminal, and a gate that receives a second gate control signal. The logic circuit generates the first gate control signal according to a control signal and a first delay signal and generates the second gate control signal according to the control signal and a second delay signal. The first delay signal is relevant to the second gate control signal and the control signal. The second delay signal is relevant to the first gate control signal and the control signal.

Abstract: A current mode logic (CML) latch that includes a first transistor coupled to a second transistor, a third transistor coupled to a fourth transistor, a first capacitor connected to the first, second, third, and fourth transistors, and a second capacitor cross-coupled with the first capacitor and connected to the third and fourth transistors. The first and second transistors are configured to receive a data signal. The third and fourth transistors are configured to receive a clock signal.

Abstract: Described is an apparatus for clock synchronization. The apparatus comprises a pair of interconnects; a first die including a first phase interpolator having an output coupled to one of the interconnects; and a second die, wherein the pair of interconnects is to couple the first die to the second die.

Abstract: A DLL may include a DLL training circuit that provides a feedback signal to the DLL and receives a first delay code value from the DLL that corresponds to the delay added to the feedback signal to align a leading edge transition in the feedback signal with a leading edge transition in the reference clock signal. The DLL training circuit further provides an inverted feedback signal to the DLL and receives a second delay code value from the DLL that corresponds to the delay added to the inverted feedback signal to align a leading edge transition in the inverted feedback signal with a leading edge transition in the reference clock signal. The DLL selectively adds the delay code corresponding to the temporally smaller of the first delay code value or the second delay code value to the feedback signal to align the feedback signal with the reference clock signal.

Abstract: Systems and methods for delay control are described herein. In one embodiment, a delay circuit comprises a first delay path and a second delay path. The delay circuit also comprises a plurality of switches, wherein each switch is coupled between different points on the first and second delay paths, and each switch is configured to turn on or off in response to a respective one of a plurality of select signals. The delay circuit further comprises a multiplexer having a first input coupled to an output of the first delay path, a second input coupled to an output of the second delay path, and an output coupled to an output of the delay circuit, wherein the multiplexer is configured to selectively couple one of the outputs of the first and second delay paths to the output of the delay circuit in response to a second select signal.

Abstract: Described is an apparatus to lower power of a charge pump. The apparatus comprises: a first delay unit to receive a reference clock, the first delay unit to provide a delayed reference clock to a first sequential unit; a second delay unit to receive a feedback clock, the second delay unit to provide a delayed feedback clock to a second sequential unit; a first logic unit to receive the reference and feedback clocks, the logic unit to perform a logical OR operation on the received reference and feedback clocks, and to generate a trigger signal for a third sequential unit; and a second logic unit to receive outputs of first and second sequential units, and to generate an output coupled to the third sequential unit.

Abstract: A system and method of calibrating a phase-locked loop (PLL) having at least a phase detector, a frequency divider and a local oscillator are provided. The disclosed example includes generating a lock window signal based on a feedback signal generated by the frequency divider where the lock window signal may form an active lock window relative to each significant edge of the feedback signal, generating a sampled window signal based on samples of the lock window signal at each significant edge of a reference signal, and estimating a phase offset between the reference signal and the feedback signal based on a number of consecutive samples of the sampled window signal that are active.

Abstract: Certain aspects of the present disclosure provide fully differential phase detectors for use in delay-locked loops, for example. One example phase detecting circuit generally includes a first input for a reference signal; a second input for an input signal to be compared with the reference signal; a set-reset (S-R) latch having a set input, a reset input, a first output, and a second output, and a delay (D) flip-flop having a logic input, a clock input, a reset input, and a logic output. The first input is connected with S-R reset input, the second input is connected with S-R set input, the first S-R output is connected with the D clock input, and the second S-R output is connected with the D reset input. The logic output of the D flip-flop indicates whether the input signal is leading or lagging the reference signal.

Abstract: A phase detector includes a phase propagator circuit including a plurality of flip-flops. Each flip-flop includes a clock input configured to receive a clock signal having a different phase relative to phases of the clock signal received by other flip-flops in the plurality of flip-flops. The phase detector further includes a phase controller coupled to the clock input of each flip-flop in the plurality of flip-flops. The phase controller is configured to provide the different phases of the clock signal to the plurality of flip-flops such that the different phases are scaled exponentially relative to one another.

Abstract: A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system latch section latches, with a system clock, check data latched by the strobe latch section. Based on a comparison by an expected value comparison section and a determination by a delay determination section, the optimal strobe signal with the optimal delay is selected from among the delayed strobe signals produced in the strobe delay selection section. Then, data from the memory is delayed through delay circuits in a data delay selection section, thus obtaining a plurality of delayed data, and the optimal data with the optimal delay is selected from among the plurality of delayed data based on the comparison by the expected value comparison section and the determination by the delay determination section.

Abstract: Systems and methods herein may include or involve control circuitry that detects missing edges of reference and/or feedback clocks and may block the next N rising edges of the feedback clock or reference clock, respectively. In some implementations, a phase frequency detector (PFD) circuit comprises first circuitry including an output that outputs a missing edge signal. The first circuitry may include components arranged to detect a missing rising edge of one or both of a reference clock signal and a feedback clock signal. Second circuitry is coupled to the first circuitry and may include components arranged to generate one or both of a reference clock blocking signal and a feedback clock blocking signal based on the missing edge signal. Further, in some implementations, the blocking of the next N rising edges of the opposite clock may effectively increase the positive gain of the PFD.

Abstract: A digital phase selector circuit that switches an output clock between N input clock phases is described. The phase selector utilizes a special output mux and switches clock phases during a safe zone to avoid glitches. The phase selector is used in the feedback path of a PLL to implement functions such as spread spectrum or fractional reference clocks. An example with N=4 and an optimized latch mux is shown.

Abstract: A phase-frequency detector (PFD) circuit is disclosed. The PFD circuit includes a PFD portion adapted to detect frequency and phase difference of two input signals and to generate control signals according to the detected frequency and phase difference and a delay and reset portion adapted to delay the generated control signals, to generate reset signals for resetting the PFD portion based on a combination of the control signals and the delayed control signals, and to provide the generated reset signals to the PFD portion.

Abstract: Described is an apparatus comprising: a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first output indicating the coarse phase difference; and a second PFD, coupled to the first PFD, to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second output indicating the fine phase difference.

Abstract: A phase detector includes a phase comparing circuit configured to detect and output a phase difference between a first clock signal and a second clock signal, a latch circuit configured to latch an output signal of the phase comparing circuit and output a phase detection signal, and an initial voltage control circuit configured to control an initial voltage of an input terminal of the latch circuit according to a control signal.

Abstract: A phase detection device includes a clock divider configured to divide a clock signal and generate a plurality of divided clock signals, a recoverer configured to generate a recovered clock signal having substantially the same frequency as the clock signal based on the plurality of divided clock signals, and a phase detector configured to detect a phase of the recovered clock signal in response to a data strobe signal.

Abstract: This disclosure provides examples of circuits, devices, systems, and methods for providing high speed operation with high noise immunity. In one implementation, a circuit includes a first buffer configured to receive an incoming signal and to generate a first output signal. The circuit also includes a second buffer configured to receive the incoming signal and to generate a second output signal. The second buffer exhibits hysteresis with lower and upper thresholds. The circuit also includes an output block configured to receive the first and second output signals and to generate a third output signal. The output block is configured to switch a logic state of the third output signal in response to a transition of a logic state of the first output signal, and to lock the logic state of the third output signal until the output block receives a transition of a logic state of the second output signal.

Abstract: A phase-detector circuit is disclosed. The phase-detector circuit comprises a plurality of phase comparators which detects a phase difference between receipt data and a clock signal of a plurality of clock signals having the same frequency and phase difference of a predetermined angle with each other, and generates and outputs signals for up/down signals for synchronizing a phase. The phase comparator generates and outputs a signal for the up/down signals having a pulse width including a detected phase-time difference and a predetermined delay time.

Abstract: A method and a system are provided for clock phase detection. A first set of delayed versions of a first clock signal is generated and a second set of delayed versions of a second clock signal is generated. The second set of delayed versions of the second clock signal is sampled using the first set of delayed versions of the first clock signal to produce an array of clock samples in a domain corresponding to the first clock signal. At least one edge indication is located within the array of clock samples.

Abstract: A sampling circuit includes a continuous section which is a circuit for transmitting a continuous signal; a digital section for transmitting a signal which is sampled and quantized; and a sampling and holding section for transmitting a signal which is sampled but not quantized between the continuous section and the digital section. The sampling and holding section includes capacitors for accumulating charge generated by an input signal and plural switches for accumulating the charge in the capacitors. The plural switches receive plural clock signals having different operation timings and perform an ON/OFF operation in response to the supplied clock signals.

Abstract: An apparatus for estimating data relating to a time difference between two events includes a delay line having a plurality of stages. Each stage has a delay difference between a first delay in a first part and a second delay in a second part. This delay difference is measured by a phase arbiter in each stage, which outputs an indication signal indicating whether the first event of two events in the first part precedes or succeeds a second event of the two events in the second part. A summation device is provided for summing over the indication signals of the plurality of stages to obtain a sum value. The sum value indicates a time difference estimate.

Abstract: A lock-on detection circuit for a phase-locked loop includes circuitry configured to receive first up and down outputs and second up and down outputs from one or more phase detectors and to determine from the first up and down outputs and the second up and down outputs how well the phase-locked loop is locked on to a reference clock.

Abstract: This disclosure provides examples of circuits, devices, systems, and methods for providing high speed operation and a high noise margin. In one implementation, a circuit includes a first buffer configured to receive an incoming signal and a control signal and to generate an output signal based on the incoming signal. The first buffer exhibits a first hysteresis range while configured in a first hysteresis state and a second hysteresis range while configured in a second hysteresis state. The first buffer is configured to transition from the first to the second hysteresis state and vice versa in response to the control signal. The circuit includes a second buffer configured to receive the incoming signal and to generate the control signal based on the incoming signal. The second buffer exhibits a third hysteresis range with a lower threshold and an upper threshold.

Abstract: Switching is provided in a transducer array of medical diagnostic ultrasound imaging. The switching controls the formation of macro elements or aperture for scanning a plane or volume. The switches are implemented with one or more transistors. The control causes the gates of the transistor to float during the “on” connection. While on, the switch connects, allowing ultrasound signals to pass through the switch.

Abstract: A phase comparison circuit includes: a first flip-flop configured to receive a data signal and a clock signal; a second flip-flop configured to receive an output signal of the first flip-flop and a signal that is an inversion of logic of the clock signal; a delay circuit configured to give delay time to the data signal, in which the delay time is equal to or longer than signal delay time from a clock terminal of the first flip-flop to a Q output terminal of the first flip-flop; a first exclusive OR circuit configured to receive an output signal of the delay circuit and the output signal of the first flip-flop; and a second exclusive OR circuit configured to receive the output signal of the first flip-flop and an output signal of the second flip-flop.

Abstract: A phase frequency detector circuit includes an edge detector circuit, a plurality of phase frequency detector sub-circuits, and a decision circuit. The edge detector circuit is configured to receive a first input signal and a second input signal. The decision circuit is configured to detect whether a blind condition exits based on outputs of the edge detector circuit and outputs of the plurality of phase frequency detector sub-circuits. Responsive to a result of the decision circuit, a corresponding frequency detector sub-circuit of the plurality of phase frequency detector sub-circuit is configured to provide signals for use in determining a phase difference between the first input signal and the second input signal.

Abstract: A phase frequency detector circuit includes an edge detector circuit, a plurality of phase frequency detector sub-circuits, and a decision circuit. The edge detector circuit is configured to receive a first input signal and a second input signal. The decision circuit is configured to detect whether a blind condition exits based on outputs of the edge detector circuit and outputs of the plurality of phase frequency detector sub-circuits. Responsive to a result of the decision circuit, a corresponding frequency detector sub-circuit of the plurality of phase frequency detector sub-circuit is configured to provide signals for use in determining a phase difference between the first input signal and the second input signal.

Abstract: Systems and methods associated with control of clock signals are disclosed. In one exemplary implementation, there is provided a delay-lock-loop (DLL) and/or a delay/phase detection circuit. Moreover, such circuit may comprise digital phase detection circuitry, digital delay control circuitry, analog phase detection circuitry, and analog delay control circuitry. Implementations may include configurations that prevent transition back to the unlocked state due to jitter or noise.

Abstract: Disclosed is a phase discriminator, including: a first XOR gate connected to a trigger and a delay unit, a second XOR gate connected to the trigger and a latch, wherein the first XOR gate is a current mode logic XOR gate, the first XOR gate comprises a first offset current source circuit outputting a first adjustable offset circuit for controlling amplitude of the error signal output by the first XOR gate; and/or, the second XOR gate is a current mode logic XOR gate, the second XOR gate comprises a second offset current source circuit outputting a second adjustable offset circuit for controlling amplitude of reference signal output by the second XOR gate. Also disclosed are a clock and data recovery system and a phase adjustment method. The present invention can prevent introducing noise coupling to the voltage control oscillator (VCO) module.

Abstract: A method for reducing noise in a frequency synthesizer includes selecting a design variable k, calibrating a feedback time delay (Td), such that Td=kTVCO, where TVCO is the period of the synthesizer output signal. The method further includes estimating an instantaneous quantization error to a number of bits equal to q, defining a reference bias current of Icp/(k2q), where Icp is a charge pump current signal, and applying the estimated instantaneous quantization error to a current array to produce a down modification signal (?I). The current array is biased by the reference bias current. The down modification signal (?I) is summed with the charge pump current signal Icp to modulate a down current portion of the charge pump current signal Icp.

Abstract: The present invention provides for a solution to reduce locking time with satisfactory performance without the need for significant footprint area for the phase lock loop (PLL) circuits by boosting phase frequency detector (PFD) and charge pump (CP) gains through various circuitry configurations that employ one or more flip-flops, delay elements and advanced circuitry techniques.

Abstract: A phase frequency detector detects the difference between the edges of a fractional-rate recovered clock signal and the edges within a serial data bit stream, where the edges within the serial data bit stream correspond with the edges of a full-rate clock signal that was used to clock the serial data bit stream.

Abstract: An adaptive delay device that provides a delay to a signal based on circuit conditions such as temperature, supply voltage values and/or fabrication processes. The adaptive delay device may respond to circuit conditions by charging a capacitive device to a threshold voltage. A comparator may incorporate the adaptive delay device to provide adaptive timing for the comparator functions thereby attaining improved noise performance and/or reduce power consumption.

Abstract: A high-accuracy phase detector circuit compatible with a 1/N rate architecture is provided. The phase detector circuit has as many as N track-and-hold circuits for tracking and holding N-phase clock signals CLK—1 to CLK_N in synchronization with a rising edge of input data signal DIN. Out of the N-phase clock signals CLK—1 to CLK_N outputted from as many track-and-hold circuits, only the one whose rising edge is most synchronized with a rising edge of the input data signal DIN is selected and outputted as a phase difference signal.

Abstract: A delay locked loop (DLL) is calibrated to obtain a measure of offset error in the DLL. The offset error is compensated for in normal operation. In an embodiment, a current corresponding to the measure of offset is forced into one of a pair of paths carrying error signals representing a phase-mismatch between a reference signal and a feedback signal. In another embodiment, additional delay corresponding to the measure of offset is introduced on one of the pair of paths. Offset error is thus largely removed in normal operation of the DLL. The DLL employs an amplifier in place of a charge pump to remove systematic offset errors due to a charge pump. A phase detector in the DLL is designed such that an overlap interval of error outputs of the phase detector is at least half the period of the reference signal, thereby lending to high-frequency operation.

Abstract: A phase frequency detector circuit includes an edge detector circuit, a plurality of phase frequency detector sub-circuits, and a decision circuit. The edge detector circuit is configured to receive a first input signal and a second input signal. The decision circuit is configured to detect whether a blind condition exits based on outputs of the edge detector circuit and outputs of the plurality of phase frequency detector sub-circuits. Responsive to a result of the decision circuit, a corresponding frequency detector sub-circuit of the plurality of phase frequency detector sub-circuit is configured to provide signals for use in determining a phase difference between the first input signal and the second input signal.

Abstract: A phase-locked loop (PLL) includes PLL loop circuitry, a frequency divider, and a phase-frequency detector (PFD) that can produce both high-gain output signals to operate the PLL in a high-gain mode and normal output signals to operate the PLL in a normal (not high-gain) mode. A mode signal can be used to switch the PFD between high-gain mode and normal operational mode. When the mode signal indicates high-gain mode, the PFD output signals are extended by one or more additional clock cycles beyond their length when the mode signal indicates normal operational mode.

Abstract: A digital phase comparator is provided in which first phase difference signals and second phase difference signals are used as digital phase difference information. The first phase difference signals are generated by sampling a second clock signal with a first group of clock signals having regular intervals. The second phase difference signals are generated, using a second group of clock signals and a first group of signals which are obtained by delaying a second clock signal and a first signal generated by performing a logic operation on the first phase difference signal respectively at different regular intervals, by sampling the second group of clock signals with the first group of signals.

Abstract: The present disclosure provides a phase comparator including, a first latch, a second latch, a first detection circuit, a second detection circuit, and a charge-pump circuit having the function of a changeover switch.

Abstract: A phase frequency detector detects the difference between the edges of a fractional-rate recovered clock signal and the edges within a serial data bit stream, where the edges within the serial data bit stream correspond with the edges of a full-rate clock signal that was used to clock the serial data bit stream.

Abstract: A phase comparator is provided that solves the problem that a VCO cannot be controlled with high precision. A frequency divider frequency-divides a VCO signal applied as input to an input terminal (10) in steps, and supplies the VCO signals of each step as output. A latch unit latches the VCO signal that is applied to the input terminal (10) and each VCO signal that was supplied from the frequency divider based on a reference signal that is applied to an input terminal (11). An output unit supplies the latch results realized by the latch unit as phase difference signals that indicate phase differences of the reference signal and the VCO signals.

Abstract: Multiple flip-flops each latch input data at a time point of the corresponding clock signal. The i-th (i represents an integer) first logical gate generates an internal up signal which is asserted when the output of the (2×i?1)-th flip-flop does not match the output of the (2×i)-th flip-flop. The j-th (j represents an integer) second logical gate generates an internal down signal which is asserted when the output of the (2×j)-th flip-flop does not match the output of the (2×j+1)-th flip-flop. A third logical gate generates an up signal based upon the multiple internal up signals. A fourth logical gate generates a down signal based upon the multiple internal down signals.

Abstract: A time-domain voltage comparator for an analog-to-digital converter includes a first voltage-to-time converter configured to be connected in series with at least one time delay cell and convert an input voltage into time information; a second voltage-to-time converter configured to be connected in series with at least one time delay cell and convert an input voltage into time information; and a phase comparator configured to determine a difference between times outputted from the first voltage-to-time converter and the second voltage-to-time converter.

Abstract: The phase-frequency detector (PFD) includes a frequency detector (FD) arranged to receive orthogonal signal pairs of a reference signal and a feedback signal and estimate a frequency error between a reference signal and a feedback signal; a FD voltage-to-current converter arranged to convert the frequency error into a first current; a phase detector (PD) arranged to receive the orthogonal signal pairs and estimate a phase error between the reference signal and the feedback signal, and a PD voltage-to-current converter arranged to convert the phase error into a second current.